M5M5W816TP-55HI [RENESAS]
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM; 8388608 - BIT （ 524288 - WORD 16位） CMOS静态RAM
| 型号： | M5M5W816TP-55HI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
- Single 2.7~3.6V power supply
The M5M5W816TP is a f amily of low v oltage 8-Mbit static
RAMs organized as 524288-words by 16-bit, f abricated by
Mitsubishi's high-performance 0.18µm CMOS technology .
The M5M5W816TP is suitable for memory applications
where a simple interf acing , battery operating and battery
backup are the important design objectiv es.
- Small stand-by current: 0.1µA (2.0V, ty p.)
- No clocks, No ref resh
- Data retention supply v oltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S#, BC1# and BC2#
- Common Data I/O
The M5M5W816TP is packaged in a 44pin thin small
outline mount dev ice, with the outline of 400mil TSOP
TYPE(II). It giv es the best solution for a compaction of
mounting area as well as f lexibility of wiring pattern of
printed circuit boards.
- Three-state outputs: OR-tie capability
- OE# prev ents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 44pin 400mil TSOP TYPE(II)
Activ e
Stand-by current
Version,
Power
Access time
max.
current
Icc1
*(3.0V ty p.)
Ratings (max. @3.6V)
* Typ. (@ 3.0V)
Part name
Operating
Supply
25°C 40°C 25°C 40°C 70°C 85°C
temperature
M5M5W816TP -55HI
M5M5W816TP -70HI
M5M5W816TP -85HI
30mA
(10MHz)
5mA
55ns
70ns
85ns
I-version
-40~+85°C
0.5
1.0
2.7~3.6V
5.0
8.0
20
40
(1MHz)
* Typical parameter indicates the value for the
center of distribution, and not 100% tested.
PIN CONFIGURATION
1
44
43
42
41
40
39
38
37
A4
A3
A5
A6
A7
OE#
BC2#
BC1#
2
3
A2
A1
A0
S#
DQ1
DQ2
4
5
6
7
DQ16
DQ15
DQ14
DQ13
GND
VCC
DQ12
DQ11
DQ10
DQ9
A18
Pin
Function
8
A0 ~ A18 Address input
DQ1 ~ DQ16
9
36
35
34
33
DQ3
DQ4
10
Data input / output
11
VCC
GND
DQ5
DQ6
DQ7
Chip select input
S#
12
W#
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
13
14
32
31
OE#
15
16
30
29
BC1#
BC2#
Vcc
DQ8
W #
A15
28
27
17
18
A8
26
25
A14
A13
A12
A16
19
20
A9
A10
A11
A17
GND
Ground supply
44Pin 400mil TSOP
Outline: 44P3W
24
23
21
22
1
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
When setting BC1# and BC2# at a high lev el or S# at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply current is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
The M5M5W816TP is organized as 524288-words by 16-
bit. These dev ices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S#. The address(A0~A18) must be set up bef ore the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S# are in an activ e state(S#=L).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
byte are in a selectable mode and upper-by te are in a
non-selectable mode.
FUNCTION TABLE
S# BC1# BC2#
OE#
W#
Mode
DQ1~8 DQ9~16
High-Z High-Z
High-Z High-Z
Icc
Non selection
Non selection
H
X
X
X
X
Standby
H
H
H
H
L
L
L
L
L
X
L
L
L
L
L
L
L
L
L
H
L
L
X
L
H
H
L
H
H
L
H
H
X
X
L
H
X
L
H
X
L
Standby
Activ e
High-Z
Write
Read
Din
Dout High-Z Activ e
High-Z High-Z Activ e
High-Z Din
High-Z Dout
High-Z High-Z Activ e
L
Activ e
Activ e
Write
Read
H
H
H
L
L
L
Din
Din
Activ e
Activ e
Write
Read
Dout
Dout
L
H
High-Z High-Z Activ e
(note) "H" and "L" in this table mean VIH or VIL, respectiv ely .
"X" in this table should be "H"or "L".
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A17
A18
-
DQ
9
CLOCK
GENERATOR
DQ
16
S#
BC1#
BC2#
Vcc
W#
OE#
GND
2
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
Ta= 25°C
-0.3* ~ +4.6
cc
VI
-0.3* ~ Vcc + 0.3 (max. 4.6V)
V
Output v oltage
Power dissipation
VO
Pd
0 ~ Vcc
700
mW
°C
Operating
temperature
- 40 ~ +85
Ta
- 65 ~ +150
Storage temperature
Tstg
°C
* -3.0V in case of AC (Pulse width < 30ns)
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Units
Min
2.2
Ty p
Max
Vcc+0.2V
0.6
High-lev el input v oltage
Low-lev el input v oltage
High-lev el output v oltage
Low-lev el output v oltage
Input leakage current
VIH
VIL
VOH
VOL
II
-0.2 *
2.4
V
IOH= - 0.5mA
IOL=2mA
0.4
±1
VI =0 ~ Vcc
µA
BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc
Output leakage current
IO
±1
BC1# and BC2# < 0.2V, S# < 0.2V
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
-
-
-
-
30
5
50
15
50
15
Activ e supply current
( AC,MOS lev el )
other inputs < 0.2V or
> Vcc-0.2V
Icc1
Icc2
Output - open (duty 100%)
mA
BC1# and BC2#=VIL , S#=VIL
other pins =VIH or VIL
Output - open (duty 100%)
30
5
Activ e supply current
( AC,TTL lev el )
0.5
1.0
-
5
~ +25°C
~ +40°C
-
-
(1)
(2)
S# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
8
Stand by supply current
( AC,MOS lev el )
Icc3
Icc4
µA
BC1# and BC2# > Vcc - 0.2V
S# < 0.2V
~ +70°C
~ +85°C
-
-
20
40
other inputs = 0 ~ Vcc
-
BC1# and BC2# = VIH or S# = VIH
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
mA
-
-
2
* -1.0V in case of AC (Pulse width < 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Limits
Ty p
Symbol
Conditions
Parameter
Units
pF
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
CO
10
3
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
1TTL
Supply v oltage
2.7~3.6V
Input pulse
VIH=2.4V, VIL=0.4V
DQ
Input rise time and f all time
5ns
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Reference lev el
Output loads
VOH=VOL=1.50V
Fig.1,CL=30pF
Including scope and
jig capacitance
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
70HI
85HI
Units
55HI
Max
Parameter
Read cy cle time
Symbol
tCR
Min
55
Min
70
Max
Min
85
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
ta(S)
Address access time
Chip select 1 access time
By te control 1 access time
By te control 2 access time
55
55
55
55
30
20
20
20
20
70
70
70
70
35
25
25
25
25
85
85
85
85
45
30
30
30
30
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
Output enable access time
Output disable time after S# high
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
Output enable time af ter S# low
10
5
5
10
5
5
10
5
5
ten(BC1,2) Output enable time af ter BC1#,BC2# low
ten(OE)
tV(A)
Output enable time af ter OE# low
Data v alid time after address
10
10
10
(3) WRITE CYCLE
Limits
70HI
55HI
Min
85HI
Min
Units
Symbol
Parameter
Max
Min
Max
Max
ns
ns
ns
ns
ns
85
60
Write cy cle time
Write pulse width
55
45
70
55
tCW
tw(W)
tsu(A)
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
0
70
70
70
70
45
0
0
0
65
65
65
65
35
0
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
50
50
50
50
30
0
ns
ns
ns
ns
ns
ns
ns
0
0
0
30
30
20
20
25
25
Output disable time from W# low
Output disable time from OE# high
5
5
5
5
5
5
ns
ns
ten(W)
ten(OE)
Output enable time f rom W# high
Output enable time f rom OE# low
4
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
tCR
Read cycle
A0~18
tv (A)
ta(A)
ta(BC1)or
ta(BC2)
BC1#,BC2#
(Note3)
(Note3)
(Note3)
tdis (BC1) or tdis (BC2)
ta(S)
S#
(Note3)
(Note3)
tdis (S)
ta (OE)
OE#
(Note3)
ten (OE)
tdis (OE)
W# = "H" lev el
ten (BC1)
ten (BC2)
DQ1~16
VALID DATA
ten (S)
Write cycle
( W# control mode )
tCW
A0~18
BC1#,BC2#
S#
tsu (BC1) or tsu(BC2)
(Note3)
(Note3)
(Note3)
tsu (S)
(Note3)
OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W#
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A0~18
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,BC2#
S#
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S# low ov erlaps BC1# and/or BC2# low and W# low.
Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the falling edge of
S#, the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCW
Write cycle (S# control mode)
A0~18
BC1#, BC2#
(Note3)
(Note3)
trec (W)
tsu (S)
tsu (A)
S#
(Note5)
W#
(Note4)
(Note3)
(Note3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
7
2002.08.30
Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test conditions
Units
V
Ty p
Max
Min
2.0
2.2
Power down supply voltage
Vcc (PD)
VI (BC)
2.2V < Vcc(PD)
Byte control input BC1# & BC2#
V
V
2.0V < Vcc(PD) < 2.2V
2.2V < Vcc(PD)
Vcc(PD)
2.2
VI (S)
Chip select input S#
2.0V < Vcc(PD) < 2.2V
Vcc(PD)
0.1
~ +25°C
~ +40°C
-
-
1.5
3
Vcc=2.0V
(1)
S#
> Vcc - 0.2V,
other inputs = 0 ~ Vcc
0.2
Power down
supply current
Icc (PD)
µA
BC1# and BC2# > Vcc - 0.2V
(2)
~ +70°C
~ +85°C
-
-
-
-
15
30
S#
< 0.2V
other inputs = 0 ~ Vcc
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
ns
tsu (PD)
trec (PD)
Power down set up time
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
BC# control mode
Vcc
On the BC# control mode, the lev el of S# must be f ixed at S# > Vcc-0.2V or S# < 0.2V.
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1#
BC2#
BC1# , BC2# > Vcc-0.2V
S# control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
S# > Vcc-0.2V
S#
8
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相关型号：
M5M5W816WG-55HI#BT
512KX16 STANDARD SRAM, 55ns, PBGA48, 7.50 X 8.50 MM, 0.75 MM PITCH, ROHS COMPLIANT, CSP-48
RENESAS
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