M5M5W816TP-85HI [MITSUBISHI]
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM; 8388608 - BIT （ 524288 - WORD 16位） CMOS静态RAM
| 型号： | M5M5W816TP-85HI |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
FEATURES
DESCRIPTION
- Single 2.7~3.0V power supply
The M5M5W816TP is a f amily of low v oltage 8-Mbit static
RAMs organized as 524288-words by 16-bit, f abricated by
Mitsubishi's high-performance 0.18µm CMOS technology .
The M5M5W816TP is suitable for memory applications
where a simple interf acing , battery operating and battery
backup are the important design objectiv es.
- Small stand-by current: 0.2µA (3.0V, ty p.)
- No clocks, No ref resh
- Data retention supply v oltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S#, BC1# and BC2#
- Common Data I/O
The M5M5W816TP is packaged in a 44pin thin small
outline mount dev ice, with the outline of 400mil TSOP
TYPE(II). It giv es the best solution for a compaction of
mounting area as well as f lexibility of wiring pattern of
printed circuit boards.
- Three-state outputs: OR-tie capability
- OE# prev ents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 44pin 400mil TSOP TYPE(II)
The operating temperature range is -40~+85°C
Activ e
Stand-by current
Ratings (max.)
25°C 40°C 25°C 40°C 70°C 85°C
Version,
Power
Access time
max.
current
Icc1
*(ty p.)
* Ty pical
Part name
Operating
Supply
temperature
40mA
(10MHz)
5mA
70ns
85ns
M5M5W816TP -70HI
M5M5W816TP -85HI
I-version
-40~+85°C
0.5
1.0
2.7~3.0V
2
4
20
40
(1MHz)
* Typical parameter indicates the value for the
center of distribution, and not 100% tested.
PIN CONFIGURATION
1
44
43
A4
A3
A5
A6
2
3
42
41
A2
A1
A0
S#
DQ1
DQ2
A7
OE#
4
5
40
39
38
37
BC2#
BC1#
DQ16
DQ15
DQ14
DQ13
6
7
Pin
Function
8
A0 ~ A18 Address input
9
36
35
DQ3
DQ4
10
DQ1 ~ DQ16
Data input / output
Chip select input
34
33
32
31
VCC
GND
DQ5
DQ6
DQ7
11
12
GND
VCC
S#
W#
Write control input
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
13
14
DQ12
DQ11
DQ10
DQ9
A18
OE#
15
16
30
29
BC1#
BC2#
Vcc
DQ8
W #
A15
28
27
17
18
A8
26
25
19
20
A14
A13
A12
A9
A10
GND
Ground supply
44Pin 400mil TSOP
Outline: 44P3W
NC: No Connection
21
22
24
23
A11
A17
A16
MITSUBISHI ELECTRIC
1
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
When setting BC1# and BC2# at a high lev el or S# at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply current is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
The M5M5W816TP is organized as 524288-words by 16-
bit. These dev ices operate on a single +2.7~3.0V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S#. The address(A0~A18) must be set up bef ore the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S# are in an activ e state(S#=L).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
byte are in a selectable mode and upper-by te are in a
non-selectable mode.
FUNCTION TABLE
BC2#
OE#
BC1#
S#
W#
Mode
DQ1~8 DQ9~16
High-Z High-Z
High-Z High-Z
Icc
Non selection
Non selection
Standby
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
L
L
L
L
X
L
H
H
L
H
H
L
H
H
X
X
L
H
X
L
H
X
L
Standby
Activ e
High-Z
Write
Read
Din
Dout High-Z Activ e
High-Z High-Z Activ e
High-Z Din
High-Z Dout
High-Z High-Z Activ e
L
H
H
H
L
L
L
Activ e
Activ e
Write
Read
Write
Read
Din
Din
Activ e
Activ e
Dout
Dout
L
H
High-Z High-Z Activ e
The operating temperature range is -40 ~ +85°C
BLOCK DIAGRAM
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
524288 WORDS
x 16 BITS
A17
A18
-
DQ
9
CLOCK
GENERATOR
DQ
16
S#
BC1#
BC2#
Vcc
W#
OE#
GND
MITSUBISHI ELECTRIC
2
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Units
Conditions
Ratings
V
Supply v oltage
Input v oltage
With respect to GND
With respect to GND
With respect to GND
Ta= 25°C
-0.3* ~ +4.6
cc
VI
-0.3* ~ Vcc + 0.3 (max. 4.6V)
V
Output v oltage
Power dissipation
VO
Pd
0 ~ Vcc
700
mW
°C
Operating
temperature
- 40 ~ +85
Ta
- 65 ~ +150
Storage temperature
Tstg
°C
<
* -3.0V in case of AC (Pulse width
30ns)
=
( Vcc=2.7 ~ 3.0V, unless otherwise noted)
Limits
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Units
Min
2.2
Ty p
Max
High-lev el input v oltage
Low-lev el input v oltage
High-level output voltage
Vcc+0.2V
0.6
VIH
VIL
VOH
VOL
II
-0.2 *
2.4
V
IOH= - 0.5mA
IOL=2mA
Low-lev el output v oltage
Input leakage current
Output leakage current
0.4
±1
VI =0 ~ Vcc
µA
BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc
IO
±1
<
<
BC1# and BC2# 0.2V, S# 0.2V
=
=
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
-
-
-
-
30
5
40
10
40
10
Activ e supply current
( AC,MOS lev el )
>
<
other inputs 0.2V or
Vcc-0.2V
Icc1
=
=
Output - open (duty 100%)
mA
BC1# and BC2#=VIL , S#=VIL
other pins =VIH or VIL
Output - open (duty 100%)
30
5
Activ e supply current
( AC,TTL lev el )
Icc2
Icc3
Icc4
~ +25°C
~ +40°C
-
-
0.5
1.0
2
(1)
(2)
>
Vcc - 0.2V,
other inputs = 0 ~ Vcc
S#
=
4
Stand by supply current
( AC,MOS lev el )
µA
>
BC1# and BC2# Vcc - 0.2V
=
~ +70°C
~ +85°C
-
-
-
-
20
40
<
S# 0.2V
=
other inputs = 0 ~ Vcc
BC1# and BC2#=VIH or S#=VIH
Other inputs= 0 ~ Vcc
Stand by supply current
( AC,TTL lev el )
mA
-
-
2
<
* -3.0V in case of AC (Pulse width
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
30ns)
=
(Vcc=2.7 ~3.0V, unless otherwise noted)
Limits
CAPACITANCE
Symbol
Conditions
Parameter
Units
Ty p
Min
Max
10
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
CI
pF
CO
10
MITSUBISHI ELECTRIC
3
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~3.0V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
1TTL
Supply v oltage
2.7~3.0V
Input pulse
VIH=2.4V, VIL=0.4V
DQ
Input rise time and f all time
5ns
CL
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Reference lev el
Output loads
VOH=VOL=1.5V
Fig.1,CL=30pF
Including scope and
jig capacitance
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
85HI
70HI
Max
Units
Parameter
Read cy cle time
Address access time
Chip select 1 access time
By te control 1 access time
Symbol
Min
70
Min
85
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1,2)
ten(OE)
tV(A)
70
85
70
70
70
35
25
25
25
25
85
85
85
45
30
30
30
30
By te control 2 access time
Output enable access time
Output disable time after S# high
Output disable time after BC1# high
Output disable time after BC2# high
Output disable time after OE# high
10
5
5
10
5
5
Output enable time af ter S# low
Output enable time af ter BC1#,BC2# low
Output enable time af ter OE# low
Data v alid time after address
ns
ns
ns
10
10
*5ns in case of using either BC1# or BC2#
(3) WRITE CYCLE
Limits
70HI
85HI
Min
Units
Symbol
Parameter
Min
Max
Max
ns
ns
ns
ns
ns
85
60
Write cy cle time
Write pulse width
70
55
tCW
tw(W)
tsu(A)
Address setup time
0
70
70
70
70
45
0
0
65
65
65
65
35
0
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time from W# low
Output disable time from OE# high
ns
ns
ns
ns
ns
ns
ns
0
0
25
25
30
30
5
5
5
5
ns
ns
ten(W)
ten(OE)
Output enable time f rom W# high
Output enable time f rom OE# low
MITSUBISHI ELECTRIC
4
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
tCR
Read cycle
A0~18
tv (A)
ta(A)
ta(BC1)or
ta(BC2)
BC1#,BC2#
(Note3)
(Note3)
(Note3)
tdis (BC1) or tdis (BC2)
ta(S)
S#
(Note3)
(Note3)
tdis (S)
ta (OE)
OE#
(Note3)
ten (OE)
tdis (OE)
W# = "H" lev el
ten (BC1)
ten (BC2)
DQ1~16
VALID DATA
ten (S)
Write cycle
( W# control mode )
tCW
A0~18
BC1#,BC2#
S#
tsu (BC1) or tsu(BC2)
(Note3)
(Note3)
(Note3)
tsu (S)
(Note3)
OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
W#
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
MITSUBISHI ELECTRIC
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A0~18
tsu (BC1) or
tsu (BC2)
trec (W)
tsu (A)
BC1#,BC2#
S#
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
W#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S# low ov erlaps BC1# and/or BC2# low and W# low.
Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the falling edge of
S#, the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
6
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCW
Write cycle (S# control mode)
A0~18
BC1#, BC2#
(Note3)
(Note3)
trec (W)
tsu (S)
tsu (A)
S#
(Note5)
W#
(Note4)
(Note3)
(Note3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
MITSUBISHI ELECTRIC
7
2001.4.11
Ver. 2.0
MITSUBISHI LSIs
M5M5W816TP-70HI, 85HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test conditions
Units
V
Ty p
Max
Min
2.0
Power down supply voltage
Vcc (PD)
VI (BC)
Byte control input BC1# & BC2#
V
V
2.0
2.0
VI (S)
Chip select input S#
0.1
0.2
~ +25°C
~ +40°C
-
-
1.5
3
Vcc=2.0V
>
(1)
S#
Vcc - 0.2V,
=
Power down
supply current
other inputs = 0 ~ Vcc
Icc (PD)
µA
>
(2)
BC1# and BC2# Vcc - 0.2V
=
~ +70°C
~ +85°C
-
-
-
-
15
30
<
S#
0.2V
=
other inputs = 0 ~ Vcc
Note 2: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 2.0V, and not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
ns
tsu (PD)
trec (PD)
Power down set up time
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
BC# control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1#
BC2#
>
BC1# , BC2# Vcc-0.2V
=
S# control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
>
S# Vcc-0.2V
S#
=
MITSUBISHI ELECTRIC
8
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric
Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs
and algorithms represents information on products at the time of publication of these materials, and
are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or
an authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various
means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from
the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake. Please
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC9
相关型号：
M5M5W816WG-55HI#BT
512KX16 STANDARD SRAM, 55ns, PBGA48, 7.50 X 8.50 MM, 0.75 MM PITCH, ROHS COMPLIANT, CSP-48
RENESAS
©2020 ICPDF网 联系我们和版权申明