ISL8103IRZ-T_技术文档

DATASHEET

ISL8103

FN9246

Rev 1.00

July 21, 2008

Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers

The ISL8103 is a three-phase PWM control IC with

integrated MOSFET drivers. It provides a precision voltage

Features

• Integrated Mulitphase Power Conversion

- 1, 2, or 3 Phase Operation

regulation system for multiple applications including, but not

limited to, high current low voltage point-of-load converters,

embedded applications and other general purpose low

voltage medium to high current applications.The integration

of power MOSFET drivers into the controller IC marks a

departure from the separate PWM controller and driver

configuration of previous mulitphase product families. By

reducing the number of external parts, this integration allows

for a cost and space saving power management solution.

• Precision Output Voltage Regulation

- Differential Remote Voltage Sensing

- W0.8% System Accuracy Over-Temperature

(for REF = 0.6V and 0.9V)

- ±0.5% System Accuracy Over-Temperature

(for REF = 1.2V and 1.5V)

- Usable for Output Voltages not Exceeding 2.3V

- Adjustable Reference-Voltage Offset

Output voltage can be programmed using the on-chip DAC

or an external precision reference. A two bit code programs

the DAC reference to one of 4 possible values (0.6V, 0.9V,

1.2V and 1.5V). A unity gain, differential amplifier is provided

for remote voltage sensing, compensating for any potential

difference between remote and local grounds. The output

voltage can also be offset through the use of single external

resistor. An optional droop function is also implemented and

can be disabled for applications having less stringent output

voltage variation requirements or experiencing less severe

step loads.

• Precision Channel Current Sharing

- Uses Loss-Less r

DS(ON)

Current Sampling

• Optional Load Line (Droop) Programming

- Uses Loss-Less Inductor DCR Current Sampling

• Variable Gate-Drive Bias - 5V to 12V

• Internal or External Reference Voltage Setting

- On-Chip Adjustable Fixed DAC Reference Voltage with

2-bit Logic Input Selects from Four Fixed Reference

Voltages (0.6V, 0.9V, 1.2V, 1.5V)

A unique feature of the ISL8103 is the combined use of both

- Reference can be Changed Dynamically

- Can use an External Voltage Reference

DCR and r

current sensing. Load line voltage

DS(ON)

positioning and overcurrent protection are accomplished

through continuous inductor DCR current sensing, while

• Overcurrent Protection

r

current sensing is used for accurate channel-current

DS(ON)

• Multi-tiered Overvoltage Protection

balance. Using both methods of current sampling utilizes the

best advantages of each technique.

- OVP Pin to Drive Optional Crowbar Device

Protection features of this controller IC include a set of

sophisticated overvoltage and overcurrent protection.

Overvoltage results in the converter turning the lower

MOSFETs ON to clamp the rising output voltage and protect

the load. An OVP output is also provided to drive an optional

crowbar device. The overcurrent protection level is set

through a single external resistor. Other protection features

include protection against an open circuit on the remote

sensing inputs. Combined, these features provide advanced

protection for the output load.

• Selectable Operation Frequency up to 1.5MHz per Phase

• Digital Soft-Start

• Capable of Start-up in a Pre-Biased Load

• Pb-Free (RoHS compliant)

Applications

• High Current DDR/Chipset Core Voltage Regulators

• High Current, Low Voltage DC/DC Converters

• High Current, Low Voltage FPGA/ASIC DC/DC

Converters

FN9246 Rev 1.00

July 21, 2008

Page 1 of 28

ISL8103

Ordering Information

PART NUMBER

PART MARKING

ISL8103 CRZ

ISL8103 IRZ

TEMERATURE (°C)

0 to +70

PACKAGE

40 Ld 6x6 QFN (Pb-Free)

PKG. DWG. #

L40.6x6

ISL8103CRZ* (Note)

ISL8103IRZ* (Note)

-40 to +85

* Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinout

ISL8103

(40 LD 6X6 QFN)

TOP VIEW

40 39 38 37 36 35 34 33 32 31

3PH

2PH

1

2

3

4

5

6

7

8

9

30 BOOT1

29 PHASE1

28 PHASE2

DAC

REF

27

26

25

24

23

22

UGATE2

BOOT2

ISEN2

OFST

VCC

41

GND

COMP

FB

PVCC2

LGATE2

PHASE3

VDIFF

RGND 10

21 BOOT3

11 12 13 14 15 16 17 18 19 20

FN9246 Rev 1.00

July 21, 2008

Page 2 of 28

ISL8103

Block Diagram

ICOMP DROOP OCSET

PGOOD OVP

ENLL

ISEN AMP

100µA

0.66V

ISUM

IREF

VCC

POWER-ON

RESET

OC

PVCC1

BOOT1

UGATE1

RGND

VSEN

+1V

SOFT-START

AND

x1

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

x1

FAULT LOGIC

PHASE1

LGATE1

VDIFF

UVP

OVP

0.2V

FS

PVCC2

BOOT2

UGATE2

CLOCK AND

SAWTOOTH

GENERATOR

PWM1



SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

+150mV

x 0.82

PHASE2

LGATE2

PWM2

PWM3



REF1

REF0

DAC

2PH

3PH



CHANNEL

DETECT

DAC

PVCC3

BOOT3

UGATE3

CHANNEL

CURRENT

BALANCE

1

N

REF

FB

E/A

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

PHASE3

LGATE3

COMP

OFST



OFFSET

CHANNEL

CURRENT

SENSE

ISEN1

ISEN2 ISEN3

GND

FN9246 Rev 1.00

July 21, 2008

Page 3 of 28

ISL8103

Typical Application - ISL8103

+12V

FB

COMP

VDIFF

PVCC1

BOOT1

UGATE1

VSEN

RGND

3PH

2PH

PHASE1

ISEN1

+5V

VCC

LGATE1

OFST

FS

PVCC2

BOOT2

DAC

REF

UGATE2

ISL8103

PHASE2

ISEN2

LOAD

LGATE2

REF1

REF0

OVP

PGOOD

PVCC3

BOOT3

+12V

GND

UGATE3

PHASE3

ISEN3

ENLL

IREF

DROOP

OCSET

LGATE3

ICOMP

ISUM

FN9246 Rev 1.00

July 21, 2008

Page 4 of 28

ISL8103

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Thermal Resistance



(°C/W)

32



(°C/W)

3.5

JA

JC

QFN Package (Notes 1, 2) . . . . . . . . . .

Absolute Boot Voltage, V

. . . . . . . .GND - 0.3V to GND + 36V

BOOT

. . . . . . . . GND - 0.3V to 15V (PVCC = 12)

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Phase Voltage, V

PHASE

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT-PHASE

Upper Gate Voltage, V

. . . . V

- 0.3V to V

PHASE

UGATE

BOOT

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

Lower Gate Voltage, V

BOOT

. . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V 5%

Ambient Temperature (ISL8103CRZ) . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (ISL8103IRZ) . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested.

PARAMETER

BIAS SUPPLY AND INTERNAL OSCILLATOR

Input Bias Supply Current

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

; ENLL = high

-

15

20

mA

VCC

Gate Drive Bias Current

; ENLL = high; all gate outputs open,

= 250kHz

0.8

2.00

PVCC

F

sw

VCC POR (Power-On Reset) Threshold

PVCC POR (Power-On Reset) Threshold

VCC Rising

VCC Falling

PVCC Rising

PVCC Falling

4.25

3.75

4.25

3.75

-

4.38

3.88

4.38

3.88

1.50

66.6

4.50

4.00

4.50

4.00

-

V

%

Oscillator Ramp Amplitude (Note 3)

Maximum Duty Cycle (Note 3)

CONTROL THRESHOLDS

V

P-P

-

ENLL Rising Threshold

-

0.66

100

-

V

mV

V

ENLL Hysteresis

COMP Shutdown Threshold

COMP Falling

0.1

0.25

0.4

REFERENCE AND DAC

System Accuracy (DAC = 0.6V, 0.9V)

System Accuracy (DAC = 1.2V, 1.50V)

DAC Input Low Voltage (REF0, REF1)

DAC Input High Voltage (REF0, REF1)

External Reference (Note 3)

DROOP connected to IREF

-0.8

-0.5

-

0.8

0.5

0.4

-

%

V

-

0.8

0.6

47.5

V

-

1.75

52.5

V

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

R

= 30kfrom OFS to VCC

= 10kfrom OFS to GND

50.0

µA

OFS

FN9246 Rev 1.00

July 21, 2008

Page 5 of 28

ISL8103

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested. (Continued)

PARAMETER

ERROR AMPLIFIER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC Gain (Note 3)

R

C

= 10k to Ground

-

96

20

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product (Note 3)

Slew Rate (Note 3)

= 100pF, R = 10k toGround

L

-

= 100pF, Load = 400µA

-

3.90

-

8

Maximum Output Voltage

Minimum Output Voltage

REMOTE SENSE DIFFERENTIAL AMPLIFIER

Input Bias Current (VSEN)

Bandwidth (Note 3)

Load = 1mA

Load = -1mA

4.20

0.85

-

1.0

V

(VSEN = 1.5V)

49

-

55

20

8

60

-

µA

MHz

V/µs

Slew Rate (Note 3)

-

OVERCURRENT PROTECTION

OCSET Trip Current

93

-5

100

0

107

5

µA

OCSET Accuracy

OC Comparator Offset (OCSET and ISUM

Difference)

mV

ICOMP Offset

ISEN Amplifier Offset

-5

0

5

mV

PROTECTION

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold while IC Disabled

Overvoltage Threshold

VSEN Falling

VSEN Rising

80

-

82

3

84

-

%VID

V

1.62

1.67

1.72

VSEN Rising

DAC +

125mV

DAC +

150mV

DAC +

175mV

V

Overvoltage Hysteresis

VSEN Falling

-

50

-

mV

V

Open Sense-Line Protection Threshold

IREF Rising and Falling

VDIFF +

0.9V

VDIFF + VDIFF +

1V

1.1V

OVP Output High Drive Voltage

SWITCHING TIME

I

= 50mA, VCC = 5V

2.2

3.9

V

OVP

UGATE Rise Time (Note 3)

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

-

26

18

12

10

-

ns

RUGATE; PVCC

LGATE Rise Time (Note 3)

V

RLGATE; PVCC

UGATE Fall Time (Note 3)

V

FUGATE; PVCC

LGATE Fall Time (Note 3)

V

FLGATE; PVCC

UGATE Turn-On Non-overlap (Note 3)

LGATE Turn-On Non-overlap (Note 3)

GATE DRIVE RESISTANCE (Note 4)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

OVER TEMPERATURE SHUTDOWN

Thermal Shutdown Setpoint (Note 3)

Thermal Recovery Setpoint (Note 3)

NOTE:

; V

= 12V, 3nF Load, Adaptive

PDHUGATE PVCC

; V

PDHLGATE PVCC

V

= 12V, 150mA Source Current

1.25

0.9

2.0

1.6

3.0



PVCC

= 12V, 150mA Sink Current

= 12V, 150mA Source Current

= 12V, 150mA Sink Current

0.85

0.60

1.4

2.2

0.94

1.35

-

160

100

-

°C

3. Limits should be considered typical and are not production tested.

4. Limits established by characterization and are not production tested.

FN9246 Rev 1.00

July 21, 2008

Page 6 of 28

ISL8103

Timing Diagram

t

PDHUGATE

t

RUGATE

FUGATE

UGATE

LGATE

t

FLGATE

RLGATE

t

PDHLGATE

Simplified Power System Diagram

+12V

IN

+5V

IN

Q1

CHANNEL1

Q2

2

REF0,REF1

DAC

ENLL

OVP

Q3

Q4

PGOOD

V

OUT

CHANNEL2

ISL8103

Q5

Q6

CHANNEL3

ENLL (Pin 37)

Functional Pin Description

This pin is a threshold sensitive (approximately 0.66V) enable

input for the controller. Held low, this pin disables controller

operation. Pulled high, the pin enables the controller for

operation.

VCC (Pin 6)

Bias supply for the IC’s small-signal circuitry. Connect this

pin to a +5V supply and locally decouple using a quality

1.0µF ceramic capacitor.

FS (Pin 36)

PVCC1, PVCC2, PVCC3 (Pins 33, 24, 18)

A resistor, placed from FS to ground, will set the switching

frequency. Refer to Equation 40 and Figure 23 for proper

resistor calculation.

Power supply pins for the corresponding channel MOSFET

drive. These pins can be connected to any voltage from +5V

to +12V, depending on the desired MOSFET gate drive level.

Note that tying PVCC2 OR PVCC3 to GND has the same

effect as tying 2PH or 3PH to GND for disabling the

corresponding phase

3PH and 2PH (Pins 1, 2)

These pins decide how many phases the controller will

operate. Tying both pins to VCC allows for 3-phase operation.

Tying the 3PH pin to GND causes the controller to operate in

2-phase mode, while connecting both 3PH and 2PH GND will

allow for single phase operation.

GND (Pin 41)

Bias and reference ground for the IC.

FN9246 Rev 1.00

July 21, 2008

Page 7 of 28

ISL8103

REF0 and REF1 (Pins 40, 39)

DAC (Pin 3)

These pins make up the 2-bit input that selects the fixed

DAC reference voltage. These pins respond to TTL logic

thresholds. The ISL8103 decodes these inputs to establish

one of four fixed reference voltages; see “Table 1” on

page 12 for correspondence between REF0 and REF1

inputs and reference voltage settings.

The DAC pin is the direct output of the internal DAC. This pin

is connected to the REF pin using a 1kto 5k resistor. This

pin can be left open if an external reference is used.

REF (Pin 4)

The REF input pin is the positive input of the error amplifier.

This pin can be connected to the DAC pin using a resistor

1kto 5k when the internal DAC voltage is used as the

reference voltage. When an external voltage reference is

used, it must be connected directly to the REF pin, while the

DAC pin is left unconnected. The output voltage will be

regulated to the voltage at the REF pin unless this voltage

is greater than the voltage at the DAC pin. If an external

reference is used at this pin, its magnitude cannot exceed

1.75V.

These pins are internally pulled high, to approximately 1.2V,

by 40µA (typically) internal current sources; the internal

pull-up current decreases to 0 as the REF0 and REF1

voltages approach the internal pull-up voltage. Both REF0

and REF1 pins are compatible with external pull-up voltages

not exceeding the IC’s bias voltage (VCC).

RGND and VSEN (Pins 10, 11)

RGND and VSEN are inputs to the precision differential

remote-sense amplifier and should be connected to the

sense pins of the remote load.

A capacitor is used between the REF pin and ground to

smooth the DAC voltage during soft-start.

ICOMP, ISUM, and IREF (Pins 13, 15, 16)

OFST (Pin 5)

ISUM, IREF, and ICOMP are the DCR current sense

amplifier’s negative input, positive input, and output

respectively. For accurate DCR current sensing, connect a

resistor from each channel’s phase node to ISUM and

connect IREF to the summing point of the output inductors.

A parallel R-C feedback circuit connected between ISUM

and ICOMP will then create a voltage from IREF to ICOMP

proportional to the voltage drop across the inductor DCR.

This voltage is referred to as the droop voltage and is added

to the differential remote-sense amplifier’s output.

The OFST pin provides a means to program a DC current for

generating an offset voltage across the resistor between FB

and VDIFF. The offset current is generated via an external

resistor and precision internal voltage references. The

polarity of the offset is selected by connecting the resistor to

GND or VCC. For no offset, the OFST pin should be left

unconnected.

OCSET (Pin 12)

This is the overcurrent set pin. Placing a resistor from OCSET

to ICOMP, allows a 100µA current to flow out of this pin,

producing a voltage reference. Internal circuitry compares the

voltage at OCSET to the voltage at ISUM, and if ISUM ever

exceeds OCSET, the overcurrent protection activates.

An optional 0.001µF to 0.01µF ceramic capacitor can be

placed from the IREF pin to the ISUM pin to help reduce

common mode noise that might be introduced by the layout.

DROOP (Pin 14)

ISEN1, ISEN2 and ISEN3 (Pins 32, 25, 19)

This pin enables or disables droop. Tie this pin to the ICOMP

pin to enable droop. To disable droop, tie this pin to the IREF

pin.

These pins are used for balancing the channel currents by

sensing the current through each channel’s lower MOSFET

when it is conducting. Connect a resistor between the

ISEN1, ISEN2, and ISEN3 pins and their respective phase

node. This resistor sets a current proportional to the current

in the lower MOSFET during its conduction interval.

VDIFF (Pin 9)

VDIFF is the output of the differential remote-sense

amplifier. The voltage on this pin is equal to the difference

between VSEN and RGND added to the difference between

IREF and ICOMP. VDIFF therefore represents the VOUT

voltage plus the droop voltage.

UGATE1, UGATE2, and UGATE3 (Pins 31, 27, 20)

Connect these pins to the upper MOSFETs’ gates. These

pins are used to control the upper MOSFETs and are

monitored for shoot-through prevention purposes. Maximum

individual channel duty cycle is limited to 66%.

FB and COMP (Pin 7, 8)

The internal error amplifier’s inverting input and output

respectively. FB is connected to VDIFF through an external

R or R-C network depending on the desired type of

compensation (Type II or III). COMP is tied back to FB

through an external R-C network to compensate the

regulator.

BOOT1, BOOT2, and BOOT3 (Pins 30, 26, 21)

These pins provide the bias voltage for the upper MOSFETs’

drives. Connect these pins to appropriately-chosen external

bootstrap capacitors. Internal bootstrap diodes connected to

the PVCC pins provide the necessary bootstrap charge.

FN9246 Rev 1.00

July 21, 2008

Page 8 of 28

ISL8103

per-channel inductance and lower total output capacitance

for any performance specification.

PHASE1, PHASE2, and PHASE3 (Pins 29, 28, 22)

Connect these pins to the sources of the upper MOSFETs.

These pins are the return path for the upper MOSFETs’

drives.

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (I , I , and I

)

L1 L2 L3

combine to form the AC ripple current and the DC load

LGATE1, LGATE2, and LGATE3 (Pins 34, 23, 17)

current. The ripple component has three times the ripple

frequency of each individual channel current. Each PWM

pulse is terminated 1/3 of a cycle after the PWM pulse of the

previous phase. The peak-to-peak current for each phase is

about 7A, and the dc components of the inductor currents

combine to feed the load.

These pins are used to control the lower MOSFETs and are

monitored for shoot-through prevention purposes. Connect

these pins to the lower MOSFETs’ gates. Do not use

external series gate resistors as this might lead to

shoot-through.

PGOOD (Pin 35)

PGOOD is used as an indication of the end of soft-start. It is

an open-drain logic output that is low impedance until the

soft-start is completed and VOUT is equal to the VID setting.

Once in normal operation PGOOD indicates whether the

output voltage is within specified overvoltage and

I

+ I + I , 7A/DIV

L2 L3

L1

I

, 7A/DIV

L3

undervoltage limits. If the output voltage exceeds these limits

or a reset event occurs (such as an overcurrent event),

PGOOD becomes high impedance again. The potential at

this pin should not exceed that of the potential at VCC pin by

more than a typical forward diode drop at any time.

PWM3, 5V/DIV

I

, 7A/DIV

L2

PWM2, 5V/DIV

I

, 7A/DIV

L1

OVP (Pin 38)

PWM1, 5V/DIV

Overvoltage protection pin. This pin pulls to VCC when an

overvoltage condition is detected. Connect this pin to the

gate of an SCR or MOSFET tied across V and ground to

prevent damage to a load device.

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

IN

To understand the reduction of ripple current amplitude in the

multiphase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

Operation

Mulitphase Power Conversion

Modern low voltage DC/DC converter load current profiles

have changed to the point that the advantages of multiphase

power conversion are impossible to ignore. The technical

challenges associated with producing a single-phase

converter that is both cost-effective and thermally viable

have forced a change to the cost-saving approach of

mulitphase. The ISL8103 controller helps simplify

implementation by integrating vital functions and requiring

minimal output components. The “Block Diagram” on page 3

provides a top level view of mulitphase power conversion

using the ISL8103 controller.

V – V

  V

OUT

 V

IN

OUT

(EQ. 1)

I

= ---------------------------------------------------------

PP

L  F

SW

In Equation 1, V and V

IN

are the input and output

OUT

voltages respectively, L is the single-channel inductor value,

and F is the switching frequency.

SW

The output capacitors conduct the ripple component of the

inductor current. In the case of multiphase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

Interleaving

The switching of each channel in a mulitphase converter is

timed to be symmetrically out-of-phase with each of the

other channels. In a 3-phase converter, each channel

switches 1/3 cycle after the previous channel and 1/3 cycle

before the following channel. As a result, the three-phase

converter has a combined ripple frequency three times

greater than the ripple frequency of any one phase. In

addition, the peak-to-peak amplitude of the combined

inductor currents is reduced in proportion to the number of

phases (Equations 1 and 2). Increased ripple frequency and

lower ripple amplitude mean that the designer can use less

V – N  V

  V

OUT

IN

OUT

(EQ. 2)

I

= -------------------------------------------------------------------

C, P – P

L  F

 V

SW

IN

FN9246 Rev 1.00

July 21, 2008

Page 9 of 28

ISL8103

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multiphase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a three-phase converter combining to reduce

the total input ripple current.

terminates 1/3 of a cycle after the PWM1 pulse. The PWM3

pulse terminates 1/3 of a cycle after PWM2.

If PVCC3 is left open or connected to ground, two channel

operation is selected and the PWM2 pulse terminates 1/2 of

a cycle after the PWM1 pulse terminates. If both PVCC3 and

PVCC2 are left open or connected to ground, single channel

operation is selected. The 2PH and 3PH inputs can also be

used to accomplish this function. Once a PWM pulse

transitions low, it is held low for a minimum of 1/3 cycle. This

forced off time is required to ensure an accurate current

sample. Current sensing is described in the next section.

After the forced off time expires, the PWM output is enabled.

The PWM output state is driven by the position of the error

amplifier output signal, VCOMP, minus the current correction

signal relative to the sawtooth ramp as illustrated in Figure 3.

When the modified VCOMP voltage crosses the sawtooth

ramp, the PWM output transitions high. The internal

The converter depicted in Figure 2 delivers 1.5V to a 36A

load from a 12V input. The RMS input capacitor current is

6.1A. Compare this to a single-phase converter also

stepping down 12V to 1.5V at 36A. The single-phase

converter has a 13.3A RMS input capacitor current. The

single-phase converter must use an input capacitor bank

with twice the RMS current capacity as the equivalent

three-phase converter.

INPUT-CAPACITOR CURRENT

MOSFET driver detects the change in state of the PWM

signal and turns off the synchronous MOSFET and turns on

the upper MOSFET. The PWM signal will remain high until

the pulse termination signal marks the beginning of the next

cycle by triggering the PWM signal low.

CHANNEL 3

INPUT CURRENT

Channel Current Balance

One important benefit of mulitphase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

CHANNEL 2

INPUT CURRENT

CHANNEL 1

INPUT CURRENT

In order to realize the thermal advantage, it is important that

each channel in a multiphase converter be controlled to

carry about the same amount of current at any load level. To

achieve this, the currents through each channel must be

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 3-PHASE

CONVERTER

sampled every switching cycle. The sampled currents, I ,

n

Figures 24, 25 and 26 in the section entitled “Input Capacitor

Selection” on page 24 can be used to determine the input

capacitor RMS current based on load current, duty cycle,

and the number of channels. They are provided as aids in

determining the optimal input capacitor solution.

from each active channel are summed together and divided

by the number of active channels. The resulting cycle

average current, I

, provides a measure of the total load

AVG

current demand on the converter during each switching

cycle. Channel current balance is achieved by comparing

the sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current-

balance method is illustrated in Figure 3, with error

PWM Operation

The timing of each converter leg is set by the number of

active channels. The default channel setting for the ISL8103

is three. One switching cycle is defined as the time between

the internal PWM1 pulse termination signals. The pulse

termination signal is the internally generated clock signal

that triggers the falling edge of PWM1. The cycle time of the

pulse termination signal is the inverse of the switching

frequency set by the resistor between the FS pin and

ground. Each cycle begins when the clock signal commands

PWM1 to go low. The PWM1 transition signals the internal

Channel 1 MOSFET driver to turn off the Channel 1 upper

MOSFET and turn on theChannel 1 synchronous MOSFET.

In the default channel configuration, the PWM2 pulse

correction for Channel 1 represented. In the figure, the cycle

average current, I

, is compared with the Channel 1

AVG

sample, I , to create an error signal I

.

1

ER

The filtered error signal modifies the pulse width

commanded by V to correct any unbalance and force

COMP

toward zero. The same method for error signal

I

ER

correction is applied to each active channel.

FN9246 Rev 1.00

July 21, 2008

Page 10 of 28

ISL8103

each channel in the converter, but may not be active

depending on the status of the PVCC3 and PVCC2 pins, as

described in the “PWM Operation” on page 10.

+

PWM1

V

COMP

TO GATE

CONTROL

LOGIC

+

-

SAWTOOTH SIGNAL

f(s)

FILTER

V

I

IN

3

I

ER

+

I

r

AVG

CHANNEL N

UPPER MOSFET

DSON



I

N

= I x-------------------------

SEN

L

-

R

ISEN

I

n

I

2

I

L

I

SAMPLE

&

HOLD

1

ISEN(n)

NOTE: Channel 2 and 3 are optional.

-

R

ISEN

FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

-

+

I x r

L

DSON

+

Current Sampling

CHANNEL N

LOWER MOSFET

In order to realize proper current balance, the currents in

each channel must be sampled every switching cycle. This

sampling occurs during the forced off-time, following a PWM

transition low. During this time the current sense amplifier

uses the ISEN inputs to reproduce a signal proportional to

ISL8103 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

FIGURE 5. ISL8103 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY FOR CURRENT BALANCE

the inductor current, I . This sensed current, I

a scaled version of the inductor current. The sample window

, is simply

L

SEN

The ISL8103 senses the channel load current by sampling

the voltage across the lower MOSFET r

, as shown in

DS(ON)

opens exactly 1/6 of the switching period, t , after the

SW

Figure 5. A ground-referenced operational amplifier, internal

to the ISL8103, is connected to the PHASE node through a

PWM transitions low. The sample window then stays open

the rest of the switching cycle until PWM transitions high

again, as illustrated in Figure 4.

resistor, R

. The voltage across R

is equivalent to

ISEN

of the lower MOSFET

the voltage drop across the r

DS(ON)

while it is conducting. The resulting current into the ISEN pin

The sampled current, at the end of the t

, is

SAMPLE

proportional to the inductor current and is held until the next

switching period sample. The sampled current is used only

for channel current balance.

is proportional to the channel current, I . The ISEN current is

sampled and held as described in “Current Sampling” on

L

page 11. From Figure 5, the following equation for I is

n

derived where I is the channel current.

L

r

DSON

----------------------

I

= I



L

(EQ. 3)

n

R

I

L

ISEN

Output Voltage Setting

The ISL8103 uses a digital to analog converter (DAC) to

generate a reference voltage based on the logic signals at

the REF1, REF0 pins. The DAC decodes the 2-bit logic

signals into one of the discrete voltages shown in Table 1 on

page 12. Each REF0 and REF1 pins are pulled up to an

internal 1.2V voltage by weak current sources (40µA current,

decreasing to 0 as the voltage at the REF0, REF1 pins

varies from 0 to the internal 1.2V pull-up voltage). External

pull-up resistors or active-high output stages can augment

the pull-up current sources, up to a voltage of 5V. The DAC

pin must be connected to REF pin through a 1kto 5k

resistor and a filter capacitor (0.022µF) is connected

between REF and GND.

PWM

SWITCHING PERIOD

I

SEN

SAMPLING PERIOD

NEW SAMPLE

CURRENT

OLD SAMPLE

CURRENT

TIME

FIGURE 4. SAMPLE AND HOLD TIMING

The ISL8103 accommodates the use of external voltage

reference connected to REF pin if a different output voltage

is required. The DAC voltage must be set at least as high as

the external reference. The error amp internal noninverting

input is the lower of REF or (DAC +300mV).

The ISL8103 supports MOSFET r

sample each channel’s current for channel current balance.

The internal circuitry, shown in Figure 5 represents Channel

N of an N-channel converter. This circuitry is repeated for

current sensing to

DS(ON)

FN9246 Rev 1.00

July 21, 2008

Page 11 of 28

ISL8103

A third method for setting the output voltage is to use a

circuitry that controls voltage regulation is illustrated in

Figure 6.

resistor divider (R , R ) from the output terminal (V

)

P1 S1

OUT

to VSEN pin to set the output voltage level as shown in

Figure 6. This method is good for generating voltages up to

2.3V (with the REF voltage set to 1.5V).

(EQ. 5)

V

= V

 V

– V

OFST DROOP

OUT

REF

EXTERNAL CIRCUIT

ISL8103 INTERNAL CIRCUIT

R

C

1

For this case, the output voltage can be obtained as shown

in Equation 4.

2

COMP

DAC

VID DAC

R + R



P1

S1

R

(EQ. 4)



---------------------------------

V

= V



V

– V

OFS DROOP



OUT

REF

P1

REF

It is recommended to choose resistor values of less than

+

-

C

REF

FB

500 for R and R resistors in order to get better output

S1 P1

voltage DC accuracy.

V

COMP

+

TABLE 1. ISL8103 DAC VOLTAGE SELECTION TABLE

R

1

ERROR AMPLIFIER

V

OFS

I

OFS

-

VDIFF

VSEN

REF1

REF0

VDAC

0.600V

0.900V

1.200V

1.500V

0

1

0

1

0

1

R

S1

+

R

P1

V

OUT

-

RGND

DIFFERENTIAL

-

Voltage Regulation

REMOTE-SENSE

AMPLIFIER

DROOP

In order to regulate the output voltage to a specified level, the

ISL8103 uses the integrating compensation network shown in

Figure 6. This compensation network insures that the steady

state error in the output voltage is limited only to the error in

the reference voltage (output of the DAC or the external

voltage reference) and offset errors in the OFS current

source, remote sense and error amplifiers. Intersil specifies

the guaranteed tolerance of the ISL8103 to include the

combined tolerances of each of these elements, except when

an external reference or voltage divider is used, then the

tolerances of these components has to be taken into account.

-

V

DROOP

+

IREF

+

ICOMP

ISENSE

C

SUM

AMP

-

ISUM

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

The ISL8103 incorporates an internal differential

Load-Line (Droop) Regulation

remote-sense amplifier in the feedback path. The amplifier

removes the voltage error encountered when measuring the

output voltage relative to the controller ground reference

point, resulting in a more accurate means of sensing output

voltage. Connect the microprocessor sense pins to the

non-inverting input, VSEN, and inverting input, RGND, of the

remote-sense amplifier. The droop voltage, VDROOP, also

feeds into the remote-sense amplifier. The remote-sense

output, VDIFF, is therefore equal to the sum of the output

In some high current applications, a requirement on a

precisely controlled output impedance is imposed. This

dependence of output voltage on load current is often

termed “droop” or “load line” regulation.

The Droop is an optional feature in the ISL8103. It can be

enabled by connecting ICOMP pin to DROOP pin as shown

in Figure 6. To disable it, connect the DROOP pin to IREF

pin.

voltage, V

, and the droop voltage. VDIFF is connected to

OUT

As shown in Figure 6, a voltage, V

total current in all active channels, I , feeds into the

, proportional to the

DROOP

the inverting input of the error amplifier through an external

resistor.

OUT

differential remote-sense amplifier. The resulting voltage at

the output of the remote-sense amplifier is the sum of the

output voltage and the droop voltage. As Equation 4 shows,

feeding this voltage into the compensation network causes

the regulator to adjust the output voltage so that it’s equal to

the reference voltage minus the droop voltage.

The output of the error amplifier, V

, is compared to the

COMP

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers

and regulate the converter output so that the voltage at FB is

equal to the voltage at REF. This will regulate the output

voltage to be equal to Equation 5. The internal and external

FN9246 Rev 1.00

July 21, 2008

Page 12 of 28

ISL8103

The droop voltage, V

current through the output inductors. This is accomplished

by using a continuous DCR current sensing method.

, is created by sensing the

DROOP

-

V (s)

L

I

OUT

V

L1

DCR

PHASE1

INDUCTOR

OUT

Inductor windings have a characteristic distributed

resistance or DCR (Direct Current Resistance). For

simplicity, the inductor DCR is considered as a separate

lumped quantity, as shown in Figure 7. The channel current,

I

L1

R

C

S

OUT

L2

DCR

PHASE2

ISUM

INDUCTOR

L2

I , flowing through the inductor, passes through the DCR.

L

Equation 6 shows the s-domain equivalent voltage, V ,

L

R

S

across the inductor.

(EQ. 6)

V s = I  s  L + DCR

L

The inductor DCR is important because the voltage dropped

across it is proportional to the channel current. By using a

simple R-C network and a current sense amplifier, as shown

in Figure 7, the voltage drop across all of the inductors DCRs

can be extracted. The output of the current sense amplifier,

R

COMP

C

COMP

ICOMP

-

DROOP

V

DROOP

C

SUM

(Optional)

V

, can be shown to be proportional to the channel

DROOP

+

IREF

currents I , I , and I , shown in Equation 7.

L1 L2 L3

(EQ. 7)

s  L







ISL8103

-------------

+ 1

R



DCR

COMP

------------------------------------------------------------------------- -----------------------

V

s =



 I + I + I   DCR

DROOP

L1 L2 L3

s  R

 C

+ 1

R

COMP

S

FIGURE 7. DCR SENSING CONFIGURATION

By simply adjusting the value of R , the load line can be set

S

If the R-C network components are selected such that the

R-C time constant matches the inductor L/DCR time

to any level, giving the converter the right amount of droop at

all load currents. It may also be necessary to compensate for

any changes in DCR due to temperature. These changes

cause the load line to be skewed, and cause the R-C time

constant to not match the L/DCR time constant. If this

becomes a problem a simple negative temperature

constant, then V

is equal to the sum of the voltage

DROOP

drops across the individual DCRs, multiplied by a gain. As

Equation 8 shows, V

total output current, I

is therefore proportional to the

DROOP

.

OUT

R

COMP

R

S

coefficient resistor network can be used in the place of

(EQ. 8)

--------------------

V

=

 I

 DCR

OUT

DROOP

R

to compensate for the rise in DCR due to

COMP

temperature.

Output Voltage Offset Programming

The ISL8103 allows the designer to accurately adjust the

offset voltage by connecting a resistor, R

pin to VCC or GND. When R

OFS

, from the OFS

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.5V. This

causes a proportional current (I ) to flow into the OFS pin

OFS

is connected to ground, the

and out of the FB pin. If R

OFS

voltage across it is regulated to 0.5V, and I

flows into the

OFS

FB pin and out of the OFS pin. The offset current flowing

through the resistor between VDIFF and FB will generate

the desired offset voltage which is equal to the product

(I

OFS

x R ). These functions are shown in Figures 8 and 9.

1

FN9246 Rev 1.00

July 21, 2008

Page 13 of 28

ISL8103

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

VDIFF

The integrated drivers incorporate a unique adaptive

deadtime control technique to minimize deadtime, resulting

in high efficiency from the reduced freewheeling time of the

lower MOSFET body-diode conduction, and to prevent the

upper and lower MOSFETs from conducting simultaneously.

This is accomplished by ensuring either rising gate turns on

its MOSFET with minimum and sufficient delay after the

other has turned off.

+

OFS

-

V

R

I

1

VREF

E/A

FB

OFS

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is

released to rise. An auto-zero comparator is used to correct

-

1.5V

+

the r

drop in the phase voltage preventing false

+

-

DS(ON)

detection of the -0.3V phase level during r

0.5V

conduction

DS(ON)

OFS

ISL8103

period. In the case of zero current, the UGATE is released

after 35ns delay of the LGATE dropping below 0.5V. During

the phase detection, the disturbance of LGATE falling

transition on the PHASE node is blanked out to prevent

falsely tripping. Once the PHASE is high, the advanced

adaptive shoot-through circuitry monitors the PHASE and

UGATE voltages during a PWM falling edge and the

subsequent UGATE turn-off. If either the UGATE falls to less

than 1.75V above the PHASE or the PHASE falls to less than

+0.8V, the LGATE is released to turn on.

R

OFS

GND

VCC

GND

FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

VDIFF

-

V

R

OFS

+

1

VREF

Internal Bootstrap Device

E/A

All three integrated drivers feature an internal bootstrap

schottky diode. Simply adding an external capacitor across

the BOOT and PHASE pins completes the bootstrap circuit.

The bootstrap function is also designed to prevent the

bootstrap capacitor from overcharging due to the large

negative swing at the PHASE node. This reduces voltage

stress on the boot to phase pins.

FB

I

OFS

VCC

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 5V and its capacitance value can be

chosen from the following equation:

-

R

OFS

1.5V

+

-

0.5V

OFS

ISL8103

Q

GATE

-------------------------------------

C

Q



BOOT_CAP

V

GND

VCC

BOOT_CAP

(EQ. 11)

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

Q

PVCC



G1^

=

N

--------------------------------

GATE

Q1

V

GS1

Once the desired output offset voltage has been determined,

where Q is the amount of gate charge per upper MOSFET

G1

use the following formulas to set R

:

OFS

at V

gate-source voltage and N is the number of

GS1

Q1

control MOSFETs. The V

BOOT_CAP

term is defined as the

For Positive Offset (connect R

OFS

to GND):

allowable droop in the rail of the upper gate drive. Figure 10

shows the boot capacitor ripple voltage as a function of boot

capacitor value and total upper MOSFET gate charge.

0.5  R

1

(EQ. 9)

--------------------------

R

=

OFS

V

OFFSET

For Negative Offset (connect R

to VCC):

OFS

1.5  R

1

--------------------------

R

=

(EQ. 10)

OFS

V

OFFSET

FN9246 Rev 1.00

July 21, 2008

Page 14 of 28

ISL8103

1.6

1.4

1.2

1.0

0.8

0.6

0.4

ISL8103 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

PVCC1

+12V

POR

CIRCUIT

ENABLE

10.7k

COMPARATOR

Q

= 100nC

GATE

ENLL

+

-

50nC

0.2

0.0

1.40k

20nC

0.66V

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

V (V)

BOOT_CAP

SOFT-START

AND

FAULT LOGIC

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

Gate Drive Voltage Versatility

The ISL8103 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

FIGURE 11. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (ENLL) FUNCTION

2. The voltage on ENLL must be above 0.66V. The EN input

allows for power sequencing between the controller bias

voltage and another voltage rail. The enable comparator

holds the ISL8103 in shutdown until the voltage at ENLL

rises above 0.66V. The enable comparator has 100mV of

hysteresis to prevent bounce.

Initialization

Prior to initialization, proper conditions must exist on the

ENLL, VCC, PVCC and the REF0 and REF1 pins. When the

conditions are met, the controller begins soft-start. Once the

output voltage is within the proper window of operation, the

controller asserts PGOOD.

3. The driver bias voltage applied at the PVCC pins must

reach the internal power-on reset (POR) rising threshold.

In order for the ISL8103 to begin operation, PVCC1 is the

only pin that is required to have a voltage applied that

exceeds POR. However, for 2 or 3-phase operation

PVCC2 and PVCC3 must also exceed the POR

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL8103 is

released from shutdown mode.

threshold. Hysteresis between the rising and falling

thresholds assure that once enabled, the ISL8103 will not

inadvertently turn off unless the PVCC bias voltage drops

substantially (see “Electrical Specifications” on page 5).

When each of these conditions is true, the controller

immediately begins the soft-start sequence.

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL8103 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL8103 will not inadvertently turn off unless the bias

voltage drops substantially (see “Electrical

Soft-Start

During soft-start, the DAC voltage ramps linearly from zero

to the programmed level. The PWM signals remain in the

high-impedance state until the controller detects that the

ramping DAC level has reached the output-voltage level.

This protects the system against the large, negative inductor

currents that would otherwise occur when starting with a

pre-existing charge on the output as the controller attempted

to regulate to zero volts at the beginning of the soft-start

Specifications” on page 5).

cycle. The Output soft-start time, t , begins with a delay

SS

period equal to 64 switching cycles after the ENLL has

exceeded its POR level, followed by a linear ramp with a rate

determined by the switching period, 1/F

.

sw

FN9246 Rev 1.00

July 21, 2008

Page 15 of 28

ISL8103

Fault Monitoring and Protection

64 + DAC  1280

The ISL8103 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to the load.

(EQ. 12)

-------------------------------------------

t

=

SS

F

SW

For example, a regulator with 450kHz switching frequency

having REF voltage set to 1.2V has t equal to 3.55ms.

SS

* Connect DROOP to IREF

to disable the Droop feature.

A 100mV offset exists on the remote-sense amplifier at the

beginning of soft-start and ramps to zero during the first 640

cycles of soft-start (704 cycles following enable). This

prevents the large inrush current that would otherwise occur

should the output voltage start out with a slight negative

bias.

R

OCSET

DROOP*

ICOMP

OCSET

100µA

V

-

OCSET

+

IREF

ISUM

+

ISEN

-

V

DROOP

The ISL8103 also has the ability to start up into a

+

pre-charged output as shown in Figure 12, without causing

any unnecessary disturbance. The FB pin is monitored

during soft-start, and should it be higher than the equivalent

internal ramping reference voltage, the output drives hold

both MOSFETs off. Once the internal ramping reference

exceeds the FB pin potential, the output drives are enabled,

allowing the output to ramp from the pre-charged level to the

final level dictated by the reference setting. Should the

output be pre-charged to a level exceeding the reference

setting, the output drives are enabled at the end of the

soft-start period, leading to an abrupt correction in the output

voltage down to the “reference set” level.

OC

+

-

VDIFF

+1V

DAC + 150mV

SOFT-START, FAULT

AND CONTROL LOGIC

V

OVP

-

OV

UV

VSEN

RGND

OUTPUT PRECHARGED

ABOVE DAC LEVEL

+

PGOOD

+

-

x1

-

OUTPUT PRECHARGED

BELOW DAC LEVEL

+

0.82 x DAC

ISL8103 INTERNAL CIRCUITRY

V

(0.5V/DIV)

GND>

OUT

FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY

ENLL (5V/DIV)

One common power good indicator is provided for linking to

external system monitors. The schematic in Figure 13

outlines the interaction between the fault monitors and the

power-good signal

T1 T2

T3

FIGURE 12. SOFT-START WAVEFORMS FOR ISL8103-BASED

MULITPHASE CONVERTER

Power-Good Signal

The power good pin (PGOOD) is an open-drain logic output

that transitions high when the converter is operating after

soft-start. PGOOD pulls low during shutdown and releases

high after a successful soft-start. PGOOD transitions low

when an undervoltage, overvoltage, or overcurrent condition

is detected or when the controller is disabled by a reset from

ENLL or POR. If after an undervoltage or overvoltage event

occurs the output returns to within under and overvoltage

limits, PGOOD will return high.

FN9246 Rev 1.00

July 21, 2008

Page 16 of 28

ISL8103

If VSEN or RGND become opened, VDIFF falls, causing the

duty cycle to increase and the output voltage on IREF to

increase. If the voltage on IREF exceeds “VDIFF+1V”, the

controller will shut down. Once the voltage on IREF falls

below “VDIFF+1V”, the ISL8103 will restart at the beginning

of soft-start.

Undervoltage Detection

The undervoltage threshold is set at 82% of the REF

voltage. When the output voltage (VSEN-RGND) is below

the undervoltage threshold, PGOOD gets pulled low. No

other action is taken by the controller. PGOOD will return

high if the output voltage rises above 85% of the REF

voltage.

Overcurrent Protection

The ISL8103 detects overcurrent events by comparing the

Overvoltage Protection

droop voltage, V

, to the OCSET voltage, V

, as

DROOP

OCSET

The ISL8103 constantly monitors the difference between the

VSEN and RGND voltages to detect if an overvoltage event

occurs. During soft-start, while the DAC/REF is ramping up,

the overvoltage trip level is the higher of REF plus 150mV or

shown in Figure 13. The droop voltage, set by the external

current sensing circuitry, is proportional to the output current

as shown in Equation 8. A constant 100µA flows through

R

, creating the OCSET voltage. When the droop

OCSET

a fixed voltage, V

. The fixed voltage, V , is 1.67V.

OVP OVP

voltage exceeds the OCSET voltage, the overcurrent

protection circuitry activates. Since the droop voltage is

proportional to the output current, the overcurrent trip level,

Upon successful soft-start, the overvoltage trip level is only

REF plus 150mV. OVP releases 50mV below its trip point if it

was “REF plus 150mV” that tripped it, and releases 100mV

I

, can be set by selecting the proper value for R ,

MAX OCSET

below its trip point if it was the fixed voltage, V

, that

OVP

as shown in Equation 13.

tripped it. Actions are taken by the ISL8103 to protect the

load when an overvoltage condition occurs, until the output

voltage falls back within set limits.

I

 R

 DCR

COMP

MAX

(EQ. 13)

---------------------------------------------------------

R

=

OCSET

100A  R

S

At the inception of an overvoltage event, all LGATE signals

are commanded high, and the PGOOD signal is driven low.

This causes the controller to turn on the lower MOSFETs

and pull the output voltage below a level that might cause

damage to the load. The LGATE outputs remain high until

VDIFF falls to within the overvoltage limits explained above.

The ISL8103 will continue to protect the load in this fashion

as long as the overvoltage condition recurs.

Once the output current exceeds the overcurrent trip level,

will exceed V , and a comparator will trigger

V

DROOP

OCSET

the converter to begin overcurrent protection procedures. At

the beginning of overcurrent shutdown, the controller turns

off both upper and lower MOSFETs. The system remains in

this state for a period of 4096 switching cycles. If the

controller is still enabled at the end of this wait period, it will

attempt a soft-start (as shown in Figure 14). If the fault

remains, the trip-retry cycles will continue indefinitely until

either the controller is disabled or the fault is cleared. Note

that the energy delivered during trip-retry cycling is much

less than during full-load operation, so there is no thermal

hazard.

Once an overvoltage condition ends the ISL8103 continues

normal operation and PGOOD returns high.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the

ISL8103 is designed to protect the load from any overvoltage

events that may occur. This is accomplished by means of an

internal 10k resistor tied from PHASE to LGATE, which

turns on the lower MOSFET to control the output voltage

until the overvoltage event ceases or the input power supply

cuts off. For complete protection, the low side MOSFET

should have a gate threshold well below the maximum

voltage rating of the load/microprocessor.

OUTPUT CURRENT

0A

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

OUTPUT VOLTAGE

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL8103 is designed to detect this

and shut down the controller. This event is detected by

monitoring the voltage on the IREF pin, which is a local

0V

FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE

version of V

OUT

sensed at the outputs of the inductors.

FN9246 Rev 1.00

July 21, 2008

Page 17 of 28

ISL8103

General Design Guide

I

M

N

PP

2

M

PP

2













--------

P

= V

 F



----- + --------  t + ----- –

 t

d2

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and

example board layouts for many applications.

LOW 2

DON

SW

d1





N

(EQ. 15)

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of P and P

.

LOW,2

LOW,1

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the

DS(ON)

Power Stages

upper-MOSFET losses are due to currents conducted

across the input voltage (V ) during switching. Since a

The first step in designing a mulitphase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

the maximum amount of load current. Generally speaking,

the most economical solutions are those in which each

phase handles between 25A and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and

heat-dissipating surfaces.

IN

substantially higher portion of the upper-MOSFET losses are

dependent on switching frequency, the power calculation is

more complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode

reverse-recovery charge, Q , and the upper MOSFET

rr

r

conduction loss.

DS(ON)

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 16,

the required time for this commutation is t and the

1

approximated associated power loss is P

.

UP,1

t

I













1

M

PP

2







(EQ. 16)

P

 V



 F

SW

----

----- + --------

UP,1

IN



2

N

MOSFETs

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 17, the

2

approximate power loss is P

.

UP,2

I

t

I















P – P

2

M

(EQ. 17)

P

 V



 F

SW

-------------

----

2









----- –

UP,2

IN

LOWER MOSFET POWER CALCULATION

N

The calculation for the approximate power loss in the lower

MOSFET can be simplified, since virtually all of the loss in

the lower MOSFET is due to current conducted through the

A third component involves the lower MOSFET

reverse-recovery charge, Q . Since the inductor current has

rr

fully commutated to the upper MOSFET before the lower-

channel resistance (r

). In Equation 14, I is the

DS(ON)

M

MOSFET body diode can recover all of Q , it is conducted

rr

maximum continuous output current, I is the peak-to-peak

PP

through the upper MOSFET across V . The power

IN

inductor current (see Equation 1), and d is the duty cycle

dissipated as a result is P

.

UP,3

(V

/V ).

OUT IN

(EQ. 18)

P

= V  Q  F

IN rr SW

2

UP,3

I

 1 – d













I

·

L, P – P

(EQ. 14)

M

P

= r



 1 – d + -----------------------------------------

-----

LOW 1

DSON

12

N

Finally, the resistive part of the upper MOSFET is given in

Equation 19 as P

.

UP,4

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

2













I

P – P

M

(EQ. 19)

P

 r

 d 

DSON

+

-------------

-----

UP,4

12

N

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 16, 17, 18 and 19. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

diode forward voltage at I , V

, the switching

M

D(ON)

frequency, F , and the length of dead times, t and t , at

SW d1 d2

the beginning and the end of the lower-MOSFET conduction

interval respectively.

FN9246 Rev 1.00

July 21, 2008

Page 18 of 28

ISL8103

Package Power Dissipation

PVCC

BOOT

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of three

drivers in the controller package, the total power dissipated

by all three drivers must be less than the maximum

allowable power dissipation for the QFN package.

D

C

GD

R

HI1

G

UGATE

C

DS

R

LO1

R

GI1

C

G1

GS

Q1

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of +125°C. The maximum allowable IC power

dissipation for the 6x6 QFN package is approximately 4W at

room temperature. See “Layout Considerations” on page 25

for thermal transfer improvement suggestions.

S

PHASE

FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PVCC

D

C

GD

When designing the ISL8103 into an application, it is

recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

R

HI2

G

LGATE

C

DS

R

LO2

R

GI2

C

G2

GS

Q2

P

, due to the gate charge of MOSFETs and the

Qg_TOT

S

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 20

and 21, respectively.

FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

P

= P

+ P

+ I  VCC

Qg_TOT

Qg_Q1

Qg_Q2 Q

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in

the controller itself is the power dissipated in the upper drive

3

2

(EQ. 20)

--

P

=

 Q

 PVCC  F

 N

Q1 PHASE

Qg_Q1

Qg_Q2

G1

SW

path resistance, P

, the lower drive path resistance,

DR_UP

= Q

 PVCC  F

 N

PHASE

G2

SW

Q2

P

, and in the boot strap diode, P

. The rest of the

DR_UP

BOOT

power will be dissipated by the external gate resistors (R

G1

and R ) of

and R ) and the internal gate resistors (R

G2 GI1

GI2

(EQ. 21)

the MOSFETs. Figures 15 and 16 show the typical upper

and lower gate drives turn-on transition path. The total power

3







--

I

=

 Q

 N

+ Q

 N

 F

+ I

SW Q

DR

G1

G2

Q2

PHASE



Q1

2

dissipation in the controller itself, P , can be roughly

DR

estimated as shown in Equation 22.

In Equations 20 and 21, P

is the total upper gate drive

Qg_Q1

is the total lower gate drive power

power loss and P

Qg_Q2

loss; the gate charge (Q and Q ) is defined at the

particular gate to source drive voltage PVCC in the

G1 G2

P

= P

+ P

+ I  VCC

BOOT Q

DR

DR_UP

P

DR_LOW

corresponding MOSFET data sheet; I is the driver total

Q

Qg_Q1

quiescent current with no load at both drive outputs; N

Q1

---------------------

P

=

BOOT

3

and N are the number of upper and lower MOSFETs per

Q2

phase, respectively; N

PHASE

is the number of active

R

P

Qg_Q1









HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

P

=

+







DR_UP

phases. The I VCC product is the quiescent power of the

R

+ R

R

+ R

EXT1

3

Q*

HI1

EXT1

LO1

(EQ. 22)

controller without capacitive load and is typically 75mW at

300kHz.

R

P

Qg_Q2









HI2

LO2

-------------------------------------- --------------------------------------- ---------------------

P

+





DR_LOW

R

+ R

R

+ R

EXT2

2



HI2

EXT2

LO2

R

GI2

GI1

-------------

R

= R

+

R

= R

+

EXT1

G1

EXT2

G2

N

Q1

Q2

FN9246 Rev 1.00

July 21, 2008

Page 19 of 28

ISL8103

output inductor DCR of each channel (As described in

“Load-Line (Droop) Regulation” on page 12” ). As Figure 7

illustrates, an R-C network is required to accurately sense

the inductor DCR voltage and convert this information into a

droop voltage, which is proportional to the total output

current.

Current Balancing Component Selection

The ISL8103 senses the channel load current by sampling

the voltage across the lower MOSFET r

, as shown in

DS(ON)

Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and

ISEN3. The resistors connected between these pins and the

respective phase nodes determine the gains in the channel

current balance loop.

Choosing the components for this current sense network is a

two step process. First, R

chosen so that the time constant of this R -C

network matches the time constant of the inductor L/DCR.

and C

must be

COMP

Select values for these resistors based on the room

COMP COMP

temperature r

of the lower MOSFETs; the full load

DS(ON)

operating current, I ; and the number of phases, N using

FL

Then the resistor R must be chosen to set the current

S

Equation 23.

sense network gain, obtaining the desired full load droop

voltage. Follow the steps below to choose the component

values for this R-C network.

r

I

FL

N

DSON

(EQ. 23)

----------------------- -------

R

=



ISEN

–

6

50  10

1. Choose an arbitrary value for C

value is 0.01µF.

. The recommended

COMP

V

IN

CHANNEL N

UPPER MOSFET

2. Plug the inductor L and DCR component values, and the

values for C chosen in steps 1, into Equation 25 to

COMP

calculate the value for R

.

I

L

COMP

L

(EQ. 25)

R

= ---------------------------------------

COMP

ISEN(n)

DCR  C

COMP

R

ISEN

3. Use the new value for R

COMP

obtained from Equation 25,

as well as the desired full load current, I , full load droop

-

FL

ISL8103

voltage, V

calculate the value for R .

, and inductor DCR in Equation 26 to

I x r

DROOP

L

DSON

S

+

CHANNEL N

LOWER MOSFET

I

FL

(EQ. 26)

------------------------

R

=

 R

 DCR

COMP

S

V

DROOP

FIGURE 17. ISL8103 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY

Due to errors in the inductance or DCR it may be necessary

to adjust the value of R to match the time constants

COMP

In certain circumstances, it may be necessary to adjust the

value of one or more ISEN resistors. When the components

of one or more channels are inhibited from effectively

dissipating their heat so that the affected channels run hotter

correctly. The effects of time constant mismatch can be seen

in the form of droop overshoot or undershoot during the

initial load transient spike, as shown in Figure 18. Follow the

steps below to ensure the R-C and inductor L/DCR time

constants are matched accurately.

than desired, choose new, smaller values of R

for the

ISEN

affected phases (see the section entitled Channel Current

Balance). Choose R in proportion to the desired

ISEN,2

1. Capture a transient event with the oscilloscope set to

about L/DCR/2 (sec/div). For example, with L = 1µH and

DCR = 1m, set the oscilloscope to 500µs/div.

decrease in temperature rise in order to cause proportionally

less current to flow in the hotter phase.

2. Record V1 and V2 as shown in Figure 18.

T

2

(EQ. 24)

----------

R

= R



ISEN,2

ISEN

3. Select a new value, R

, for the time constant

COMP,2

T

1

resistor based on the original value, R

, using the

COMP,1

following equation.

In Equation 24, make sure that T is the desired

2

V

temperature rise above the ambient temperature, and T is

1

(EQ. 27)

----------

R

= R



COMP 1

COMP 2

V

the measured temperature rise above the ambient

temperature. While a single adjustment according to

Equation 24 is usually sufficient, it may occasionally be

2

4. Replace R

with the new value and check to see that

the error is corrected. Repeat the procedure if necessary.

COMP

necessary to adjust R

two or more times to achieve

ISEN

optimal thermal balance between all channels.

After choosing a new value for R , it will most likely be

COMP

necessary to adjust the value of R to obtain the desired full

load droop voltage. Use Equation 26 to obtain the new value

S

Load Line Regulation Component Selection (DCR

Current Sensing)

for R

S.

For accurate load line regulation, the ISL8103 senses the

total output current by detecting the voltage across the

FN9246 Rev 1.00

July 21, 2008

Page 20 of 28

ISL8103

yields a solution that is always stable with very close to ideal

transient performance.

The feedback resistor, R₁, has already been chosen as

outlined in “Load-Line (Droop) Regulation” on page 12.

Select a target bandwidth for the compensated system, F .

V

2

0

V

1

The target bandwidth must be large enough to assure

adequate transient performance, but smaller than 1/3 of the

per-channel switching frequency. The values of the

compensation components depend on the relationships of

V

OUT

F to the L-C double pole frequency and the ESR zero

frequency. For each of the following three, there is a

0

I

TRAN

separate set of equations for the compensation components.

I

1

--------------------------- > F

Case 1:

0

2  L  C

2  F  V

 L  C

0

OSC

-----------------------------------------------------------

R

C

= R



2

1

0.66  V

FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR

IN

0.66  V

IN

= ------------------------------------------------

Compensation

2  V

 R  f

OSC

1

0

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in “Load-Line (Droop) Regulation” on page 12,

there are two distinct methods for achieving these goals.

1

---------------------------

 F < ---------------------------------

Case 2:

0

2  C  ESR

2  L  C

2

V

 2  F  L  C

0

OSC

---------------------------------------------------------------

= R 

1

R

C

(EQ. 28)

2

1

0.66  V

IN

Compensating the Load-Line Regulated Converter

0.66  V

IN

= -------------------------------------------------------------------------------

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter L-C resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

2

0

2

2  F  V

 R  L  C

OSC

1

F > ---------------------------------

0

2  C  ESR

2  F  V

 L

OSC

0

-----------------------------------------------

= R 

1

R

C

Case 3:

2

compensation components, R and C .

0.66  V  ESR

2

1

IN

0.66  V  ESR 

C

IN

C

(Optional)

= --------------------------------------------------------------

2  V  R  F

2



0

L

OSC

1

C

1

In Equation 28, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

R

2

COMP

FB

the bulk output filter capacitance; and V is the peak-to-

PP

peak sawtooth signal amplitude as described in the

“Electrical Specifications” on page 5.

ISL8103

R

1

Once selected, the compensation values in Equations 28

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

VDIFF

FIGURE 19. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL8103 CIRCUIT

improved by making adjustments to R . Slowly increase the

2

value of R while observing the transient performance on an

2

oscilloscope until no further improvement is noted. Normally,

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C

poles and the ESR zero of the voltage mode approximation,

C will not need adjustment. Keep the value of C from

Equations 28 unless some performance issue is noted.

1

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (see Figure 19). Keep

a position available for C , and be prepared to install a high

2

frequency capacitor of between 22pF and 150pF in case any

leading edge jitter problem is noted.

FN9246 Rev 1.00

July 21, 2008

Page 21 of 28

ISL8103

Compensating the Converter operating without

Load-Line Regulation

C

2

The ISL8103 multiphase converter operating without load

line regulation behaves in a similar manner to a

voltage-mode controller. This section highlights the design

consideration for a voltage-mode controller requiring external

compensation. To address a broad range of applications, a

type-3 feedback network is recommended (see Figure 20).

C

R

3

R

C

2

1

COMP

-

R

FB

1

+

E/A

C

2

VREF

C

R

1

2

COMP

FB

VDIFF

-

RGND

VSEN

C

3

+

R

1

ISL8103

R

3

VDIFF

V

OSCILLATOR

OUT

V

IN

V

OSC

FIGURE 20. COMPENSATION CONFIGURATION FOR

NON-LOAD-LINE REGULATED ISL8103 CIRCUIT

PWM

CIRCUIT

L

DCR

UGATE

PHASE

Figure 21 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable, with a

small number of adjustments, to the mulitphase ISL8103

HALF-BRIDGE

DRIVE

C

circuit. The output voltage (V

) is regulated to the reference

ESR

OUT

LGATE

voltage, VREF, level. The error amplifier output (COMP pin

voltage) is compared with the oscillator (OSC) modified

saw-tooth wave to provide a pulse-width modulated wave with

ISL8103

EXTERNAL CIRCUIT

an amplitude of V at the PHASE node. The PWM wave is

IN

smoothed by the output filter (L and C). The output filter

capacitor bank’s equivalent series resistance is represented by

the series resistor E.

FIGURE 21. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

C ) in Figure 20 and 21. Use the following guidelines for

3

locating the poles and zeros of the compensation network:

The modulator transfer function is the small-signal transfer

function of V

/V

. This function is dominated by a DC

V /V , and shaped by the output

OUT COMP

1. Select a value for R (1k to 5k, typically). Calculate

1

gain, given by d

MAX IN OSC

filter, with a double pole break frequency at F and a zero at

value for R for desired converter bandwidth (F ).

2

0

LC

. For the purpose of this analysis, L and DCR represent

V

 R  F

1 0

 V  F

IN LC

OSC

(EQ. 30)

F

---------------------------------------------

=

CE

R

2

d

MAX

the individual channel inductance and its DCR divided by 3

(equivalent parallel value of the three output inductors), while

C and ESR represents the total output capacitance and its

equivalent series resistance.

If setting the output voltage to be equal to the reference

set voltage as shown in Figure 21, the design procedure

can be followed as presented. However, when setting the

output voltage via a resistor divider placed at the input of

the differential amplifier (as shown in Figure 6), in order

to compensate for the attenuation introduced by the

1

(EQ. 29)

---------------------------

F

=

---------------------------------

F

=

LC

CE

2  C  ESR

2  L  C

resistor divider, the obtained R value needs be

2

The compensation network consists of the error amplifier

(internal to the ISL8103) and the external R -R , C -C

multiplied by a factor of (R +R )/R . The remainder of

P

S

P

the calculations remain unchanged, as long as the

1

3

1

3

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

frequency (F ; typically 0.1 to 0.3 of F ) and adequate phase

compensated R value is used.

2

2. Calculate C such that F is placed at a fraction of the F

,

1

Z1 LC

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

0

SW

LC

margin (better than 45°). Phase margin is the difference

between the closed loop phase at F and +180°. The

desired number). The higher the quality factor of the output

filter and/or the higher the ratio F /F , the lower the F

CE LC

Z1

0dB

frequency (to maximize phase boost at F ).

equations that follow relate the compensation network’s poles,

zeros and gain to the components (R , R , R , C , C , and

LC

1

2

3

1

2

----------------------------------------------

(EQ. 31)

C

=

1

2  R  0.5  F

2

LC

FN9246 Rev 1.00

July 21, 2008

Page 22 of 28

ISL8103

3. Calculate C such that F is placed at F

.

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

2

P1

CE

F

P1

F

Z1 Z2

P2

C

1

(EQ. 32)

-------------------------------------------------------

=

C

2

2  R  C  F – 1

CE

2

1

4. Calculate R such that F is placed at F . Calculate C

3

Z2

LC

such that F is placed below F

(typically, 0.5 to 1.0

P2 SW

times F ). F

SW

represents the per-channel switching

SW

frequency. Change the numerical factor to reflect desired

R2

-------









20log

d

 V

IN

R1

MAX

20log---------------------------------

placement of this pole. Placement of F lower in

P2

V

0

OSC

frequency helps reduce the gain of the compensation

network at high frequency, in turn reducing the HF ripple

component at the COMP pin and minimizing resultant

duty cycle jitter.

G

FB

G

CL

G

MOD

R

1

LOG

---------------------

R

=

F

0

FREQUENCY

LC

CE

3

F

SW

------------

– 1

F

(EQ. 33)

LC

FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

1

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

------------------------------------------------

2  R  0.7  F

C

=

3

SW

It is recommended a mathematical model is used to plot the

loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

frequency response of the modulator (G

), feedback

MOD

compensation (G ) and closed-loop response (G ):

FB

CL

the per-channel switching frequency, F

.

SW

Output Filter Design

d

 V

1 + sf  ESR  C

MAX

V

IN

----------------------------- -----------------------------------------------------------------------------------------------------------

G

f =



The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

MOD

2

OSC

1 + sf  ESR + DCR  C + s f  L  C

1 + sf  R  C

2

1

----------------------------------------------------

G

f =



FB

sf  R  C + C 

(EQ. 34)

1

2

1 + sf  R + R   C

1

3

-------------------------------------------------------------------------------------------------------------------------



C

 C

2

+ C

2













1

--------------------

1 + sf  R  C   1 + sf  R 

2



3

C



1

G

f = G

f  G f

MOD FB

where sf = 2  f  j

CL

In high-speed converters, the output capacitor bank is

usually the most costly (and often the largest) part of the

circuit. Output filter design begins with minimizing the cost of

this part of the circuit. The critical load parameters in

choosing the output capacitors are the maximum size of the

load step, I, the load-current slew rate, di/dt, and the

maximum allowable output-voltage deviation under transient

COMPENSATION BREAK FREQUENCY EQUATIONS

1

--------------------------------------------

F

=

------------------------------

F

=

P1

P2

Z1

C

 C

2

2  R  C

1

2

1

--------------------

2  R



2

C

+ C

1

2

1

(EQ. 35)

-------------------------------------------------

2  R + R   C

------------------------------

2  R  C

F

=

Z2

1

3

loading, V

. Capacitors are characterized according to

Figure 22 shows an asymptotic plot of the DC/DC

MAX

converter’s gain vs. frequency. The actual Modulator Gain

has a high gain peak dependent on the quality factor (Q) of

the output filter, which is not shown. Using the above

guidelines should yield a compensation gain similar to the

curve plotted. The open loop error amplifier gain bounds the

their capacitance, ESR, and ESL (equivalent series

inductance).

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total

compensation gain. Check the compensation gain at F

P2

against the capabilities of the error amplifier. The closed loop

gain, G , is constructed on the log-log graph of Figure 22

CL

by adding the modulator gain, G

(in dB), to the feedback

MOD

compensation gain, G (in dB). This is equivalent to

FB

multiplying the modulator transfer function and the

compensation transfer function and then plotting the

resulting gain.

output-voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

FN9246 Rev 1.00

July 21, 2008

Page 23 of 28

ISL8103

response, the output voltage initially deviates by an amount

as shown in Equation 36.





1.25  N  C

(EQ. 39)





---------------------------------

L 



V

– I  ESR  V – V

MAX

IN

O

2









I

di

----

(EQ. 36)

V  ESL  + ESR  I

dt

Switching Frequency

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper MOSFET loss calculation. These effects are

outlined in “MOSFETs” on page 18, and they establish the

upper limit for the switching frequency. The lower limit is

established by the requirement for fast transient response

and small output-voltage ripple as outlined in “Output Filter

Design” on page 23. Choose the lowest switching frequency

that allows the regulator to meet the transient-response

requirements.

The filter capacitor must have sufficiently low ESL and ESR

so that V < V

.

MAX

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

Switching frequency is determined by the selection of the

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor ac ripple current (see “Interleaving” on

page 9” and Equation 2), a voltage develops across the bulk

frequency-setting resistor, R . Figure 23 and Equation 40

FS

are provided to assist in selecting the correct value for R ..

FS







10.61 – 1.035  logF

SW

(EQ. 40)

R

= 10

FS

capacitor ESR equal to I

(ESR). Thus, once the output

C,P-P

capacitors are selected, the maximum allowable ripple

voltage, V , determines the lower limit on the

PP(MAX)

inductance as shown in Equation 37.

200

100

50





F



V



V

– N  V

IN

OUT



(EQ. 37)

L

ESR

--------------------------------------------------------------------





 V  V

IN P – PMAX

SW

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

20

10

V

. This places an upper limit on inductance.

MAX

Equation 38 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 39

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

100k

500k

1M

2M

200k

SWITCHING FREQUENCY (Hz)

FIGURE 23. R vs SWITCHING FREQUENCY

FS

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the AC component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

2  N  C  V

O

(EQ. 38)

---------------------------------

L 



V

– I  ESR

MAX

2





I

FN9246 Rev 1.00

July 21, 2008

Page 24 of 28

ISL8103

0.6

0.4

0.2

0

0.3

I

= 0

I

= 0.5 I

O

L,P-P

I

= 0.25 I

= 0.75 I

O

0.2

0.1

0

I

= 0

L,P-P

= 0.5 I

O

= 0.75 I

O

0

0.2

0.4

0.6

IN

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V /V

)

O

DUTY CYCLE (V

V

)

IN/

O

FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS

FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 3-PHASE CONVERTER

CURRENT FOR SINGLE-PHASE CONVERTER

For a three-phase design, use Figure 24 to determine the

input-capacitor RMS current requirement set by the duty

Low ESL, high-frequency ceramic capacitors are needed in

addition to the input bulk capacitors to suppress leading and

falling edge voltage spikes. The spikes result from the high

current slew rate produced by the upper MOSFET turn on

and off. Place them as close as possible to each upper

MOSFET drain to minimize board parasitics and maximize

suppression.

cycle, maximum sustained output current (I ), and the ratio

O

of the peak-to-peak inductor current (I

) to I . Select a

L,P-P

O

bulk capacitor with a ripple current rating which will minimize

the total number of input capacitors required to support the

RMS current calculated. The voltage rating of the capacitors

should also be at least 1.25 times greater than the maximum

input voltage. Figures 25 and 26 provide the same input

RMS current information for two-phase and single-phase

designs respectively. Use the same approach for selecting

the bulk capacitor type and number.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes.

0.3

0.2

0.1

I

= 0

L,P-P

= 0.5 I

O

= 0.75 I

O

There are two sets of critical components in a DC/DC

converter using a ISL8103 controller. The power

components are the most critical because they switch large

amounts of energy. Next are small signal components that

connect to sensitive nodes or supply critical bypassing

current and signal coupling.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

V

)

O

IN/

FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

It is important to have a symmetrical layout, preferably with

the controller equidistantly located from the three power

trains it controls. Equally important are the gate drive lines

(UGATE, LGATE, PHASE): since they drive the power train

FN9246 Rev 1.00

July 21, 2008

Page 25 of 28

ISL8103

MOSFETs using short, high current pulses, it is important to

size them as large and as short as possible to reduce their

overall impedance and inductance. Extra care should be

given to the LGATE traces in particular since keeping the

impedance and inductance of these traces helps to

significantly reduce the possibility of shoot-through.

Equidistant placement of the controller to the three power

trains also helps to keep these traces equally short (equal

impedances, resulting in similar driving of both sets of

MOSFETs).

their respective controller pins, since they belong to a

high-impedance circuit loop, sensitive to EMI pick-up. It is

also important to place current sense components close to

their respective pins on the ISL8103, including the RISEN

resistors, RS, RCOMP, CCOMP. For proper current sharing

route three separate symmetrical as possible traces from the

corresponding phase node for each RISEN.

A multi-layer printed circuit board is recommended. Figure 27

shows the connections of the critical components for the

converter. Note that capacitors C

and C could

xxIN

xxOUT

The power components should be placed first. Locate the

input capacitors close to the power switches. Minimize the

length of the connections between the input capacitors, CIN,

and the power switches. Locate the output inductors and

output capacitors between the MOSFETs and the load.

Locate the high-frequency decoupling capacitors (ceramic)

as close as practicable to the decoupling target, making use

of the shortest connection paths to any internal planes, such

as vias to GND immediately next, or even onto the capacitor

solder pad.

each represent numerous physical capacitors. Dedicate one

solid layer, usually the one underneath the component side

of the board, for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this

plane into smaller islands of common voltage levels. Keep

the metal runs from the PHASE terminal to inductor L

OUT

short. The power plane should support the input power and

output power nodes. Use copper filled polygons on the top

and bottom circuit layers for the phase nodes. Use the

remaining printed circuit layers for small signal wiring. The

wiring traces from the IC to the MOSFETs’ gates and

sources should be sized to carry at least one ampere of

current (0.02” to 0.05”).

The critical small components include the bypass capacitors

for VCC and PVCC. Locate the bypass capacitors, CBP,

close to the device. It is especially important to locate the

components associated with the feedback circuit close to

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9246 Rev 1.00

July 21, 2008

Page 26 of 28

ISL8103

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

KEY

R

1

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

C

2

+12V

R

C

2

1

C

HF01

FB

COMP

VDIFF

PVCC1

BOOT1

C

BIN1

C

HF1

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

C

BOOT1

VSEN

RGND

UGATE1

3PH

2PH

PHASE1

ISEN1

L

OUT1

+5V

VCC

R

ISEN1

C

HF0

LGATE1

R

OFST

FS

+12V

C

HF02

PVCC2

BOOT2

C

BIN2

C

R

HF2

FS

C

BOOT2

DAC

REF

UGATE2

ISL8103

R

REF

PHASE2

ISEN2

L

OUT2

C

(C

)

HFOUT

BOUT

C

REF

R

ISEN2

LGATE2

LOAD

REF1

REF0

+12V

OVP

PGOOD

C

HF03

C

BIN3

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION PATH)

PVCC3

BOOT3

C

HF3

+12V

GND

C

BOOT3

UGATE3

PHASE3

ISEN3

ENLL

IREF

L

OUT3

R

ISEN3

DROOP

OCSET ICOMP

LGATE3

ISUM

R

S

R

C

COMP

R

S

R

OCSET

R

S

C

COMP

SUM

FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9246 Rev 1.00

July 21, 2008

Page 27 of 28

ISL8103

Package Outline Drawing

L40.6x6

40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 10/06

4X

4.5

6.00

0.50

36X

A

6

B

31

40

PIN #1 INDEX AREA

6

30

1

PIN 1

INDEX AREA

4 . 10 ± 0 . 15

21

10

(4X)

0.15

11

20

0.10 M C A B

TOP VIEW

40X 0 . 4 ± 0 . 1

4

0 . 23 +0 . 07 / -0 . 05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

0 . 90 ± 0 . 1

BASE PLANE

( 5 . 8 TYP )

(

SEATING PLANE

0.08 C

SIDE VIEW

0 . 2 REF

4 . 10 )

( 36X 0 . 5 )

5

C

0 . 00 MIN.

0 . 05 MAX.

( 40X 0 . 23 )

DETAIL "X"

( 40X 0 . 6 )

NOTES:

TYPICAL RECOMMENDED LAND PATTERN

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9246 Rev 1.00

July 21, 2008

Page 28 of 28


型号：	ISL8103IRZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	SWITCHING CONTROLLER, 1500kHz SWITCHING FREQ-MAX, PQCC40, 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220VJJD-2, QFN-40 开关
文件：	总28页 (文件大小：1282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL8103IRZ-T [RENESAS]

相关型号：

ISL8104

ISL8104CBZ

ISL8104CBZ-T

ISL8104CRZ

ISL8104EVAL1Z

ISL8104EVAL2Z

ISL8104IBZ

ISL8104IRZ

ISL8105

ISL8105A

ISL8105ACBZ

ISL8105ACRZ