ISL8104IBZ_技术文档

ISL8104

®

Data Sheet

February 13, 2006

FN9257.0

Synchronous Buck Pulse-Width

Modulator (PWM) Controller

Features

• Operates from an +8V ±5% to +14V ±10% Input

The ISL8104 is a high performance synchronous controller

for demanding DC/DC converter applications. It provides

overcurrent fault protection and is designed to safely start-up

into prebiased output loads.

• Excellent Output Voltage Regulation

- 0.597V Internal Reference

- ±1% Over the Commercial Temperature Range

- ±1.5% Over the Industrial Temperature Range

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

- Leading and Falling Edge Modulation

• Small Converter Size

- Constant Frequency Operation

- Oscillator Programmable from 50kHz to Over 1.5MHz

The output voltage of the converter can be precisely

regulated to as low as 0.597V, with a maximum tolerance of

±1% over the commercial temperature range, and ±1.5%

over the industrial temperature range.

The ISL8104 provides simple, single feedback loop, voltage-

mode control with fast transient response. It includes a

triangle-wave oscillator that is adjustable from below 50kHz

to over 1.5MHz. Full (0% to 100%) PWM duty cycle support

is provided.

• 14V High Speed MOSFET Gate Drivers

- 2.0A Source/3A Sink at 14V Low Side Gate Drive

- 1.25A Source/2A Sink at 14V High Side Gate Drive

- Drives Two N-Channel MOSFETs

The error amplifier features a 15MHz gain-bandwidth

product and 6V/µs slew rate which enables high converter

bandwidth for fast transient performance.

The ISL8104's overcurrent protection monitors the current

• Overcurrent Fault Monitor

by using the r

of the upper MOSFET which eliminates

DS(ON)

- High-Side MOSFET’s r

Sensing

DS(ON)

the need for a current sensing resistor.

- Reduced ~120ns Blanking Time

• Converter can Source and Sink Current

• Soft-Start Done and an External Reference Pin for

Tracking Applications are Available in the QFN Package

• Pin Compatible with ISL6522 and ISL6535

• Supports Start-Up into Prebiased Loads

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinouts

ISL8104

(14 LD NARROW SOIC AND 16 LD QFN)

TOP VIEW

14 VCC

1

2

3

4

5

6

7

RT

OCSET

SS

13 PVCC

12 LGATE

Applications

• Test & Measurement Instruments

• Routers Switches

• Medical Instrumentation

• Industrial Applications

COMP

FB

11

PGND

10 BOOT

9

8

UGATE

PHASE

EN

GND

• Telecom/Datacom Applications

Ordering Information

PART #

(Note)

PART

TEMP.

PACKAGE

(Pb-free)

PKG.

16 15 14 13

MARKING RANGE (°C)

DWG. #

SS

COMP

FB

1

2

3

4

12 PVCC

11 LGATE

10 PGND

ISL8104CBZ 8104CBZ

ISL8104IBZ 8104IBZ

ISL8104CRZ 8104CRZ

ISL8104IRZ 8104IRZ

Add “-T” suffix for tape and reel.

0 to 70

14 Ld SOIC

M14.15

-40 to 85 14 Ld SOIC

0 to 70

-40 to 85 16 Ld 4x4 QFN L16.4x4

16 Ld 4x4 QFN L16.4x4

EN

9

BOOT

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate termination finish,

which are RoHS compliant and compatible with both SnPb and Pb-free soldering

operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

5

6

7

8

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL8104

Simplified Power Sys tem Diagram

R

+1.2V to +14V

OCSET

IN

+8V to +14V

Q1

Q2

C

vcc

L

OUT

V

OUT

ISL8104

C

OUT

R

FS

C

SS

R

1

2

Typical Application

+14V

IN

L

IN

R

FILTER

C

HFIN

C

BIN

D

C

BOOT

F2

C

F1

PVCC

VCC

BOOT

R

C

OCSET

SSDONE

Q1

C

(QFN ONLY)

BOOT

UGATE

PHASE

LGATE

REFIN

L

OUT

(QFN ONLY)

V

OUT

Q2

C

EN

BOUT

HFOUT

PGND

R

RT

SS

ISL8104

COMP

C

SS

2

C

1

C

R

3

R

2

FB

R

1

R

GND

O

FN9257.0

February 13, 2006

3

ISL8104

Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical)

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Note 2). . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead tips only)

Supply Voltage, V

,V

. . . . . . . . . . . . . .GND - 0.3V to +16V

θ

(°C/W)

95

47

θ

(°C/W)

JC

N/A

8.5

PVCC VCC

EN

JA

Enable Voltage, V

. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +16V

Soft-start Done Voltage, V

. . . . . . . . . .GND - 0.3V to +16V

SSDONE

Boot Voltage, V

. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +36V

BOOT

PHASE

Phase Voltage, V

. . . . . . . . . V

- 16V to V

+ 0.3V

BOOT

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.0V

Operating Conditions

ESD Ratings

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Supply Voltage, V

. . . . . . . . . . . . . . . . .+8V ±5% to +14V ±10%

VCC

. . . . . . . . . . . . . . . .+8V ±5% to +14V ±10%

PVCC

Boot to Phase Voltage, V

- V

. . . . . . . . . . . . . . <V

PHASE PVCC

BOOT

Ambient Temperature Range, ISL8104C. . . . . . . . . . . . 0°C to 70°C

Ambient Temperature Range, ISL8104I. . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. Parameters designated by GBD are "Guaranteed by Design."

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

SUPPLY CURRENT

CC

Shutdown Supply V

I

SS/EN = 0V

3.5

6.1

0.5

8.5

mA

CC

VCC

I

0.30

0.75

PVCC

POWER-ON RESET

V

/V

CC PVCC

Rising Threshold

Hysteresis

6.55

170

0.70

180

1.4

7.10

250

0.73

200

1.5

7.55

500

0.75

220

1.60

325

V

mV

V

/V

CC PVCC

OCSET Rising Threshold

OCSET Hysteresis

Enable - Rising Threshold

Enable - Hysteresis

OSCILLATOR

mV

V

175

250

mV

Trim Test Frequency

Total Variation

R

= OPEN V

= 12

VCC

175

-

200

±15

1.9

220

-

kHz

%

RT

8kΩ < R to GND < 200kΩ - GBD

RT

= OPEN

Ramp Amplitude

∆V

R

1.7

2.15

V

P-P

OSC

RT

ERROR AMPLIFIER

DC Gain

R = 10kΩ, C = 100pF - GBD

-

88

15

6

-

dB

L

Gain-Bandwidth Product

Slew Rate

GBWP

SR

R

= 10kΩ, C = 100pF - GBD

MHz

V/µs

L

= 10kΩ, C = 100pF - GBD

L

PROTECTION

OCSET Current

I

T = 0°C to 70°C

180

176

-

200

±10

30

220

224

-

µA

mV

µA

OCSET

J

OCSET Current

I

T = -40°C to 85°C

J

OCSET Measurement Offset

Soft-start Current

OCP

OCSET= 1.5V to 15.4V - GBD

OFFSET

I

22

38

SS

FN9257.0

4

February 13, 2006

ISL8104

Electrical Specifications Recommended Operating Conditions, unless otherwise noted specifications in bold are valid for process,

temperature, and line operating conditions. (Continued)

PARAMETER

REFERENCE

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Reference Voltage

T = 0°C to 70°C

0.591

0.588

-1.0

-1.5

-4

0.597

0.603

0.606

1.0

V

J

T = -40°C to 85°C

0.597

J

System Accuracy

T = 0°C to 70°C

-

%

J

T = -40°C to 85°C

1.5

%

J

REFIN Current Source (QFN Only)

REFIN Threshold (QFN Only)

REFIN Offset (QFN Only)

GATE DRIVERS

-6

-

-8

µA

V

2.10

-3

3.50

3

-

mV

Upper Drive Source Current

Upper Drive Source Impedance

Upper Drive Sink Current

Upper Drive Sink Impedance

Lower Drive Source Current

Lower Drive Source Impedance

Lower Drive Sink Current

Lower Drive Sink Impedance

SSDONE (QFN ONLY)

I

V

- V = 14V, 3nF Load - GBD

PHASE

-

1.25

2.0

2

-

A

Ω

A

Ω

A

Ω

A

Ω

U_SOURCE

BOOT

90mA Source Current

R

U_SOURCE

I

V

- V

= 14V, 3nF Load - GBD

PHASE

U_SINK

BOOT

90mA Source Current

V = 14V, 3nF Load - GBD

R

1.3

2

U_SINK

L_SOURCE

I

PVCC

90mA Source Current

R

1.3

3

L_SOURCE

I

V

= 14V, 3nF Load - GBD

L_SINK

PVCC

90mA Source Current

R

0.94

L_SINK

SSDONE Low Output Voltage

I

= 2mA

0.30

V

SSDONE

Typical Performance Curves

80

70

60

50

40

30

20

10

0

R

PULLUP

RT

TO +14V

1000

100

10

C

= 3300pF

GATE

C

= 1000pF

GATE

R

PULLDOWN

RT

TO GND

C

= 10pF

GATE

100 200 300 400 500 600 700 800 900 1000

10

100

SWITCHING FREQUENCY (kHz)

1000

SWITCHING FREQUENCY (kHz)

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

FIGURE 1. R RESISTANCE vs FREQUENCY

RT

Functional Pin Description (SOIC/QFN)

RT (Pin 1/14)

This pin provides oscillator switching frequency adjustment.

Alternately ISL8104’s switching frequency can be lowered

from 200kHz to 50kHz by connecting the RT pin with a

resistor to VCC according to the following equation:

By placing a resistor (R ) from this pin to GND, the

switching frequency is set from between 200kHz and

1.5MHz according to the following equation:

RT

55000

R

[kΩ] ≈ ------------------------------------------------------- + 70kΩ

RT

(R to VCC)

RT

200[kHz] – F [kHz]

6500

s

R

[kΩ] ≈ ------------------------------------------------------- – 1.3kΩ

RT

(R to GND)

RT

F [kHz] – 200[kHz]

s

FN9257.0

February 13, 2006

5

ISL8104

OCSET (Pin 2/15)

VCC (Pin 14/13)

Provide an 8V to 14V bias supply for the chip to this pin. The

pin should be bypassed with a capacitor to GND.

The current limit is programmed by connecting this pin with a

resistor and capacitor to the drain of the high side MOSEFT.

A 200µA current source develops a voltage across the

resistor which is then compared with the voltage developed

across the high side MOSFET. A blanking period of 120ns is

provided for noise immunity.

REFIN (QFN ONLY Pin 5)

Upon enable if REFIN is less than 2.2V, the external

reference pin is used as the control reference instead of the

internal 0.597V reference. An internal 6µA pull up to 5V is

provided for disabling this functionality.

SS (Pin 3/1)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 30µA current source, sets the soft-start

interval of the converter.

SSDONE (QFN ONLY Pin 16)

Provides an open drain signal at the end of soft-start.

COMP (Pin 4/2) and FB (Pin 5/3)

Functional Description

Initialization

COMP and FB are the available external pins of the error

amplifier. The FB pin is the inverting input of the error ampli-

fier and the COMP pin is the error amplifier output. These

pins are used to compensate the voltage-control feedback

loop of the converter.

The ISL8104 automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary.

The Power-On Reset (POR) function continually monitors

the bias voltage at the VCC pin and the driver input on the

PVCC pin. When the voltages at VCC and PVCC exceed

their rising POR thresholds, a 30µA current source driving

the SS pin is enabled. Upon the SS pin exceeding 1V, the

ISL8104 begins ramping the non-inverting input of the error

amplifier from GND to the System Reference. During

initialization the MOSFET drivers pull UGATE to PHASE and

LGATE to PGND.

EN (Pin 6/4)

This pin is a TTL compatible input. Pull this pin below 0.8V to

disable the converter. In shutdown the soft-start pin is

discharged and the UGATE and LGATE pins are held low.

GND (Pin 7/6)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

Soft-Start

PHASE (Pin 8/7)

During soft-start, an internal 30µA current source charges the

This pin connects to the source of the high side MOSFET

and the drain of the low side MOSFET. This pin represents

the return path for the high side gate driver. During normal

switching, this pin is used for high side current sensing.

external capacitor (C ) on the SS pin up to ~4V. If the

SS

ISL8104 is utilizing the internal reference, then as the SS pin’s

voltage ramps from 1V to 3V, the soft-start function scales the

reference input (positive terminal of error amp) from GND to

VREF (0.597V nominal). If the ISL8104 is utilizing an

UGATE (Pin 9/8)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

V

EN

BOOT (Pin 10/9)

This pin provides bias to the upper MOSFET driver. A

bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

V

OUT

V

SS

PGND (Pin 11/10)

This is the power ground connection. Tie the lower MOSFET

source and board ground to this pin.

LGATE (Pin 12/11)

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lower MOSFET.

t

SS

PVCC (Pin 13/12)

Provide an 8V to 14V bias supply for the lower gate drive to

this pin. This pin should be bypassed with a capacitor to

PGND.

FIGURE 3. TYPICAL SOFT-START INTERVAL

externally supplied reference, when the voltage on the SS pin

reaches 1V, the internal reference input (into of the error amp)

ramps from GND to the externally supplied reference at the

same rate as the voltage on the SS pin. Figure 3 shows a

FN9257.0

6

February 13, 2006

ISL8104

typical soft-start interval. The rise time of the output voltage is,

A 120ns blanking period is used to reduce the current

sampling error due to leading-edge switching noise. An

additional simultaneous 120ns low pass filter is used to

further reduce measurement error due to noise.

therefore, dependent upon the value of the soft-start

capacitor, C . If the internal reference is used, then the soft-

SS

start capacitance value can be calculated through:

30µA ⋅ t

OCP faults cause the regulator to disable (upper and lower

drives disabled, SSDONE pulled low, soft-start capacitor

discharged) itself for a fixed period of time, after which a

normal soft-start sequence is initiated. If the voltage on the

SS pin is already at 4V and an OCP is detected, a 30µA

current sink is immediately applied to the SS pin. If an OCP

is detected during soft-start, the 30µA current sink will not be

applied until the voltage on the SS pin has reached 4V. This

current sink discharges the CSS capacitor in a linear

fashion. Once the voltage on the SS pin has reached

approximately 0V, the normal soft-start sequence is initiated.

If the fault is still present on the subsequent restart, the

ISL8104 will repeat this process in a hiccup mode. Figure 4

shows a typical reaction to a repeated overcurrent condition

that places the regulator in a hiccup mode. If the regulator is

repeatedly tripping overcurrent, the hiccup period can be

approximated by the following formula:

SS

C

= ----------------------------

SS

2V

If an external reference is used, then the soft-start

capacitance can be calculated through:

30µA ⋅ t

SS

C

= ----------------------------

SS

V

REFEXT

Prebiased Load Start-up

Drivers are held in tri-state (UG pulled to Phase, LG pulled to

PGND) at the beginning of a soft-start cycle until two PWM

pulses are detected. The low side MOSFET is turned on first

to provide for charging of the bootstrap capacitor. This

method of driver activation provides support for start-up into

prebiased loads by not activating the drivers until the control

loop has entered its linear region, thereby substantially

reducing output transients that would otherwise occur had

the drivers been activated at the beginning of the soft-start

cycle.

8V ⋅ C

SS

T

= -----------------------

HICCUP

30µA

SSDONE

V

SSDONE

Soft-start done is only available in the 16 Lead QFN

packaging option of the ISL8104. When the soft-start pin

reaches 4V, an open drain signal is provided to support

sequencing requirements. SSDONE is deasserted by

disabling of the part, including pulling SS low, and by POR

and OCP events.

V

SS

I

OCP

Oscillator

The oscillator is a triangular waveform, providing for leading

and falling edge modulation. The peak to peak of the ramp

amplitude is set at 1.9V and varies as a function of

frequency. At 50kHz the peak to peak amplitude is

I

LOAD

approximately 1.8V while at 1.5MHz it is approximately 2.2V.

In the event the regulator operates at 100% duty cycle for 64

clock cycles an automatic boot cap refresh circuit will

activate turning on LG for approximately 1/2 of a clock cycle.

T

HICCUP

FIGURE 4. TYPICAL OVERCURRENT PROTECTION

Overcurrent Protection

The OCP function is enabled with the drivers at start-up.

The OCP trip point varies mainly due to MOSFET r

DS(ON)

OCP is implemented via a resistor (R

) and a

OCSET

variations and layout noise concerns. To avoid overcurrent

capacitor (C

) connecting the OCSET pin and the

OCSET

tripping in the normal operating load range, find the R

resistor from the following equations with:

OCSET

drain of the high side MOSEFT. An internal 200mA current

source develops a voltage across R which is then

OCSET

compared with the voltage developed across the high side

MOSFET at turn on as measured at the PHASE pin. When

the voltage drop across the MOSFET exceeds the voltage

drop across the resistor, a sourcing OCP event occurs.

1. The maximum r

temperature;

at the highest junction

DS(ON)

2. The minimum I

OCSET

from the specification table;

C

is placed in parallel with R

to smooth the

OCSET

voltage across R

on the input bus.

in the presence of switching noise

OCSET

FN9257.0

February 13, 2006

7

ISL8104

Determine the overcurrent trip point greater than the

maximum output continuous current at maximum inductor

ripple current.

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Simple OCP Equation

I

• r

A multi-layer printed circuit board is recommended. Figure 5

shows the critical components of the converter. Note that

OC_SOURCE

DS(ON)

R

= ---------------------------------------------------------------

OCSET

200µA

capacitors C and C

could each represent numerous

IN OUT

physical capacitors. Dedicate one solid layer, usually a

middle layer of the PC board, for a ground plane and make

all critical component ground connections with vias to this

layer. Dedicate another solid layer as a power plane and

break this plane into smaller islands of common voltage

levels. Keep the metal runs from the PHASE terminals to the

output inductor short. The power plane should support the

input power and output power nodes. Use copper filled

polygons on the top and bottom circuit layers for the phase

nodes. Use the remaining printed circuit layers for small

signal wiring.

Detailed OCP Equation

∆I

2







I

+ ---- • r

OC_SOURCE



DS(ON)

R

N

= ---------------------------------------------------------------------------------

OCSET

I

• N

U

HSOC

= NUMBER OF HIGH SIDE MOSFETs

U

V

- V

V

OUT

V

IN

OUT

--------------------------------- ---------------

∆I =

•

F

• L

SW

OUT

F

= Regulator Switching Frequency

SW

High Speed MOSFET Gate Driver

The integrated driver has the same drive capability and

feature as the Intersil’s 12V gate driver, ISL6612. The PWM

tri-state feature helps prevent a negative transient on the

output voltage when the output is being shut down. This

eliminates the Schottky diode that is used in some systems

for protecting the microprocessor from reversed-output-

voltage damage. See the ISL6612 datasheet for

+14V

VCC

C

BP_PVCC

PVCC

C

BP_VCC

ISL8104

VIN

C

specification parameters that are not defined in the current

ISL8104 electrical specifications table.

IN

UGATE

BOOT

Q

1

Reference Input

The REFIN pin allows the user to bypass the internal 0.597V

reference with an external reference. If REFIN is NOT above

~2.2V, the external reference pin is used as the control

reference instead of the internal 0.597V reference. When not

using the external reference option the REFIN pin should be

left floating. An internal 6mA pull-up keeps this REFIN pin

above 2.2V in this situation.

C

IN

L

OUT

C

V

OUT

PHASE

LGATE

OUT

Q

2

SS

Internal Reference and System Accuracy

C

SS

GND

PGND

The Internal Reference is set to 0.597V. The total DC system

accuracy of the system is to be within 1.0% over commercial

temperature range and 1.5% over the industrial temperature

range. System Accuracy includes Error Amplifier offset, and

Reference Error. The use of REFIN may add up to 3mV of

offset error into the system (as the Error Amplifier offset is

trimmed out via the internal System reference.)

KEY

TRACE SIZED FOR 3A PEAK CURRENT

SHORT TRACE, MINIMUM IMPEDANCE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

Application Guidelines

Layout Considerations

FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

FN9257.0

February 13, 2006

8

ISL8104

Locate the ISL8104 within 2 to 3 inches of the MOSFETs, Q1

C

2

and Q2 (1 inch or less for 500kHz or higher operation). The

circuit traces for the MOSFETs’ gate and source connections

from the ISL8104 must be sized to handle up to 3A peak

current. Minimize any leakage current paths on the SS pin

C

R

3

R

C

2

1

COMP

and locate the capacitor, C close to the SS pin as the

ss

-

internal current source is only 30µA. Provide local V

CC

R

FB

1

+

decoupling between VCC and GND pins. Locate the

capacitor, C as close as practical to the BOOT pin and

E/A

BOOT

the phase node.

VREF

GND

Compensating the Converter

The ISL8104 Single-phase converter is a voltage-mode

controller. This section highlights the design consideration for a

voltage-mode controller requiring external compensation. To

address a broad range of applications, a type-3 feedback

network is recommended (see Figure 6).

V

OSCILLATOR

OUT

V

IN

V

OSC

PWM

CIRCUIT

C

2

L

C

R

1

DCR

C

UGATE

PHASE

2

COMP

FB

HALF-BRIDGE

DRIVE

C

3

R

1

ESR

ISL8104

LGATE

R

3

VOUT

ISL8104

EXTERNAL CIRCUIT

FIGURE 6. COMPENSATION CONFIGURATION FOR THE

ISL8104 CIRCUIT

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

The compensation network consists of the error amplifier

(internal to the ISL8104) and the external R -R , C -C

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage is

regulated to the reference voltage level. The error amplifier

output is compared with the oscillator triangle wave to

provide a pulse-width modulated wave with an amplitude of

1

3

1

3

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

frequency (F ; typically 0.1 to 0.3 of F ) and adequate

0

SW

phase margin (better than 45 degrees). Phase margin is the

difference between the closed loop phase at F and 180°.

V

at the PHASE node. The PWM wave is smoothed by the

IN

0dB

The equations that follow relate the compensation network’s

output filter. The output filter capacitor bank’s equivalent

series resistance is represented by the series resistor ESR.

poles, zeros and gain to the components (R , R , R , C , C ,

1

2

3

1

2

and C ) in Figures 6 and 7. Use the following guidelines for

3

The modulator transfer function is the small-signal transfer

locating the poles and zeros of the compensation network:

function of V

/V . This function is dominated by a

OUT COMP

DC gain and shaped by the output filter, with a double pole

break frequency at F and a zero at F . For the purpose

1. Select a value for R (1kΩ to 10kΩ, typically). Calculate

1

LC

CE

value for R for desired converter bandwidth (F ). If

2

0

of this analysis, L and DCR represent the output inductance

and its DCR, while C and ESR represents the total output

capacitance and its equivalent series resistance.

setting the output voltage to be equal to the reference set

voltage as shown in Figure 7, the design procedure can

be followed as presented. As the ISL8104 supports 100%

1

V

⋅ R ⋅ F

F

= ---------------------------

OSC

1 0

F

= ---------------------------------

LC

CE

R

= ----------------------------------------------

2π ⋅ C ⋅ ESR

2

2π ⋅ L ⋅ C

D

⋅ V ⋅ F

IN LC

MAX

duty cycle, D

equals 1. The ISL8104 uses a fixed

OSC

MAX

ramp amplitude (V

simplifies to:

) of 1.9V, the above equation

1.9 ⋅ R ⋅ F

1

0

R

= -------------------------------

2

V

⋅ F

LC

IN

FN9257.0

February 13, 2006

9

ISL8104

2. Calculate C such that F is placed at a fraction of the F ,

LC

compensation gain at F against the capabilities of the error

P2

1

Z1

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor below

LC

amplifier. The closed loop gain, G , is constructed on the

CL

to the desired number). The higher the quality factor of the

log-log graph of Figure 8 by adding the modulator gain,

output filter and/or the higher the ratio F /F , the lower

CE LC

G

(in dB), to the feedback compensation gain, G (in

MOD

FB

the F frequency (to maximize phase boost at F ).

Z1 LC

dB). This is equivalent to multiplying the modulator transfer

function and the compensation transfer function and then

plotting the resulting gain.

1

C

= ----------------------------------------------

1

2π ⋅ R ⋅ 0.5 ⋅ F

2

LC

3. Calculate C such that F is placed at F

.

2

P1 CE

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

Z1 Z2

P1

P2

C

1

C

= -------------------------------------------------------

2

2π ⋅ R ⋅ C ⋅ F – 1

CE

2

1

4. Calculate R such that F is placed at F . Calculate C

Z2 LC

3

P2

3

such that F is placed below F (typically, 0.3 to 1.0

SW

times F ). F

represents the switching frequency of

SW

the regulator. Change the numerical factor (0.7) below to

R2

-------









20log

D

⋅ V

reflect desired placement of this pole. Placement of F

P2

R1

MAX

IN

20log---------------------------------

lower in frequency helps reduce the gain of the

compensation network at high frequency, in turn reducing

the HF ripple component at the COMP pin and minimizing

resultant duty cycle jitter.

V

0

OSC

G

FB

G

CL

R

G

MOD

FREQUENCY

1

R

= ---------------------

3

F

LOG

SW

F

0

LC

CE

------------ – 1

F

LC

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

1

C

= ------------------------------------------------

2π ⋅ R ⋅ 0.7 ⋅ F

3

SW

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin. The mathematical model

presented makes a number of approximations and is

generally not accurate at frequencies approaching or

exceeding half the switching frequency. When designing

compensation networks, select target crossover frequencies

in the range of 10% to 30% of the switching frequency,

It is recommended that a mathematical model be used to

plot the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

frequency response of the modulator (G

), feedback

MOD

compensation (G ) and closed-loop response (G ):

FB

CL

D

⋅ V

1 + s(f) ⋅ ESR ⋅ C

MAX

V

IN

------------------------------ -----------------------------------------------------------------------------------------------------------

G

(f) =

⋅

MOD

2

OSC

1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C

F

.

SW

1 + s(f) ⋅ R ⋅ C

2

1

----------------------------------------------------

G

(f) =

⋅

FB

Component Selection Guidelines

s(f) ⋅ R ⋅ (C + C )

1

2

1 + s(f) ⋅ (R + R ) ⋅ C

3

Output Capacitor Selection

1

3

-------------------------------------------------------------------------------------------------------------------------

C

⋅ C

2

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.













1

--------------------

(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R

⋅



3

2

C

+ C

2



1

G

(f) = G

(f) ⋅ G (f)

MOD FB

where, s(f) = 2π ⋅ f ⋅ j

CL

COMPENSATION BREAK FREQUENCY EQUATIONS

1

F

= --------------------------------------------

F

= ------------------------------

P1

Z1

C

⋅ C

2

2π ⋅ R ⋅ C

1

2

1

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

--------------------

⋅

2π ⋅ R

2

C

+ C

2

1

F

= -------------------------------------------------

F

= ------------------------------

2π ⋅ R ⋅ C

3

Z2

P2

2π ⋅ (R + R ) ⋅ C

1

3

Figure 8 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

FN9257.0

10

February 13, 2006

ISL8104

components. Consult with the manufacturer of the load on

specific decoupling requirements.

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output levels for

the worst case response time.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

transient. An aluminum electrolytic capacitor's ESR value is

related to the case size with lower ESR available in larger

case sizes. However, the equivalent series inductance

(ESL) of these capacitors increases with case size and can

reduce the usefulness of the capacitor to high slew-rate

transient loading. Unfortunately, ESL is not a specified

parameter. Work with your capacitor supplier and measure

the capacitor’s impedance with frequency to select a

suitable component. In most cases, multiple electrolytic

capacitors of small case size perform better than a single

large case capacitor.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place

the small ceramic capacitors physically close to the

MOSFETs and between the drain of Q1 and the source of

Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select a bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage, a voltage rating of 1.5 times greater is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

V

- V

V

OUT

V

IN

OUT

------------------------------- ---------------

∆I =

•

∆V

= ∆I x ESR

OUT

Fs x L

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL8104 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection/Considerations

The ISL8104 requires at least 2 N-Channel power

MOSFETs. These should be selected based upon r

gate supply requirements, and thermal management

requirements.

,

DS(ON)

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. At a

300kHz switching frequency, the conduction losses are the

largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed

between the two MOSFETs according to duty factor (see the

following equations). Only the upper MOSFET exhibits

switching losses, since the schottky rectifier clamps the

switching node before the synchronous rectifier turns on.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

L

× I

L × I

O TRAN

O

TRAN

T

= -------------------------------

T

= ------------------------------

RISE

FALL

V

– V

V

IN

OUT

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the lower MOSFETs body diode. The

gate-charge losses are dissipated by the ISL8104 and don't

heat the MOSFETs. However, large gate-charge increases

where: I

TRAN

is the transient load current step, T

is the

RISE

is the

response time to the application of load, and T

FALL

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

FN9257.0

11

February 13, 2006

ISL8104

+14V

1

2

P

= I x r

O

x D + Io x V x T

IN

x Fs

SW

UPPER

DS(ON)

D

BOOT

2

+1.2V TO +14V

-

+

P

= I x r

x (1 - D)

LOWER

O

DS(ON)

V

D

where: D is the duty cycle = V / V

IN

,

O

ISL8104

BOOT

T

is the switching interval, and

SW

Fs is the switching frequency.

C

BOOT

Q1

UGATE

PHASE

PVCC

NOTE:

the switching interval, T

MOSFET switching losses. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

which increases the upper

V_G-S≈ V - V

CC D

SW

+14V

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate

heatsink may be necessary depending upon MOSFET

power, package type, ambient temperature and air flow.

D2

Q2

LGATE

PGND

-

NOTE:

_G-S≈ PVCC

+

V

GND

Standard-gate MOSFETs are normally recommended for

use with the ISL8104. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFETs absolute gate-to-

source voltage rating determine whether logic-level

MOSFETs are appropriate.

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

+14V

+5V OR LESS

Figure 9 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from +14V. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of +12V

ISL8104

BOOT

Q1

Q2

less the boot diode drop (V ) when the lower MOSFET, Q2

D

UGATE

turns on. A MOSFET can only be used for Q1 if the

NOTE:

V

_G-S≈ V - 5V

CC

MOSFETs absolute gate-to-source voltage rating exceeds

the maximum voltage applied to +14V. For Q2, a logic-level

MOSFET can be used if its absolute gate-to-source voltage

rating also exceeds the maximum voltage applied to +14V.

+14V

PVCC

D2

LGATE

PGND

-

NOTE:

_G-S≈ PVCC

+

Figure 10 shows the upper gate drive supplied by a direct

connection to +14V. This option should only be used in

converter systems where the main input voltage is +5VDC or

less. The peak upper gate-to-source voltage is

V

GND

approximately +14V less the input supply. For +5V main

power and +14VDC for the bias, the gate-to-source voltage

of Q1 is 9V. A logic-level MOSFET is a good choice for Q1

and a logic-level MOSFET can be used for Q2 if its absolute

gate-to-source voltage rating exceeds the maximum voltage

applied to PVCC. This method reduces the number of

required external components, but does not provide for

immunity to phase node ringing during turn on and may

result in lower system efficiency.

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

CC

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor

swing during the dead time between turning off the lower

MOSFET and turning on the upper MOSFET. The diode must

be a Schottky type to prevent the lossy parasitic MOSFET

body diode from conducting. It is acceptable to omit the diode

and let the body diode of the lower MOSFET clamp the

negative inductor swing, but efficiency could slightly decrease

as a result. The diode's rated reverse breakdown voltage

must be greater than the maximum input voltage.

FN9257.0

12

February 13, 2006

ISL8104

Small Outline Plas tic Packages (SOIC)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

8.55

3.80

MAX

1.75

0.25

0.51

0.25

8.75

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

-

SEATING PLANE

A

9

0.0075

0.3367

0.1497

0.0098

0.3444

0.1574

-

-A-

o

h x 45

D

3

4

-C-

α

0.050 BSC

1.27 BSC

-

e

A1

C

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

B

0.10(0.004)

5

0.25(0.010) M

C

A M B S

L

6

N

α

14

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN9257.0

13

February 13, 2006

ISL8104

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.23

1.95

0.28

0.35

2.25

5, 8

D

4.00 BSC

-

D1

D2

E

3.75 BSC

9

2.10

7, 8

4.00 BSC

-

E1

E2

e

3.75 BSC

9

2.10

7, 8

0.65 BSC

-

k

0.25

0.50

-

L

0.60

0.75

0.15

8

L1

N

-

16

4

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 5 5/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9257.0

14

February 13, 2006


型号：	ISL8104IBZ
厂家：	Intersil
描述：	Synchronous Buck Pulse-Width Modulator (PWM) Controller 同步降压型脉宽调制器（PWM ）控制器控制器
文件：	总14页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL8104IBZ [INTERSIL]

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