ISL8104CBZ-T [RENESAS]
3A SWITCHING CONTROLLER, 1500kHz SWITCHING FREQ-MAX, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14;
| 型号： | ISL8104CBZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3A SWITCHING CONTROLLER, 1500kHz SWITCHING FREQ-MAX, PDSO14, ROHS COMPLIANT, PLASTIC, MS-012AB, SOIC-14 开关 光电二极管 |
| 文件： | 总14页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8104
FN9257
Rev 2.00
March 7, 2008
8V to 14V, Single-Phase Synchronous Buck Pulse-Width Modulation (PWM)
Controller With Integrated Gate Drivers
The ISL8104 is a 8V to 14V synchronous PWM controller
with integrated MOSFET drivers. The controller features the
Features
• +8V ±5% to +14V ±10% Bias Voltage Range
- 1.5V to 15.4V Input Voltage Range
ability to safely start-up into prebiased output loads and
provides protection against overcurrent fault events.
Overcurrent protection is implemented using top-side
• 0.597V Internal Reference Voltage
MOSFET r
sensing, eliminating the need for a current
- 1.0% Over the Commercial Temperature Range
- 1.5% Over the Industrial Temperature Range
DS(ON)
sensing resistor.
• Voltage-Mode PWM Control with Dual-Edge Modulation
The ISL8104 employs voltage-mode control with dual-edge
modulation to achieve fast transient response. The operating
frequency is adjustable from 50kHz to 1.5MHz with full (0%
to 100%) PWM duty cycle capability. The error amplifier
features a 15MHz (typ) gain-bandwidth product and 6V/µs
slew rate enabling high converter bandwidth.
• 14V High Speed N-Channel MOSFET Gate Drivers
- 2.0A Source/3A Sink at 14V Bottom-Side Gate Drive
- 1.25A Source/2A Sink at 14V Top-Side Gate Drive
• Fast Transient Response
- 15MHz (typ) Gain-Bandwidth Error Amplifier with 6V/µs
slew rate
- Full 0% to 100% Duty Cycle Support
The output voltage of the converter can be regulated to as
low as 0.597V with a tolerance of ±1.0% over the
commercial temperature range (0°C to +70°C), and ±1.5%
over industrial temperature range (-40°C to +85°C).
Provided in the QFN package, a SS pin and REFIN pin
enable supply sequencing and voltage tracking functionality.
• Programmable Operating Frequency from 50kHz to
1.5MHz
• Lossless Programmable Overcurrent Protection
- Top-Side MOSFET’s r
Sensing
DS(ON)
- ~120ns Blanking Time
Pinouts
• Sourcing and Sinking Current Capability
• Support for Start-Up into Prebiased Loads
ISL8104 (16 LD QFN)
TOP VIEW
• Soft-Start Done and an External Reference Pin for
Tracking Applications are Available in the QFN Package
• Pb-free available (RoHS compliant)
16 15 14 13
Applications
SS
COMP
FB
1
2
3
4
12 PVCC
11 BGATE
10 PGND
• Test and Measurement Instruments
• Distributed DC/DC Power Architecture
• Industrial Applications
EN
9
BOOT
• Telecom/Datacom Applications
5
6
7
8
Ordering Information
PART NUMBER
(Note)
PART
TEMP.
PACKAGE
(Pb-free)
PKG.
DWG. #
MARKING RANGE (°C)
ISL8104CBZ*
ISL8104IBZ*
ISL8104CRZ*
ISL8104IRZ*
8104CBZ
8104IBZ
0 to +70
14 Ld SOIC
M14.15
M14.15
ISL8104 (14 LD SOIC)
TOP VIEW
-40 to +85 14 Ld SOIC
0 to +70
-40 to +85 16 Ld 4x4 QFN L16.4x4
81 04CRZ
81 04IRZ
16 Ld 4x4 QFN L16.4x4
14 VCC
13 PVCC
1
FSET
TSOC
SS
2
3
4
5
6
7
ISL8104EVAL1Z Evaluation Board
ISL8104EVAL2Z Evaluation Board
12
11
BGATE
PGND
COMP
FB
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
10 BOOT
9
8
TGATE
LX
EN
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
GND
FN9257 Rev 2.00
March 7, 2008
Page 1 of 14
Block Diagram
SS
EN
VCC
TSOC
INTERNAL
REGULATOR
200µA
POWER-ON
RESET (POR)
30A
BOOT
SOURCE OCP
TGATE
SOFT-START
SSDONE
(QFN ONLY)
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
LX
FSET
OSCILLATOR
PWM
6µA
REFERENCE
= 0.597 V
PVCC
BGATE
PGND
V
REF
EA
REFIN
(QFN ONLY)
GND
COMP
FB
ISL8104
Typical Application with Single Power Supply
+8V TO +14V
V
L
IN
IN
R
FILTER
D
C
C
BOOT
HFIN
BIN
C
F2
PVCC
VCC
C
F1
BOOT
TSOC
R
TSOC
TSOC
SSDONE
(QFN ONLY)
C
C
BOOT
Q1
Q2
TGATE
LX
REFIN
(QFN ONLY)
L
OUT
V
OUT
BGATE
PGND
C
C
EN
BOUT
HFOUT
ISL8104
R
FSET
FSET
COMP
R
2
1
C
R
3
3
C
2
SS
C
FB
GND
C
SS
R
1
R
0
Typical Application with Separated Power Supplies
+1.5V TO +15.4V
V
IN
+8V TO +14V
R
V
FILTER
CC
D
C
C
BIN
BOOT
HFIN
C
F2
C
F1
PVCC
VCC
BOOT
TSOC
R
C
TSOC
TSOC
SSDONE
(QFN ONLY)
C
BOOT
Q1
Q2
TGATE
LX
REFIN
(QFN ONLY)
L
OUT
V
OUT
BGATE
PGND
C
C
EN
BOUT
HFOUT
ISL8104
R
FSET
FSET
COMP
R
C
2
1
C
R
3
3
C
2
SS
FB
GND
C
SS
R
1
R
0
FN9257 Rev 2.00
March 7, 2008
Page 3 of 14
ISL8104
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
Enable Voltage, V
Soft-start Done Voltage, V
, V
. . . . . . . . . . . . .GND - 0.3V to +16V
. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +16V
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
PVCC VCC
JA
EN
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
95
47
N/A
8.5
. . . . . . . . . .GND - 0.3V to +16V
SSDONE
TSOC Voltage, V
BOOT Voltage, V
. . . . . . . . . . . . . . . . . . . .GND - 0.3V to +16V
. . . . . . . . . . . . . . . . . . .GND - 0.3V to +36V
TSOC
BOOT
LX Voltage, V . . . . . . . . . . . . . . . . V
- 16V to V + 0.3V
BOOT
LX BOOT
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.0V
ESD Rating
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, V
Supply Voltage, V
. . . . . . . . . . . . . . . . .+8V 5% to +14V 10%
VCC
. . . . . . . . . . . . . . . .+8V 5% to +14V 10%
PVCC
Boot to Phase Voltage, V
- V
. . . . . . . . . . . . . . . . . <V
BOOT
LX PVCC
Ambient Temperature Range, ISL8104C. . . . . . . . . . . 0°C to +70°C
Ambient Temperature Range, ISL8104I. . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
4. Limits should be considered typical and are not production tested.
Electrical Specifications Recommended Operating Conditions, unless otherwise noted, specifications in bold are valid for process,
temperature, and line operating conditions.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY CURRENT
CC
Shutdown Supply V
Shutdown Supply V
I
SS/EN = 0V
SS/EN = 0V
3.5
6.1
0.5
8.5
mA
mA
CC
VCC
I
0.30
0.75
PVCC
PVCC
POWER-ON RESET
V
/V
CC PVCC
Rising Threshold
Hysteresis
6.45
170
0.70
180
1.4
7.10
250
0.73
200
1.5
7.55
500
0.75
220
1.60
325
V
mV
V
V /V
CC PVCC
TSOC Rising Threshold
TSOC Hysteresis
mV
V
Enable - Rising Threshold
Enable - Hysteresis
REFERENCE
175
250
mV
Reference Voltage
T = 0°C to +70°C
0.591
0.588
-1.0
-1.5
-4
0.597
0.603
0.606
1.0
V
V
J
T = -40°C to +85°C
0.597
J
System Accuracy
T = 0°C to +70°C
-
-
%
J
T = -40°C to +85°C
1.5
%
J
REFIN Current Source (QFN Only)
REFIN Threshold (QFN Only)
REFIN Offset (QFN Only)
-6
-
-8
µA
V
2.10
-3
3.50
3
-
mV
FN9257 Rev 2.00
March 7, 2008
Page 4 of 14
ISL8104
Electrical Specifications Recommended Operating Conditions, unless otherwise noted, specifications in bold are valid for process,
temperature, and line operating conditions. (Continued)
PARAMETER
OSCILLATOR
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Trim Test Frequency
R
= OPEN V
= 12
175
200
15
1.9
1
220
kHz
%
FSET
VCC
Total Variation (Note 4)
8k < R
to GND < 200k
-
1.7
-
-
2.15
-
FSET
= OPEN
Ramp Amplitude
V
R
V
OSC
FSET
P-P
V
Ramp Bottom (Note 4)
ERROR AMPLIFIER
DC Gain (Note 4)
R
R
R
= 10k, C = 100pF
-
-
-
-
-
88
15
6
-
-
-
-
-
dB
MHz
V/s
mA
L
L
L
L
Gain-Bandwidth Product (Note 4)
Slew Rate (Note 4)
GBWP
SR
= 10k, C = 100pF
L
= 10k, C = 100pF
L
COMP Source Current (Note 4)
COMP Sink Current (Note 4)
GATE DRIVERS
I
2
COMPSRC
I
2
mA
COMPSNK
Top-side Drive Source Current (Note 4)
Top-side Drive Source Impedance
Top-side Drive Sink Current (Note 4)
Top-side Drive Sink Impedance
Bottom-side Drive Source Current (Note 4)
Bottom-side Drive Source Impedance
Bottom-side Drive Sink Current (Note 4)
Bottom-side Drive Sink Impedance
PROTECTION
I
V
- V = 14V, 3nF Load
LX
-
-
-
-
-
-
-
-
1.25
2.0
2
-
-
-
-
-
-
-
-
A
A
A
A
T_SOURCE
BOOT
R
90mA Source Current
T_SOURCE
I
V
- V = 14V, 3nF Load
BOOT LX
T_SINK
R
90mA Source Current
V = 14V, 3nF Load
1.3
2
T_SINK
I
B_SOURCE
PVCC
90mA Source Current
R
1.3
3
B_SOURCE
I
V
= 14V, 3nF Load
B_SINK
PVCC
R
90mA Source Current
0.94
B_SINK
TSOC Current
I
T = 0°C to +70°C
180
176
-
200
200
10
220
224
-
A
A
TSOC
J
T = -40°C to +85°C
J
TSOC Measurement Offset (Note 4)
SOFT-START
OCP
TSOC = 1.5V to 15.4V
mV
OFFSET
Soft-start Current
I
22
-
30
-
38
A
SS
SSDONE Low Output Voltage (QFN ONLY)
I
= 2mA
0.30
V
SSDONE
EN (Pin 4/6)
Functional Pin Description (QFN/SOIC)
This pin is a TTL compatible input. Pull this pin below 0.8V to
disable the converter. In shutdown the soft-start pin is
discharged and the TGATE and BGATE pins are held low.
SS (Pin 1/3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 30µA current source, sets the soft-start
interval of the converter.
REFIN (QFN ONLY Pin 5)
Upon enable if REFIN is less than 2.2V, the external
reference pin is used as the control reference instead of the
internal 0.597V reference. An internal 6µA pull-up to 5V is
provided for disabling this functionality.
COMP (Pin 2/4) and FB (Pin 3/5)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 6/7)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
FN9257 Rev 2.00
March 7, 2008
Page 5 of 14
ISL8104
LX (Pin 7/8)
This pin connects to the source of the top-side MOSFET and
the drain of the bottom-side MOSFET. This pin represents
the return path for the top-side gate driver. During normal
switching, this pin is used for top-side current sensing.
R
PULLUP
FSET
TO VCC
1000
100
10
TGATE (Pin 8/9)
Connect TGATE to the top-side MOSFET gate. This pin
provides the gate drive for the top-side MOSFET.
R
PULL-DOWN
FSET
TO GND
BOOT (Pin 9/10)
This pin provides bias to the top-side MOSFET driver. A
bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
10k
100k
SWITCHING FREQUENCY (Hz)
1M
PGND (Pin 10/11)
FIGURE 1. R
FSET
RESISTANCE vs FREQUENCY
This is the power ground connection. Tie the bottom-side
MOSFET source and board ground to this pin.
80
70
60
50
40
30
20
10
0
BGATE (Pin 11/12)
Connect BGATE to the bottom-side MOSFET gate. This pin
provides the gate drive for the bottom-side MOSFET.
C
= 3300pF
GATE
C
= 1000pF
GATE
PVCC (Pin 12/13)
Provide an 8V to 14V bias supply for the bottom-side gate
drive to this pin. This pin should be bypassed with a
capacitor to PGND.
C
= 10pF
GATE
VCC (Pin 13/14)
Provide an 8V to 14V bias supply for the chip to this pin. The
pin should be bypassed with a capacitor to GND.
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
FSET (Pin 14/1)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
This pin provides oscillator switching frequency adjustment.
SSDONE (QFN ONLY Pin 16)
By placing a resistor (R
) from this pin to GND, the
FSET
switching frequency is set from between 200kHz and
1.5MHz according to Equation 1:
Provides an open drain signal at the end of soft-start.
Functional Description
6500
-------------------------------------------------------
s
R
k
– 1.3 k
FSET
(R
FSET
to GND)
F kHz – 200kHz
Initialization
(EQ. 1)
The ISL8104 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the bias voltage at the VCC pin and the driver input on the
PVCC pin. When the voltages at VCC and PVCC exceed
their rising POR thresholds, a 30µA current source driving
the SS pin is enabled. Upon the SS pin exceeding 1V, the
ISL8104 begins ramping the non-inverting input of the error
amplifier from GND to the System Reference. During
initialization the MOSFET drivers pull TGATE to LX and
BGATE to PGND.
Alternately ISL8104’s switching frequency can be lowered
from 200kHz to 50kHz by connecting the FSET pin with a
resistor to VCC according Equation 2:
55000
200kHz – F kHz
-------------------------------------------------------
R
k
+ 70 k
FSET
(R
FSET
to VCC)
s
(EQ. 2)
TSOC (Pin 15/2)
The current limit is programmed by connecting this pin with a
resistor and capacitor to the drain of the top-side MOSEFT.
A 200µA current source develops a voltage across the
resistor which is then compared with the voltage developed
across the top-side MOSFET. A blanking period of 120ns is
provided for noise immunity.
Soft-Start
During soft-start, an internal 30µA current source charges the
external capacitor (C ) on the SS pin up to ~4V. If the
SS
ISL8104 is utilizing the internal reference, then as the SS pin’s
voltage ramps from 1V to 3V, the soft-start function scales the
FN9257 Rev 2.00
March 7, 2008
Page 6 of 14
ISL8104
reference input (positive terminal of error amp) from GND to
VREF (0.597V nominal). If the ISL8104 is utilizing an
externally supplied reference, when the voltage on the SS pin
reaches 1V, the internal reference input (into the error amp)
ramps from GND to the externally supplied reference at the
same rate as the voltage on the SS pin. Figure 3 shows a
typical soft-start interval. The rise time of the output voltage is,
therefore, dependent upon the value of the soft-start
Oscillator
The oscillator is a triangular waveform, providing for leading
and falling edge modulation. The peak-to-peak of the ramp
amplitude is set at 1.9V and varies as a function of frequency.
At 50kHz the peak to peak amplitude is approximately 1.8V
while at 1.5MHz it is approximately 2.2V. In the event the
regulator operates at 100% duty cycle for 64 clock cycles an
automatic boot cap refresh circuit will activate turning on
BGATE for approximately 1/2 of a clock cycle.
capacitor, C . If the internal reference is used, then the
SS
soft-start capacitance value can be calculated through
Equation 3:
Overcurrent Protection
30A t
SS
V
SSDONE
----------------------------
=
(EQ. 3)
(EQ. 4)
C
SS
2V
If an external reference is used then the soft-start
capacitance can be calculated through Equation 4:
V
SS
30A t
SS
----------------------------
=
C
SS
V
REFEXT
I
OCP
V
EN
V
OUT
I
LOAD
V
SS
t
HICCUP
FIGURE 4. TYPICAL OVERCURRENT PROTECTION
The OCP function is enabled with the drivers at start-up.
OCP is implemented via a resistor (R ) and a capacitor
TSOC
(C
) connecting the TSOC pin and the drain of the
TSOC
top-side MOSEFT. An internal 200mA current source
develops a voltage across R , which is then compared
TSOC
t
SS
with the voltage developed across the top-side MOSFET at
turn on as measured at the LX pin. When the voltage drop
across the MOSFET exceeds the voltage drop across the
FIGURE 3. TYPICAL SOFT-START INTERVAL
Prebiased Load Start-up
resistor, a sourcing OCP event occurs. C
is placed in
in
TSOC
parallel with R
TSOC
to smooth the voltage across R
TSOC
Drivers are held in tri-state (TGATE pulled to LX, BGATE
pulled to PGND) at the beginning of a soft-start cycle until
two PWM pulses are detected. The bottom-side MOSFET is
turned on first to provide for charging of the bootstrap
capacitor. This method of driver activation provides support
for start-up into prebiased loads by not activating the drivers
until the control loop has entered its linear region, thereby
substantially reducing output transients that would otherwise
occur had the drivers been activated at the beginning of the
soft-start cycle.
the presence of switching noise on the input bus.
A 120ns blanking period is used to reduce the current
sampling error due to leading-edge switching noise. An
additional simultaneous 120ns low pass filter is used to
further reduce measurement error due to noise.
OCP faults cause the regulator to disable (top- and
bottom-side drives disabled, SSDONE pulled low, soft-start
capacitor discharged) itself for a fixed period of time, after
which a normal soft-start sequence is initiated. If the voltage
on the SS pin is already at 4V and an OCP is detected, a
30A current sink is immediately applied to the SS pin. If an
OCP is detected during soft-start, the 30µA current sink will
not be applied until the voltage on the SS pin has reached 4V.
SSDONE
Soft-start done is only available in the 16 Ld QFN packaging
option of the ISL8104. When the soft-start pin reaches 4V, an
open drain signal is provided to support sequencing
requirements. SSDONE is deasserted by disabling of the part,
including pulling SS low, and by POR and OCP events.
This current sink discharges the C capacitor in a linear
fashion. Once the voltage on the SS pin has reached
SS
approximately 0V, the normal soft-start sequence is initiated. If
the fault is still present on the subsequent restart, the ISL8104
FN9257 Rev 2.00
March 7, 2008
Page 7 of 14
ISL8104
will repeat this process in a hiccup mode. Figure 4 shows a
typical reaction to a repeated overcurrent condition that
places the regulator in a hiccup mode. If the regulator is
repeatedly tripping overcurrent, the hiccup period can be
approximated by Equation 5:
temperature range. System Accuracy includes Error Amplifier
offset, and Reference Error. The use of REFIN may add up to
3mV of offset error into the system (as the Error Amplifier
offset is trimmed out via the internal System reference).
Application Guidelines
2 4V C
SS
-------------------------------
=
t
(EQ. 5)
HICCUP
30A
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
The OCP trip point varies mainly due to MOSFET r
DS(ON)
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the R
resistor from the following equations with:
OCSET
1. The maximum r
temperature
at the highest junction
DS(ON)
2. The minimum I
from the specification table
TSOC
Determine the overcurrent trip point greater than the
+14V
VCC
maximum output continuous current at maximum inductor
ripple current.
C
BP_PVCC
BP_VCC
SIMPLE OCP EQUATION
PVCC
I
r
OC_SOURCE
DSON
----------------------------------------------------------------
=
R
C
TSOC
200A
ISL8104
VIN
C
DETAILED OCP EQUATION
I
2
----
I
+
r
IN
OC_SOURCE
DSON
TGATE
BOOT
Q
---------------------------------------------------------------------------------
R
=
1
TSOC
I
N
T
TSOC
N
= NUMBER OF TOP-SIDE MOSFETs
T
C
IN
L
OUT
C
V
OUT
V
- V
V
OUT
V
IN
IN
OUT
LX
------------------------------- ---------------
I =
f
L
SW
OUT
f
= Regulator Switching Frequency
OUT
SW
(EQ. 6)
BGATE
Q
2
High Speed MOSFET Gate Driver
SS
The integrated driver has the same drive capability and
feature as the Intersil’s 12V gate driver, ISL6612. The PWM
tri-state feature helps prevent a negative transient on the
output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the loads from reversed-output-voltage
damage. See the ISL6612 data sheet FN9153 for
C
SS
GND
PGND
KEY
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
specification parameters that are not defined in the current
ISL8104 “Electrical Specifications” table on page 4.
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
Reference Input
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option, the REFIN pin should be
left floating. An internal 6µA pull-up keeps this REFIN pin
above 2.2V in this situation.
A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that
capacitors C and C
could each represent numerous
IN OUT
physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the LX terminals to the output inductor short.
Internal Reference and System Accuracy
The Internal Reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.5% over the industrial
FN9257 Rev 2.00
March 7, 2008
Page 8 of 14
ISL8104
The power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the LX nodes. Use the remaining
printed circuit layers for small signal wiring.
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
Locate the ISL8104 within 2 to 3 inches of the MOSFETs, Q
1
V
at the LX node. The PWM wave is smoothed by the
IN
and Q (1 inch or less for 500kHz or higher operation). The
2
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
circuit traces for the MOSFETs’ gate and source connections
from the ISL8104 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin and
The modulator transfer function is the small-signal transfer
locate the capacitor, C close to the SS pin as the internal
function of V . This function is dominated by a
/V
ss
OUT COMP
current source is only 30µA. Provide local V decoupling
CC
DC gain and shaped by the output filter, with a double pole
between VCC and GND pins. Locate the capacitor, C
as
break frequency at F and a zero at F . For the purpose
BOOT
LC CE
close as practical to the BOOT pin and the phase node.
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
Compensating the Converter
This section highlights the design consideration for a voltage
mode controller requiring external compensation. To address a
broad range of applications, a type-3 feedback network is
recommended (see Figure 6).
1
1
(EQ. 7)
---------------------------
2 L C
F
=
---------------------------------
F
=
LC
CE
2 C ESR
The compensation network consists of the error amplifier
(internal to the ISL8104) and the external R to R , C to C
3
1
3
1
C
2
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F ; typically 0.1 to 0.3 of f ) and adequate phase
C
R
1
2
COMP
FB
0
SW
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F and 180°. The
C
0dB
3
equations that follow relate the compensation network’s poles,
R
1
ISL8104
R
zeros and gain to the components (R , R , R , C , C , and
3
1
2
3
1
2
VOUT
C ) in Figures 6 and 7. Use the following guidelines for
3
locating the poles and zeros of the compensation network:
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
ISL8104 CIRCUIT
1. Select a value for R (1k to 10k, typically). Calculate
1
value for R for desired converter bandwidth (F ). If
2
0
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented in Equation 8.
C
2
V
R F
1 0
V F
IN LC
OSC
(EQ. 8)
----------------------------------------------
=
R
C
R
3
2
3
D
R
C
MAX
2
1
COMP
As the ISL8104 supports 100% duty cycle, D
MAX
equals 1.
) of 1.9V,
-
FB
R
The ISL8104 uses a fixed ramp amplitude (V
1
OSC
+
E/A
Equation 8 simplifies to Equation 9:
VREF
1.9 R F
1
0
GND
-------------------------------
=
R
(EQ. 9)
2
V
F
LC
IN
2. Calculate C such that F is placed at a fraction of the F
,
1
Z1 LC
at 0.1 to 0.75 of F (to adjust, change the 0.5 factor in
LC
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio
V
OSCILLATOR
OUT
V
IN
V
F
/F , the lower the F frequency (to maximize
OSC
PWM
CE LC Z1
CIRCUIT
phase boost at F ).
LC
L
DCR
TGATE
LX
1
(EQ. 10)
(EQ. 11)
----------------------------------------------
C
=
HALF-BRIDGE
DRIVE
1
2 R 0.5 F
2
LC
C
3. Calculate C such that F is placed at F
.
2
P1 CE
ESR
BGATE
C
1
-------------------------------------------------------
=
C
2
2 R C F – 1
CE
2
1
ISL8104
EXTERNAL CIRCUIT
4. Calculate R such that F is placed at F . Calculate C
3
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
3
Z2
LC
such that F is placed below f
(typically, 0.3 to 1.0
P2
SW
FN9257 Rev 2.00
March 7, 2008
Page 9 of 14
ISL8104
times f ). f
SW SW
represents the switching frequency of the
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
regulator. Change the numerical factor (0.7) below to
reflect desired placement of this pole. Placement of F
lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
P2
the switching frequency, f
.
SW
R
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
F
F
F
P1
1
Z1 Z2
--------------------
R
=
3
f
SW
----------
– 1
(EQ. 12)
F
LC
F
P2
1
----------------------------------------------
2 R 0.7 f
C
=
3
3
SW
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equation 13 describes the frequency
R2
-------
20log
D
V
IN
R1
MAX
20log----------------------------------
V
0
OSC
G
FB
response of the modulator (G
), feedback compensation
MOD
G
CL
(G ) and closed-loop response (G ):
FB
CL
G
MOD
FREQUENCY
D
V
IN
1 + sf ESR C
MAX
V
------------------------------ -----------------------------------------------------------------------------------------------------------
LOG
G
f =
f =
MOD
F
F
CE
F
0
2
LC
OSC
1 + sf ESR + DCR C + s f L C
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
1 + sf R C
2
1
----------------------------------------------------
G
FB
sf R C + C
1
1
2
Component Selection Guidelines
1 + sf R + R C
3
1
3
-------------------------------------------------------------------------------------------------------------------------
Output Capacitor Selection
C
C
1
2
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
--------------------
1 + sf R C 1 + sf R
2
3
3
C
+ C
2
1
G
f = G
f G f
MOD FB
where sf = 2 f j
(EQ. 13)
CL
COMPENSATION BREAK FREQUENCY EQUATIONS
1
1
--------------------------------------------
F
=
------------------------------
F
=
P1
Z1
C
C
2
+ C
2
2 R C
1
For applications that have transient load rates above 1A/ns,
high frequency capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (effective series resistance) and voltage rating
2
1
--------------------
2 R
2
C
1
1
1
-------------------------------------------------
2 R + R C
------------------------------
2 R C
3
F
=
F
=
Z2
P2
1
3
3
3
(EQ. 14)
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
gain. Check the compensation gain at F against the
P2
capabilities of the error amplifier. The closed loop gain, G , is
CL
constructed on the log-log graph of Figure 8 by adding the
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
modulator gain, G
(in dB), to the feedback
MOD
compensation gain, G (in dB). This is equivalent to
FB
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
FN9257 Rev 2.00
March 7, 2008
Page 10 of 14
ISL8104
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
operation, select a bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage, a voltage rating of 1.5 times greater is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC load
current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by Equation 15:
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or
equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up. The
TPS series available from AVX, and the 593D series from
Sprague are both surge current tested.
V
- V
V
OUT
IN
OUT
------------------------------- ---------------
I =
(EQ. 15)
V
= I x ESR
OUT
Fs x L
V
IN
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
MOSFET Selection/Considerations
The ISL8104 requires at least 2 N-Channel power MOSFETs.
These should be selected based upon r
, gate supply
DS(ON)
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor current.
Given a sufficiently fast control loop design, the ISL8104 will
provide either 0% or 100% duty cycle in response to a load
transient. The response time is the time required to slew the
inductor current from an initial current value to the transient
current level. During this interval the difference between the
inductor current and the transient current level must be supplied
by the output capacitor. Minimizing the response time can
minimize the output capacitance required.
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. At a 300kHz switching
frequency, the conduction losses are the largest component of
power dissipation for both the top-side and the bottom-side
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor (see the following
equations). Only the top-side MOSFET exhibits switching
losses, since the schottky rectifier clamps the switching node
before the synchronous rectifier turns on.
The response time to a transient load is different for the
application of load and the removal of load. Equation 16 gives
the approximate response time interval for application and
removal of a transient load:
1
2
2
P
= I x r
O
x D + Io x V x t
x f
top-side
DS(ON)
IN SW SW
L
I
L I
O TRAN
2
O
TRAN
P
= I x r
x (1 - D)
bottom-side
O
DS(ON)
-------------------------------
------------------------------
t
=
t
=
FALL
(EQ. 16)
is the
RISE
V
– V
V
IN
OUT
OUT
where: D is the duty cycle = V / V
IN
,
O
where: I
is the transient load current step, t
RISE
t
is the switching interval, and
is the switching frequency.
TRAN
response time to the application of load, and t
SW
SW
is the
(EQ. 17)
f
FALL
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application
or removal of load and dependent upon the output voltage
setting. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Equation 17 assumes linear voltage-current transitions and
does not adequately model power loss due to the
reverse-recovery of the bottom-side MOSFETs body diode.
The gate-charge losses are dissipated by the ISL8104 and
don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
which increases the
SW
Input Capacitor Selection
top-side MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply the
current needed each time Q1 turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
drain of Q and the source of Q .
1
2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
Standard-gate MOSFETs are normally recommended for use
with the ISL8104. However, logic-level gate MOSFETs can be
FN9257 Rev 2.00
March 7, 2008
Page 11 of 14
ISL8104
used under special circumstances. The input voltage, top-side
gate drive level, and the MOSFETs absolute gate-to-source
voltage rating determine whether logic-level MOSFETs are
appropriate.
+14V
D
BOOT
-
+1.2V TO +14V
+
V
D
ISL8104
BOOT
Figure 9 shows the top-side gate drive (BOOT pin) supplied by
C
BOOT
a bootstrap circuit from +14V. The boot capacitor, C
BOOT
Q1
develops a floating supply voltage referenced to the LX pin.
This supply is refreshed each cycle to a voltage of +14V less
TGATE
LX
NOTE:
VG-S V - V
CC D
the boot diode drop (V ) when the bottom-side MOSFET, Q
D
2
turns on. A MOSFET can only be used for Q if the MOSFETs
absolute gate-to-source voltage rating exceeds the maximum
1
+14V
PVCC
D2
Q2
voltage applied to +14V. For Q , a logic-level MOSFET can be
used if its absolute gate-to-source voltage rating also exceeds
the maximum voltage applied to +14V.
2
BGATE
PGND
-
NOTE:
G-S PVCC
+
V
GND
Figure 10 shows the top-side gate drive supplied by a direct
connection to +14V. This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak top-side gate-to-source voltage is
FIGURE 9. TOP-SIDE GATE DRIVE - BOOTSTRAP OPTION
approximately +14V less the input supply. For +5V main power
and +14VDC for the bias, the gate-to-source voltage of Q is
1
9V. A logic-level MOSFET is a good choice for Q and a logic-
1
+14V
level MOSFET can be used for Q if its absolute gate-to-
2
+5V OR LESS
source voltage rating exceeds the maximum voltage applied to
PVCC. This method reduces the number of required external
components, but does not provide for immunity to phase node
ringing during turn on and may result in lower system
efficiency.
ISL8104
BOOT
Q1
TGATE
NOTE:
V
G-S V - 5V
CC
Schottky Selection
+14V
Rectifier D2 is a clamp that catches the negative inductor swing
during the dead time between turning off the bottomside
MOSFET and turning on the top-side MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET body
diode from conducting. It is acceptable to omit the diode and let
the body diode of the bottom-side MOSFET clamp the negative
inductor swing, but efficiency could slightly decrease as a result.
The diode's rated reverse breakdown voltage must be greater
than the maximum input voltage.
PVCC
D2
Q2
BGATE
PGND
-
NOTE:
G-S PVCC
+
V
GND
FIGURE 10. TOP-SIDE GATE DRIVE - DIRECT V
OPTION
DRIVE
CC
FN9257 Rev 2.00
March 7, 2008
Page 12 of 14
ISL8104
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2006-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9257 Rev 2.00
March 7, 2008
Page 13 of 14
ISL8104
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
1.95
1.95
0.28
0.35
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.65 BSC
-
k
0.25
0.50
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
-
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9257 Rev 2.00
March 7, 2008
Page 14 of 14
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+5V or +12V Single-Phase Synchronous Buck Converter PWM Controller with Integrated MOSFET Gate Drivers
INTERSIL
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