ISL78228ARZ-T13 [RENESAS]
DUAL SWITCHING CONTROLLER;
| 型号： | ISL78228ARZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL SWITCHING CONTROLLER 开关 |
| 文件： | 总18页 (文件大小：1464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 800mA Low Quiescent Current 2.25MHz High
Efficiency Synchronous Buck Regulator
ISL78228
Features
The ISL78228 is a high efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 800mA continuous
output current per channel. The supply voltage range of 2.75V
to 5.5V allows for the use of a 3.3V or 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78228 operates above the AM
radio band as well as the 2.25MHz switching frequency,
allowing for the use of small, low cost inductors and
capacitors. Each channel is optimized for generating an output
voltage as low as 0.6V.
• Internal Current Mode Compensation
• 100% Maximum Duty Cycle for Lowest Dropout
• Selectable Forced PWM Mode and PFM Mode
• External Synchronization up to 4MHz
• Start-up with Pre-biased Output
• Soft-Stop Output Discharge During Disabled
• Internal Digital Soft-Start - 2ms
• Power-Good (PG) Output with 1ms Delay
• AEC-Q100 Tested
The ISL78228 has a user configurable mode of
• Pb-free (RoHS Compliant)
operation-forced PWM mode and PFM/PWM mode. The forced
PWM mode operation reduces noise and RF interference while
the PFM mode operation provides high efficiency by reducing
switching losses at light loads. In PFM mode of operation, both
channels draw a total quiescent current of only 30µA, hence
enabling high light load efficiency in order to maximize battery
life.
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Rear Camera Systems
• Navigation Systems
The ISL78228 offers a 1ms Power-Good (PG) to monitor both
outputs at power-up. When shutdown, ISL78228 discharges
the outputs capacitor. Other features include internal digital
soft-start, enable for power sequence, overcurrent protection,
and thermal shutdown. The ISL78228 is offered in a
• Infotainment Systems
3mmx3mm 10 Ld DFN package with 1mm maximum height.
2
The complete converter occupies less than 1.8cm area.
The ISL78228 is AEC-Q100 rated. The ISL78228 is rated for
the automotive temperature range (-40°C to +105°C).
100
90
80
2.5V
-PFM
OUT
1.8V
70
-PFM
OUT
-PWM
2.5V
OUT
60
50
40
1.8V
-PWM
OUT
VIN = 5V
0.0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY CHARACTERISTICS CURVE
December 4, 2013
FN7849.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL78228
Typical Application
L1
2.2µH
OUTPUT1
2.5V/800mA
LX1
C2
10µF
C3
10pF
PGND
FB1
R2
316k
INPUT 2.75V TO 5.5V
VIN
EN1
R3
100k
C1
10µF
ISL78228
EN2
L2
2.2µH
OUTPUT2
1.8V/800mA
LX2
PG
C4
10µF
C5
10pF
PGND
FB2
R5
SYNC
200k
R6
100k
PGND
FN7849.2
December 4, 2013
2
ISL78228
Pin Configuration
ISL78228
(10 LD 3X3 DFN)
TOP VIEW
FB1
FB2
1
2
3
4
5
10
EN1
VIN
LX1
NC
EN2
PG
9
8
7
6
PAD
LX2
SYNC
Pin Descriptions
DFN
SYMBOL
DESCRIPTION
1
FB1
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to any
voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1
regulator output voltage.
2
EN1
Regulator Channel 1 enable pin. Enable the output, V
OUT1
, when driven to high. Shutdown the V and discharge output
OUT1
capacitor when driven to low. Do not leave this pin floating.
3
4
5
6
VIN
LX1
NC
Input supply voltage. Connect 10µF ceramic capacitor to power ground.
Switching node connection for Channel 1. Connect to one terminal of inductor for V
Recommended to connect this pin to the exposed pad.
.
OUT1
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM mode.
Connect to an external function generator for Synchronization, and negative edge trigger. Do not leave this pin floating.
7
8
LX2
PG
Switching node connection for Channel 2. Connect to one terminal of inductor for V .
OUT2
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the V
and V voltages.
OUT2
OUT1
There is an internal 1MΩ pull-up resistor.
9
EN2
FB2
Regulator Channel 2 enable pin. Enable the output, V
OUT2
capacitor when driven to low. Do not leave this pin floating.
, when driven to high. Shutdown the V and discharge output
OUT2
10
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to any
voltage between the power-rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2 regulator output voltage.
-
PAD
The exposed pad must be connected to PGND for proper electrical performance. Add as much vias as possible for optimal thermal
performance.
Ordering Information
PART NUMBER
PART
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2, 3)
MARKING
ISL78228ARZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
8228
-40 to +105
10 Ld 3x3 DFN
L10.3x3C
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78228. For more information on MSL please see techbrief TB363.
FN7849.2
December 4, 2013
3
ISL78228
Absolute Maximum Ratings (Reference to GND)
Thermal Information
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Thermal Resistance (Typical)
θJA (°C/W)
θJC(°C/W)
IN
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V (20ms)
10 Ld 3x3 DFN Package (Notes 4, 5) . . . . . .
49
4
IN
EN1, EN2, PG, SYNC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to V + 0.3V
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
IN
LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to 7V (20ms)
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Recommended Operating Conditions
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD78C; Class II, Level A) . . . . . . . . . . . . . . . 100mA
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75V to 5.5V
IN
Load Current Range Per Channel. . . . . . . . . . . . . . . . . . . . . 0mA to 800mA
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating
conditions: T = -40°C to +105°C, V = 2.75V to 5.5V, EN1 = EN2 = V , SYNC = 0V, L = 2.2µH, C = 10µF, C = C = 10µF,
A
OUT2
-40°C to +105°C.
IN
IN
1
2
4
I
= I
= 0A to 800mA. (Typical values are at T = +25°C, V = 3.6V). Boldface limits apply over the operating temperature range,
OUT1
A
IN
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
INPUT SUPPLY
Undervoltage Lockout Threshold
V
V
Rising
Falling
2.5
2.4
30
2.75
50
V
V
IN
UVLO
2.1
Quiescent Supply Current
I
SYNC = V , EN1 = EN2 = V , no load at the
IN IN
µA
VIN
output and no switches switching.
VFB1 = VFB2 = 0.7V
SYNC = GND, EN1 = EN2 = VIN,
0.1
6.5
1
mA
µA
F
= 2.25MHz, no load at the output
S
Shut Down Supply Current
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Line Regulation
I
V
= 5.5V, EN1 = EN2 = GND
IN
12
SD
V
0.590
0.6
0.1
0.2
0.610
V
FB_
I
VFB = 0.55V
µA
FB_
V
= V + 0.5V to 5.5V (minimal 2.75V,
%/V
IN
O
I
= 0A)
OUT
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Peak Overcurrent Limit
2
ms
I
I
0.95
0.95
180
180
1.2
1.2
1.6
1.6
A
pk1
pk2
A
Peak SKIP Limit
I
I
V
= 3.6V
250
250
360
360
mA
mA
skip1
skip2
IN
LX1, LX2
P-Channel MOSFET ON-Resistance
V
V
V
V
= 5.5V, I = 200mA
180
320
180
320
350
450
350
450
mΩ
mΩ
mΩ
mΩ
IN
IN
IN
IN
O
= 2.75V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 5.5V, I = 200mA
O
= 2.75V, I = 200mA
O
FN7849.2
December 4, 2013
4
ISL78228
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating
conditions: T = -40°C to +105°C, V = 2.75V to 5.5V, EN1 = EN2 = V , SYNC = 0V, L = 2.2µH, C = 10µF, C = C = 10µF,
A
OUT2
IN
IN
1
2
4
I
= I
= 0A to 800mA. (Typical values are at T = +25°C, V = 3.6V). Boldface limits apply over the operating temperature range,
OUT1
A
IN
-40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
LX_ Maximum Duty Cycle
PWM Switching Frequency
Synchronization Range
LX Minimum On-Time
Soft Discharge Resistance
PG
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
100
2.25
(Note 6)
UNITS
%
F
1.8
2.7
2.7
4
MHz
MHz
ns
S
SYNC = 0 (forced PWM mode)
EN = LOW
100
130
R
80
100
Ω
DIS_
Output Low Voltage
Sinking 1mA, VFB = 0.5V
0.3
V
PG Pull-up Resistor
1
92
89
1
mΩ
mΩ
%
Internal P
Internal P
Low Rising Threshold
Low Falling Threshold
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
88
82
96
91
GOOD
GOOD
Delay Time (Rising Edge)
Internal P Delay Time (Falling Edge)
ms
µs
1
2
GOOD
EN1, EN2, SYNC
Logic Input Low
0.4
V
Logic Input High
1.4
V
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
I
Pulled up to 5.5V
0.1
0.1
150
25
1
1
µA
µA
°C
°C
SYNC
I
EN_
Thermal Shutdown Hysteresis
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7849.2
December 4, 2013
5
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
IN
1
2
1
2
4
OUT1
OUT1
0A to 800mA.
100
90
100
90
80
70
60
50
40
80
2.5V
- PWM
OUT
2.5V
OUT
- PFM
- PFM
70
60
50
40
1.5V
- PWM
OUT
1.8V
- PFM
OUT
1.2V
- PWM
1.2V
OUT
1.5V
- PFM
OUT
OUT
1.8V
OUT -
PWM
0.0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD 2.25MHz 3.3V PFM
IN
FIGURE 2. EFFICIENCY vs LOAD 2.25MHz 3.3V PWM
IN
100
100
90
80
70
60
50
40
90
80
70
60
50
40
2.5V
- PWM
OUT
1.5V
OUT
- PFM
3.3V
- PFM
3.3V
0.1
- PWM
1.2V
1.5V
- PWM
OUT
OUT
1.2V
0.3
- PFM
2.5V
OUT
OUT
- PWM
1.8V
- PWM
OUT
OUT
1.8V
- PFM
- PFM
OUT
OUT
0.0
0.1
0.2
0.4
0.5
0.6
0.7
0.8
0.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD 2.25MHz 5V PWM
IN
FIGURE 5. EFFICIENCY vs LOAD 2.25MHz 5V PFM
IN
0.30
0.25
0.20
0.15
0.10
0.05
0.00
1.23
1.22
1.21
1.20
1.19
1.18
1.17
5V
PFM MODE
IN
3.3V
- PWM MODE
IN
5V
PWM MODE
IN
5V
IN
- PWM MODE
5V
IN
- PFM MODE
3.3V V
PFM
3.3V V
IN
PWM
IN
3.3V
IN
- PFM
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 7. V
REGULATION vs LOAD 2.25MHz 1.2V
PFM
OUT
FIGURE 6. POWER DISSIPATION vs LOAD 2.25MHz 1.8V
PWM
OUT
OUT
FN7849.2
December 4, 2013
6
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
= 2.5V, V
= 1.8V, I
= I
=
OUT2
IN
IN
1
2
1
2
4
OUT1
OUT2
OUT1
0A to 800mA. (Continued)
1.56
1.84
5 V
PFM MODE
5 V
PFM MODE
IN
IN
1.55
1.54
1.53
1.52
1.51
1.50
1.83
3.3V V
PFM
IN
1.82
1.81
3.3V V
PFM
IN
5V
PWM MODE
IN
1.80
1.79
1.78
3.3V V
PWM
IN
3.3V V
PWM
IN
5V
PWM MODE
IN
0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 9. V
REGULATION vs LOAD 2.25MHz 1.8V
OUT
FIGURE 8. V
REGULATION vs LOAD 2.25MHz 1.5V
OUT
OUT
OUT
2.55
3.42
2.54
2.53
2.52
2.51
2.50
2.49
3.40
3.38
3.36
3.34
3.32
3.30
5V V
PFM
IN
5V V
IN
PFM
3.3V V
PFM
IN
3.3V V
5V V
PWM
IN
5V V
IN
PWM
PWM
IN
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. V
REGULATION vs LOAD 2.25MHz 3.3V
FIGURE 10. V
REGULATION vs LOAD 2.25MHz 2.5V
OUT
OUT
OUT
OUT
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.83
1.82
1.81
1.80
1.79
1.78
1.77
0A LOAD
0A LOAD PWM
0.4A LOAD
0.8A LOAD
0.4A LOAD PWM
0.8A LOAD PWM
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 12. OUTPUT VOLTAGE REGULATION vs V 1.8V
IN
FIGURE 13. OUTPUT VOLTAGE REGULATION vs V 1.8V
IN
OUT
OUT
PWM MODE
PFM MODE
FN7849.2
December 4, 2013
7
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
IN OUT1
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
1
2
1
2
4
OUT1
0A to 800mA. (Continued)
500ns/DIV
500ns/DIV
LX1 2V/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT1
I
0.5A/DIV
I
0.5A/DIV
L1
L2
FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
(PWM)
FIGURE 14. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
(PWM)
LX1 2V/DIV
500ns/DIV
500ns/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
0.5A/DIV
OUT2
I
0.5A/DIV
L1
I
L2
FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
(PFM)
FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
(PFM)
LX2 2V/DIV
LX1 2V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT2
OUT1
I
0.5A/DIV
L1
500ns/DIV
I
0.5A/DIV
L2
500ns/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD
CHANNEL 2
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD
CHANNEL 1
FN7849.2
December 4, 2013
8
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
0A to 800mA. (Continued)
IN
1
2
1
2
4
OUT1
OUT1
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT1
OUT2
I
0.5A/DIV
L1
I 0.5A/DIV
L2
50µs/DIV
50µs/DIV
FIGURE 21. LOAD TRANSIENT CHANNEL 2 (PWM)
FIGURE 20. LOAD TRANSIENT CHANNEL 1 (PWM)
LX2 2V/DIV
LX1 2V/DIV
V
RIPPLE 50mV/DIV
OUT1
V
RIPPLE 50mV/DIV
OUT2
50µs/DIV
50µs/DIV
I
0.5A/DIV
I
0.5A/DIV
L2
L1
FIGURE 23. LOAD TRANSIENT CHANNEL 2 (PFM)
FIGURE 22. LOAD TRANSIENT CHANNEL 1 (PFM)
50µs/DIV
50µs/DIV
EN2 2V/DIV
V
0.5V/DIV
EN1 2V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
I
0.5A/DIV
L1
PG 5V/DIV
PG 5V/DIV
FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 1 (PWM)
FIGURE 25. SOFT-START WITH NO LOAD CHANNEL 2 (PWM)
FN7849.2
December 4, 2013
9
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
IN
1
2
1
2
4
OUT1
OUT1
0A to 800mA. (Continued)
50µs/DIV
50µs/DIV
EN2 2V/DIV
EN1 2V/DIV
V
0.5V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
0.5A/DIV
I
L
PG 5V/DIV
PG 5V/DIV
FIGURE 26. SOFT-START AT NO LOAD CHANNEL 1 (PFM)
FIGURE 27. SOFT-START AT NO LOAD CHANNEL 2 (PFM)
50µs/DIV
50µs/DIV
EN1 2V/DIV
EN2 2V/DIV
V
1V/DIV
OUT1
V
0.5V/DIV
OUT2
I
0.5A/DIV
L1
I
0.5A/DIV
L2
PG 5V/DIV
PG 5V/DIV
FIGURE 28. SOFT-START AT FULL LOAD CHANNEL 1
FIGURE 29. SOFT-START AT FULL LOAD CHANNEL 2
EN2 5V/DIV
1ms/DIV
1ms/DIV
EN1 5V/DIV
V
0.5V/DIV
OUT2
V
1V/DIV
OUT1
I
0.5A/DIV
L2
I
0.5A/DIV
L1
PG 5V/DIV
PG 5V/DIV
FIGURE 31. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 30. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FN7849.2
December 4, 2013
10
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
IN OUT1
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
1
2
1
2
4
OUT1
0A to 800mA. (Continued)
200ns/DIV
200ns/DIV
LX1 2V/DIV
LX1 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
V
RIPPLE 20mV/DIV
I
0.5A/DIV
OUT1
L1
V
0.5A/DIV
RIPPLE 20mV/DIV
I
OUT1
L1
FIGURE 32. CH1 STEADY STATE OPERATION AT NO LOAD (PFM)
WITH FREQUENCY = 4MHz
FIGURE 33. CH1 STEADY STATE OPERATION AT FULL LOAD (PFM)
WITH FREQUENCY = 4MHz
200ns/DIV
200ns/DIV
LX2 2V/DIV
LX2 2V/DIV
SYNCH 2V/DIV
SYNCH 2V/DIV
I
0.5A/DIV
L2
V
RIPPLE 20mV/DIV
OUT2
V
RIPPLE 20mV/DIV
OUT2
I
0.5A/DIV
L2
FIGURE 35. CH2 STEADY STATE OPERATION AT FULL LOAD (PFM)
WITH FREQUENCY = 4MHz
FIGURE 34. CH2 STEADY STATE OPERATION AT NO LOAD (PFM)
WITH FREQUENCY = 4MHz
100ns/DIV
LX1 5V/DIV
100ns/DIV
LX1 5V/DIV
LX2 5V/DIV
LX2 5V/DIV
SYNCH 5V/DIV
SYNCH 5V/DIV
V
RIPPLE 20mV/DIV
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
RIPPLE 20mV/DIV
OUT1
V
V
OUT2
OUT2
FIGURE 37. CH1 AND CH2 STEADY STATE OPERATION AT FULL LOAD
(PFM) WITH FREQUENCY = 4MHz
FIGURE 36. CH1 AND CH2 STEADY STATE OPERATION AT NO LOAD
(PFM) WITH FREQUENCY = 4MHz
FN7849.2
December 4, 2013
11
ISL78228
Typical Operating Performance
Unless otherwise noted, operating conditions are: T = +25°C,
A
V
= 2.75V to 5.5V, EN = V , L = L = 2.2µH, C = 10µF, C = C = 10µF, V
= 2.5V, V
OUT2
= 1.8V, I
= I
=
OUT2
IN
IN
1
2
1
2
4
OUT1
OUT1
0A to 800mA. (Continued)
PHASE1 5V/DIV
LX1 5V/DIV
I
0.5A/DIV
L1
V
1V/DIV
OUT1
V
1V/DIV
I
0.5A/DIV
OUT1
L1
500µs/DIV
10µs/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 38. OUTPUT SHORT CIRCUIT CHANNEL 1
FIGURE 39. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 1
500µs/DIV
10µs/DIV
PHASE2 5V/DIV
LX2 5V/DIV
V
0.5V/DIV
OUT2
I
0.5A/DIV
L2
I
0.5A/DIV
L2
V
1V/DIV
OUT2
PG 5V/DIV
PG 5V/DIV
FIGURE 40. OUTPUT SHORT CIRCUIT CHANNEL 2
FIGURE 41. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 2
2.4
2.0
1.6
1.2
V
6V I
OC
OUT2
IN
V
6V I OC
OUT1
IN
V
3.5V I
-30
OC
0.8
0.4
0
IN
OUT2
-10
V
3.5V I
OC
OUT1
IN
-50
10
20
50
70
90
110
TEMPERATURE (°C)
FIGURE 42. OUTPUT CURRENT LIMIT vs TEMPERATURE
FN7849.2
December 4, 2013
12
ISL78228
Block Diagram
SHUTDOWN
SOFT-
START
27pF
200k
SHUTDOWN
VIN
+
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
EN1
0.6V
BANDGAP
+
+
EAMP
LX1
COMP
-
-
3pF
PGND
SLOPE
COMP
+
+
FB1
CSA1
+
-
SCP
0.3V
1.6k
-
+
OCP
0.59V
-
+
PG1
SKIP
0.09V
+
OSCILLATOR
-
VIN
0.552V
-
ZERO-CROSS
SENSING
1M
PG
1ms
DELAY
SGND
SYNC
SHUTDOWN
SHUTDOWN
THERMAL
SHUTDOWN
27pF
SOFT-
START
SHUTDOWN
200k
+
VIN
EN2
0.6V
+
BANDGAP
+
EAMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
COMP
-
-
LX2
3pF
PGND
SLOPE
COMP
+
+
FB2
CSA2
-
-
SCP
0.3V
+
1.6k
+
OCP
0.59V
0.09V
-
+
0.552V
-
+
PG2
SKIP
-
ZERO-CROSS
SENSING
FN7849.2
December 4, 2013
13
ISL78228
operation during the start-up and will be discussed separately
Theory of Operation
shortly. The error amplifier is a transconductance amplifier that
converts the voltage error signal to a current output. The voltage
loop is internally compensated with the 27pF and 200kΩ RC
network. The maximum EAMP voltage output is precisely
clamped to 0.8V.
The ISL78228 is a dual 800mA step-down switching regulator
optimized for battery-powered or mobile applications. The
regulator operates at 2.25MHz fixed switching frequency under
heavy load conditions to allow small external inductor and
capacitors to be used for minimal printed-circuit board (PCB)
area. At light load, the regulator reduces the switching frequency,
unless forced to the fixed frequency, to minimize the switching
loss and to maximize the battery life. The two channels are
in-phase operation. The quiescent current when the outputs are
not loaded is typically only 30µA. The supply current is typically
only 6.5µA when the regulator is shut down.
V
EAMP
V
CSA
DUTY
CYCLE
PWM Control Scheme
I
L
Pulling the SYNC pin LOW (<0.4V) forces the converter into PWM
mode in the next switching cycle regardless of output current. Each
of the channels of the ISL78228 employ the current-mode
pulse-width modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting shown in the “Block
Diagram” on page 13. The current loop consists of the oscillator,
the PWM comparator COMP, current sensing circuit, and the slope
compensation for the current loop stability. The current sensing
circuit consists of the resistance of the P-Channel MOSFET when it
is turned on and the current sense amplifier CSA1 (or CSA2 on
Channel 2). The gain for the current sensing circuit is typically
0.285V/A. The control reference for the current loops comes from
the error amplifier EAMP of the voltage loop.
V
OUT
FIGURE 43. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin HIGH (>2.0V) forces the converter into PFM
mode. The ISL78228 enters a pulse-skipping mode at light load
to minimize the switching loss by reducing the switching
frequency. Figure 44 illustrates the skip-mode operation. A
zero-cross sensing circuit shown in the “Block Diagram” on
page 13 monitors the N-MOSFET current for zero crossing. When
8 consecutive cycles of the N-MOSFET crossing zero are detected,
the regulator enters the skip mode. During the 8 detecting cycles,
the current in the inductor is allowed to become negative. The
counter is reset to zero when the current in any cycle does not
cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier CSA1 (or CSA2) and the
compensation slope (0.33V/µs) reaches the control reference of
the current loop, the PWM comparator COMP sends a signal to the
PWM logic to turn off the P-MOSFET and to turn on the N-Channel
MOSFET. The N-MOSFET stays on until the end of the PWM cycle.
Figure 43 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA-output.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in the “Block Diagram”
on page 13. Each pulse cycle is still synchronized by the PWM
clock. The P-MOSFET is turned on at the clock and turned off
when its current reaches the threshold of 250mA. As the average
inductor current in each cycle is higher than the average current
of the load, the output voltage rises cycle over cycle. When the
output voltage reaches 1.5% above the nominal voltage, the
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.6V
reference voltage to the voltage control loop. The feedback signal
comes from the V pin. The soft-start block only affects the
FB
PWM
PFM
CLOCK
8 CYCLES
PFM CURRENT LIMIT
I
L
LOAD CURRENT
0
NOMINAL +1.5%
V
OUT
NOMINAL
FIGURE 44. SKIP MODE OPERATION WAVEFORMS
FN7849.2
December 4, 2013
14
ISL78228
P-MOSFET is turned off immediately. Then the inductor current is
Soft-Start-Up
fully discharged to zero and stays at zero. The output voltage
reduces gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-MOSFET will be turned on again at the clock, repeating the
previous operations.
The soft-start-up eliminates the in-rush current during the
start-up. The soft-start block outputs a ramp reference to both
the voltage loop and the current loop. The two ramps limit the
inductor current rising speed as well as the output voltage speed
so that the output voltage rises in a controlled fashion. At the
very beginning of the start-up, the output voltage is less than
0.2V; hence the PWM operating frequency is 1/3 of the normal
frequency.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
Synchronization Control
The frequency of operation can be synchronized up to 4MHz by
an external signal applied to the SYNC pin. The falling edge on
the SYNC triggered the rising edge of the PWM ON pulse.
In force PWM mode, the IC will continue to start-up in PFM mode
to support pre-biased load applications.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, or the output
undervoltage fault latch is set, the outputs discharge to GND
through an internal 100Ω switch.
Overcurrent Protection
CSA1 and CSA2 are used to monitor output 1 and output 2
channels respectively. The overcurrent protection is realized by
monitoring the CSA_ output with the OCP threshold logic, as
shown in “Block Diagram” on page 13. The current sensing
circuit has a gain of 0.285V/A, from the P-MOSFET current to the
CSA_output. When the CSA_ output reaches the threshold of
590mV, the OCP comparator is tripped to turn off the P-MOSFET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFETs.
Power MOSFETs
The power MOSFETs are optimize for best efficiency. The
ON-resistance for the P-MOSFET is typically 180mΩ and the
ON-resistance for the N-MOSFET is typical 180mΩ.
100% Duty Cycle
The ISL78228 features 100% duty cycle operation to maximize
the battery life. When the battery voltage drops to a level that the
ISL78228 can no longer maintain the regulation at the output,
the regulator completely turns on the P-MOSFET. The maximum
dropout voltage under the 100% duty-cycle operation is the
product of the load current and the ON-resistance of the
P-MOSFET.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle.
PG
The power-good signal, (PG) monitors both of the output
channels. When powering up, the open-collector power-on-reset
output holds low for about 1ms after V and V reaches the
preset voltages. The PG output also serves as a 1ms delayed
Power-Good signal. If one of the output is disabled, then PG only
monitors the active channels. There is an internal 1MΩ pull-up
resistor.
Thermal Shut-Down
The ISL78228 has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +130°C, the ISL78228
resumes operation by stepping through a soft-start-up.
O1
O2
Applications Information
TABLE 1. PG
PG1
INTERNAL
PG2
INTERNAL
Output Inductor and Capacitor Selection
EN1
0
EN2
0
PG
0
To consider steady state and transient operation, ISL78228
typically uses a 2.2µH output inductor. Higher or lower inductor
values can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
applications, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
The inductor ripple current can be expressed as shown in
Equation 1:
X
X
1
1
X
1
X
1
0
1
1
1
0
1
1
1
1
UVLO
When the input voltage is below the undervoltage lock out (UVLO)
threshold, the regulator is disabled.
V
⎛
⎜
⎝
⎞
⎟
⎠
O
--------
V
•
1 –
O
V
IN
(EQ. 1)
-----------------------------------
ΔI =
L • f
S
Enable
The enable (EN1, EN2) input allows the user to control the turning
on or off of the regulator for purposes such as power-up
sequencing. The regulator is enabled, there is typically a 600µs
delay for waking up the bandgap reference, then the soft start-up
begins.
The inductor’s saturation current rating needs be at least larger
than the peak current. The ISL78228 protects the typical peak
current 1.2A. The saturation current needs be over 1.8A for
maximum output current application.
FN7849.2
December 4, 2013
15
ISL78228
ISL78228 uses internal compensation network and the output
Input Capacitor Selection
capacitor value is dependent on the output voltage. The ceramic
capacitor is recommended to be X5R or X7R. The recommended
minimum output capacitor values are shown in Table 2 for the
ISL78228.
The main functions of the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. One 10µF X5R or X7R ceramic capacitor is a good
starting point for the input capacitor selection for both channels.
TABLE 2. OUTPUT CAPACITOR VALUE vs V
OUT
ISL78228
V
C
(µF)
L
(µH)
OUT
OUT
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL78228, the power
loop is composed of the output inductor (L’s), the output
(V)
0.8
1.2
1.6
1.8
2.5
3.3
3.6
10
1.0~2.2
1.0~2.2
1.0~2.2
1.5~3.3
1.5~3.3
1.5~4.7
1.5~4.7
10
capacitor (COUT1 and C
), the LX’s pins, and the GND pin. It is
OUT2
10
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short and wide.
The switching node of the converter, the LX_ pins, and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as closely as possible to the VIN pin. The ground
of input and output capacitors should be connected as closely as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
10
10
6.8
8.6
In Table 2, the minimum output capacitor value is given for
different output voltages to make sure the whole converter
system is stable.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to “Typical
Application” on page 2.
The output voltage programming resistor, R (or R in
2
5
Channel 2), will depend on the desired output voltage of the
regulator. The value for the feedback resistor is typically between
0Ω and 750kΩ, as shown in Equation 2.
Let R = 100kΩ, then R will be:
3
2
V
⎛
⎜
⎝
⎞
OUT
(EQ. 2)
------------
R
= R
– 1
⎟
2
3
V
⎠
FB
If the output voltage desired is 0.6V, then R is left unpopulated
3
and short R . For faster response performance, add 47pF in
2
parallel to R .
2
FN7849.2
December 4, 2013
16
ISL78228
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7849.2
CHANGE
December 4, 2013
Page 1:
changed last paragraph in description from:
“The ISL78228 is rated for the automotive temperature range (-40°C to +105°C).”
to:
“The ISL78228 is AEC-Q100 rated. The ISL78228 is rated for the automotive temperature range
(-40°C to +105°C).”
Features bullet changed from: “Qualified for automotive applications” to: “AEC-Q100 Tested”
October 22, 2013
May 2, 2011
FN7849.1
FN7849.0
Page 1 - Added the words "Qualified for automotive applications" under the Features section
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7849.2
December 4, 2013
17
ISL78228
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 3, 10/11
5
3.00
A
B
PIN #1 INDEX AREA
10
1
2
5
PIN 1
INDEX AREA
10 x 0.25
6
C B
0.10
(4X)
1.64
10x 0.40
TOP VIEW
BOTTOM VIEW
C B
M
0.10
(4X)
SEE DETAIL "X"
0.10
(10 x 0.60)
(10x 0.25)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
2.80 TYP
4
0.20 REF
0.05
C
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
4.
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
6.
COMPLIANT TO JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN7849.2
December 4, 2013
18
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