ISL78233AARZ-T [RENESAS]
3A Compact Synchronous Buck Regulator; TQFN16, WFQFN16; Temp Range: -40° to 125°C;
| 型号： | ISL78233AARZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3A Compact Synchronous Buck Regulator; TQFN16, WFQFN16; Temp Range: -40° to 125°C |
| 文件： | 总21页 (文件大小：2210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL78233, ISL78234
3A and 4A Compact Synchronous Buck Regulators
FN8359
Rev.9.00
Feb 21, 2019
The ISL78233 and ISL78234 are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 3A
(ISL78233), or 4A (ISL78234) of continuous output current from
a 2.7V to 5.5V input supply. The devices use current mode control
architecture to deliver a very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
Features
• 2.7V to 5.5V input voltage range
• Very low ON-resistance FETs - P-channel 35mΩ and
N-channel 11mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
The ISL78233 and ISL78234 integrate a very low
ON-resistance P-channel (35mΩ) high-side FET and N-channel
(11mΩ) low-side FET to maximize efficiency and minimize
external component count. The 100% duty-cycle operation
allows less than 200mV dropout voltage at 4A output current.
The operation frequency of the Pulse-Width Modulator (PWM)
is adjustable from 500kHz to 4MHz. The default switching
frequency of 2MHz is set by connecting the FS pin high.
• -1.2%/1% reference accuracy over temperature/load/line
• Complete BOM with as few as 3 external parts
• Internal soft-start - 1ms or adjustable
• Soft-stop output discharge during disable
• Adjustable frequency from 500kHz to 4MHz - default at
2MHz
The ISL78233 and ISL78234 can be configured for
discontinuous or forced continuous operation at light load.
Forced continuous operation reduces noise and RF
interference, while discontinuous mode provides higher
efficiency by reducing switching losses at light loads.
• External synchronization up to 4MHz
• Over-temperature, overcurrent, overvoltage, and negative
overcurrent protection
• Shared common device pinout allows simplified output
power upgrades over time
Fault protection is provided by internal Hiccup mode current
limiting during short-circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
• Tiny 3mmx3mm TQFN package
• AEC-Q100 qualified
Applications
• DC/DC POL modules
The ISL78233 and ISL78234 offer a 1ms Power-Good (PG)
timer at power-up. When in shutdown, the ISL78233 and
ISL78234 discharge the output capacitor through an internal
soft-stop switch. Other features include internal fixed or
adjustable soft-start and internal/external compensation.
• μC/µP, FPGA, and DSP power
• Video processor/SOC power
• Li-ion battery powered devices
• Automotive infotainment power
The ISL78233 and ISL78234 are available in a 3mmx3mm 16
Ld Thin Quad Flat (TQFN) Pb-free package and in a 5mmx5mm
16 Ld Wettable Flank Quad Flat No-Lead (WFQFN) package
with an exposed pad for improved thermal performance. The
ISL78233 and ISL78234 are rated to operate across the
temperature range of -40°C to +125°C.
Related Literature
For a full list of related documents, visit our website:
• ISL78233, ISL78234 device pages
100
90
3.3V
OUT
1.5V
80
OUT
1.2V
OUT
1.8V
OUT
70
60
50
40
2.5V
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD (2MHz 5V PFM, T = +25°C)
IN
A
FN8359 Rev.9.00
Feb 21, 2019
Page 1 of 21
ISL78233, ISL78234
Typical Application Diagram
L
1
+1.8V/4A
V
OUT
1.0μH
2x22μF
C
2
GND
+2.7V …+5.5V
1
2
PGND
PGND
SGND
FB
V
IN
VIN
ISL78233, ISL78234
R
2
C
1
C *
3
200kꢀꢁ
2x22μF
22pF
GND
R
1
ꢀꢁ
VDD
PG
100k
R
3
3
4
PG
100k
ꢀꢁ
SYNC
*C IS OPTIONAL. IT IS
3
RECOMMENDED TO PUT A
PLACEHOLDER FOR IT AND CHECK
LOOP ANALYSIS BEFORE USE.
FIGURE 2. TYPICAL APPLICATION DIAGRAM
TABLE 1. COMPONENT SELECTION TABLE
V
1.2V
2 x 22µF
2 x 22µF
22pF
1.5V
2 x 22µF
2 x 22µF
22pF
1.8V
2 x 22µF
2 x 22µF
22pF
2.5V
3.3V
2 x 22µF
2 x 22µF
22pF
3.6V
OUT
C
C
C
2 x 22µF
2 x 22µF
22pF
2 x 22µF
2 x 22µF
22pF
1
2
3
1
L
0.33-0.68µH
100kΩ
0.33-0.68µH
150kΩ
0.33-0.68µH
200kΩ
0.47-0.78µH
316kΩ
0.47-0.78µH
450kΩ
0.47-0.78µH
500kΩ
R
2
3
R
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
FN8359 Rev.9.00
Feb 21, 2019
Page 2 of 21
ISL78233, ISL78234
COMP
55pF
FS
SYNC
SS
SOFT-
START
SHUTDOWN
SHUTDOWN
VDD
VIN
100kΩ
+
+
EN
OSCILLATOR
VREF
3pF
BANDGAP
EAMP
+
COMP
-
P
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
PHASE
PGND
LS
DRIVER
N
+
FB
SLOPE
COMP
0.8V
6kΩ
+
-
CSA
-
+
-
OV
+
OCP
-
0.85*VREF
ISET
THRESHOLD
+
UV
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
-
SCP
+
0.5V
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
Ordering Information
PART NUMBER
PART
OUTPUT VOLTAGE TEMP. RANGE TAPE AND REEL
PACKAGE
PKG.
(Note 4)
MARKING
(V)
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
(°C)
(UNITS) (Note 1)
(RoHS Compliant)
DWG. #
ISL78233ARZ (Note 2)
8233
8233
8233
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-
6k
250
-
16 Ld 3x3 TQFN
L16.3x3D
L16.3x3D
L16.3x3D
L16.5x5D
L16.5x5D
L16.5x5D
L16.3x3D
L16.3x3D
L16.3x3D
L16.5x5D
ISL78233ARZ-T (Note 2)
ISL78233ARZ-T7A (Note 2)
ISL78233AARZ (Note 3)
ISL78233AARZ-T (Note 3)
ISL78233AARZ-T7A (Note 3)
ISL78234ARZ (Note 2)
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
78233A ARZ
78233A ARZ
78233A ARZ
8234
16 Ld 5x5mm WFQFN
16 Ld 5x5mm WFQFN
16 Ld 5x5mm WFQFN
16 Ld 3x3 TQFN
6k
250
-
ISL78234ARZ-T (Note 2)
ISL78234ARZ-T7A (Note 2)
ISL78234AARZ (Note 3)
8234
6k
250
-
16 Ld 3x3 TQFN
8234
16 Ld 3x3 TQFN
78234A ARZ
16 Ld 5x5mm WFQFN
FN8359 Rev.9.00
Feb 21, 2019
Page 3 of 21
ISL78233, ISL78234
Ordering Information
PART NUMBER
PART
OUTPUT VOLTAGE TEMP. RANGE TAPE AND REEL
PACKAGE
PKG.
(Note 4)
MARKING
(V)
Adjustable
Adjustable
(°C)
(UNITS) (Note 1)
(RoHS Compliant)
DWG. #
ISL78234AARZ-T (Note 3)
ISL78234AARZ-T7A (Note 3)
ISL78233EVAL1Z
ISL78234EVAL1Z
ISL78233EVAL2Z
ISL78234EVAL2Z
NOTES:
78234A ARZ
78234A ARZ
-40 to +125
-40 to +125
6k
16 Ld 5x5mm WFQFN
16 Ld 5x5mm WFQFN
L16.5x5D
L16.5x5D
250
3x3mm TQFN Evaluation Board
3x3mm TQFN Evaluation Board
5x5mm WFQFN Evaluation Board
5x5mm WFQFN Evaluation Board
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see the ISL78233, ISL78234 device information pages. For more information about MSL, see TB363.
TABLE 2. KEY DIFFERENCE BETWEEN FAMILY OF PARTS
I
MAX
OUT
(A)
PART NUMBER
ISL78233
3
4
5
ISL78234
ISL78235
Pin Configuration
16 LD TQFN
TOP VIEW
16
15
14
13
VIN
PGND
PGND
1
2
3
4
12
11
10
9
VDD
PG
SGND
FB
SYNC
7
8
6
5
FN8359 Rev.9.00
Feb 21, 2019
Page 4 of 21
ISL78233, ISL78234
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 16
VIN
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
2
3
VDD
PG
Input supply voltage for logic. Connect to the VIN pin.
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
4
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNC pin float.
5
6
EN
FS
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 2MHz
if FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
8
9
COMP
FB
The feedback network of the regulator, FB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if COMP is not tied to VDD. Otherwise, COMP is
disconnected through a MOSFET for internal compensation. Must connect COMP to VDD in internal
compensation mode. The output voltage is set by an external resistor divider connected to FB. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. Additional external networks across COMP and SGND might be required to improve the
loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
10
SGND
PGND
PHASE
Signal ground
Power ground
11, 12
13, 14, 15
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See “Functional Block Diagram” on page 3 for more detail.
Exposed Pad
-
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
many vias as possible under the pad connecting to the SGND plane for optimal thermal performance.
FN8359 Rev.9.00
Feb 21, 2019
Page 5 of 21
ISL78233, ISL78234
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE
Thermal Resistance
16 Ld TQFN Package (Notes 5, 6) . . . . . . .
16 Ld WFQFN Package (Notes 5, 6) . . . . .
(°C/W)
43
33
(°C/W)
3.5
3.5
JA
JC
DC: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Pulsed (Note 8): . . . . . . . . . . . . . . . . . . . . . . . . -2V (< 0.6µJ) to 7V (20ms)
COMP, SS (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Operating Junction Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per AEC-Q100-003). . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per AEC-Q100-004, Class II, Level A) . . . . . . . . . . 100mA
Recommended Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
IN
Load Current Range
(ISL78233) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
(ISL78234) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
JA
6. , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
7. COMP is an input and output pin. When the ISL7823x is used with an internal compensation, the COMP pin has a rating similar to VIN. When using
the ISL7823x in an external compensation, the ratings are -0.3V to 2.7V.
8. The PHASE pin negative voltage can be less than -2V as long as the energy of the pulse does not exceed 0.6µJ.
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions
and the specification limits are measured at the following conditions: T = -40°C to +125°C, V = 3.6V, EN = V , unless otherwise noted. Typical values
A
IN
IN
are at T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C.
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNIT
INPUT SUPPLY
Undervoltage Lockout Threshold
V
V
Rising, no load
2.5
2.45
45
2.7
V
V
IN
UVLO
Falling, no load
2.2
Quiescent Supply Current
I
SYNC = GND, no load at the output
µA
µA
VIN
SYNC = GND, no load at the output and no
switches switching
45
60
SYNC = V , FS = 2MHz, no load at the output
IN
19
25
10
mA
µA
Shutdown Supply Current
OUTPUT REGULATION
Reference Voltage
I
SYNC = GND, V = 5.5V, EN = low
IN
3.8
SD
V
0.593
1.7
0.600
0.1
0.2
1
0.606
V
REF
VFB Bias Current
I
VFB = 0.75V
µA
VFB
Line Regulation
V
= V + 0.5V to 5.5V (minimal 2.7V)
%/V
ms
µA
IN
SS = SGND
= 0.1V
O
Soft-Start Ramp Time Cycle
Soft-Start Charging Current
OVERCURRENT PROTECTION
Current Limit Blanking Time
I
V
2.1
2.5
SS
SS
t
17
Clock
OCON
pulses
Overcurrent and Auto Restart Period
Positive Peak Current Limit
t
8
SS cycle
OCOFF
I
ISL78234, T = +25°C
5.4
5.2
3.9
3.7
6.7
8.1
9
A
A
A
A
PLIMIT
A
ISL78234, T = -40°C to +125°C
A
ISL78233, T = +25°C
4.9
6
A
ISL78233, T = -40°C to +125°C
6.6
A
FN8359 Rev.9.00
Feb 21, 2019
Page 6 of 21
ISL78233, ISL78234
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions
and the specification limits are measured at the following conditions: T = -40°C to +125°C, V = 3.6V, EN = V , unless otherwise noted. Typical values
A
IN
IN
are at T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
ISL78234, T = +25°C
(Note 9)
TYP
1.1
(Note 9)
UNIT
A
Peak Skip Limit
I
0.9
1.35
1.5
SKIP
A
ISL78234, T = -40°C to +125°C
0.84
0.7
A
A
ISL78233, T = +25°C
0.9
1.2
A
A
ISL78233, T = -40°C to +125°C
0.6
1.3
A
A
Zero Cross Threshold
Negative Current Limit
-275
-5.1
375
-1.3
-0.6
mA
A
I
T
= +25°C
-2.8
NLIMIT
A
T
= -40°C to +125°C
-6.0
A
A
COMPENSATION
Error Amplifier Transconductance
COMP = V , internal compensation
DD
125
130
0.2
µA/V
µA/V
Ω
External compensation
4A application
Transresistance
RT
0.145
0.25
PHASE
P-Channel MOSFET ON-Resistance
V
V
V
V
= 5V, I = 200mA
26
38
5
35
52
50
78
20
31
mΩ
mΩ
mΩ
mΩ
%
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 5V, I = 200mA
11
O
= 2.7V, I = 200mA
8
15
O
PHASE Maximum Duty Cycle
PHASE Minimum On-Time
OSCILLATOR
100
SYNC = High
100
ns
Nominal Switching Frequency
f
FS = V
1700
0.67
2000
420
2350
kHz
kHz
kHz
V
SW
IN
FS with RS = 402kΩ
FS with RS = 42.2kΩ
4200
0.75
0.17
3.7
SYNC Logic LOW to HIGH Transition Range
SYNC Hysteresis
0.84
5
V
SYNC Logic Input Leakage Current
PG
V
= 3.6V
µA
IN
Output Low Voltage
IPG = 1mA
0.3
2
V
ms
µA
V
Delay Time (Rising Edge)
PG Pin Leakage Current
OVP PG Rising Threshold
UVP PG Rising Threshold
UVP PG Hysteresis
Time from V
reached regulation
0.5
80
1
OUT
PG = V
0.01
0.80
86
0.1
IN
90
%
5.5
6.5
%
PGOOD Delay Time (Falling Edge)
EN
µs
Logic Input Low (Note 10)
Logic Input High
EN_VIL
EN_VIH
0.4
1
V
0.9
V
EN Logic Input Leakage Current
Thermal Shutdown
Pulled up to 3.6V
0.1
150
25
µA
°C
°C
Temperature Rising
Temperature Falling
Thermal Shutdown Hysteresis
NOTE:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. EN should be held below the EN_VIL until V exceeds V
IN
rising.
UVLO
FN8359 Rev.9.00
Feb 21, 2019
Page 7 of 21
ISL78233, ISL78234
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
IN
A
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A.
IN
1
2
OUT
100
90
80
70
60
50
40
100
90
80
70
60
50
40
2.5V
2.5V
OUT
OUT
1.5V
1.5V
OUT
OUT
1.2V
OUT
1.2V
OUT
1.8V
OUT
1.8V
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (2MHz, 3.3V PWM)
IN
FIGURE 5. EFFICIENCY vs LOAD (2MHz, 3.3V PFM)
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
2.5V
OUT
3.3V
3.3V
OUT
OUT
2.5V
OUT
1.5V
1.5V
OUT
OUT
1.2V
OUT
1.8V
1.2V
OUT
1.8V
OUT
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD (2MHz, 5V PWM)
IN
FIGURE 7. EFFICIENCY vs LOAD (2MHz, 5V PFM)
IN
1.219
1.214
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
1.475
1.209
1.204
1.199
3.3V PFM
IN
3.3V PFM
IN
5V PFM
IN
5V PFM
IN
5V PWM
IN
5V PWM
IN
1.194
1.189
3.3V PWM
IN
3.3V PWM
IN
1.184
1.179
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 8. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 1.2V)
FIGURE 9. V
OUT
REGULATION vs LOAD (1MHz, V
= 1.5V)
OUT
FN8359 Rev.9.00
Feb 21, 2019
Page 8 of 21
ISL78233, ISL78234
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
IN
A
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
1.815
1.810
1.805
1.800
1.795
1.790
2.505
2.500
2.495
2.490
2.485
2.480
2.475
2.470
2.465
3.3V PFM
IN
3.3V PFM
IN
5V PFM
IN
5V PFM
IN
5V PWM
IN
5V PWM
IN
1.785
1.780
1.775
3.3V PWM
IN
3.3V PWM
IN
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. V
REGULATION vs LOAD (1MHz, V
= 2.5V)
OUT
FIGURE 10. V
OUT
REGULATION vs LOAD (1MHz, V
= 1.8V)
OUT
OUT
3.309
75
70
65
60
3.301
3.293
3.285
3.277
3.269
3.261
3.253
3.245
T = +125°C
5V PWM
IN
5V PFM
IN
T = +25°C
55
50
T = -40°C
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
OUTPUT LOAD (A)
IN
FIGURE 12. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 3.3V)
FIGURE 13. PHASE MINIMUM ON-TIME vs V (2MHz)
IN
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
V
OUT
1V/DIV
OUT
V
5V/DIV
EN
V
5V/DIV
EN
PG 5V/DIV
PG 5V/DIV
400µs/DIV
400µs/DIV
FIGURE 14. START-UP AT NO LOAD (PFM)
FIGURE 15. START-UP AT NO LOAD (PWM)
FN8359 Rev.9.00
Feb 21, 2019
Page 9 of 21
ISL78233, ISL78234
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
IN
A
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I = 0A to 4A. (Continued)
OUT
IN
1
2
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
V
5V/DIV
V
5V/DIV
EN
EN
PG 5V/DIV
PG 5V/DIV
400µs/DIV
400µs/DIV
FIGURE 16. SHUTDOWN AT NO LOAD (PFM)
FIGURE 17. SHUTDOWN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
V
1V/DIV
5V/DIV
OUT
OUT
V
5V/DIV
EN
V
EN
PG 5V/DIV
500µs/DIV
PG 5V/DIV
500µs/DIV
FIGURE 18. START-UP AT 4A LOAD (PWM)
FIGURE 19. SHUTDOWN AT 4A LOAD (PWM)
I
2A/DIV
1V/DIV
OUT
I
2A/DIV
1V/DIV
OUT
V
V
OUT
OUT
V
5V/DIV
V
5V/DIV
EN
EN
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 20. START-UP AT 4A LOAD (PFM)
FIGURE 21. SHUTDOWN AT 4A LOAD (PFM)
FN8359 Rev.9.00
Feb 21, 2019
Page 10 of 21
ISL78233, ISL78234
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
IN
A
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 22. JITTER AT NO LOAD PWM (1MHz)
FIGURE 23. JITTER AT FULL LOAD PWM (1MHz)
PHASE 5V/DIV
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
OUT
V
RIPPLE 20mV/DIV
OUT
I
1A/DIV
I
1A/DIV
L
L
20ms/DIV
500ns/DIV
FIGURE 24. STEADY STATE AT NO LOAD PWM
FIGURE 25. STEADY STATE AT NO LOAD PFM
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
OUT
I
2A/DIV
L
500ns/DIV
FIGURE 26. STEADY STATE AT 4A PWM
FN8359 Rev.9.00
Feb 21, 2019
Page 11 of 21
ISL78233, ISL78234
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
IN
A
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I = 0A to 4A. (Continued)
OUT
IN
1
2
V
RIPPLE 100mV/DIV
V
RIPPLE 100mV/DIV
OUT
OUT
I
2A/DIV
LOAD
I
2A/DIV
LOAD
200µs/DIV
200µs/DIV
FIGURE 28. LOAD TRANSIENTS (PFM)
FIGURE 27. LOAD TRANSIENTS (PWM)
PHASE 5V/DIV
V
1V/DIV
OUT
I
2A/DIV
L
I
5A/DIV
L
V
1V/DIV
OUT
PG 5V/DIV
PG 5V/DIV
4µs/DIV
40µs/DIV
FIGURE 29. OUTPUT SHORT-CIRCUIT
FIGURE 30. OVERCURRENT PROTECTION
PHASE 5V/DIV
V
1V/DIV
OUT
V
2V/DIV
OUT
I
5A/DIV
L
PG 2V/DIV
PG 5V/DIV
20µs/DIV
20ms/DIV
FIGURE 31. OVERVOLTAGE PROTECTION
FIGURE 32. OVER-TEMPERATURE PROTECTION
FN8359 Rev.9.00
Feb 21, 2019
Page 12 of 21
ISL78233, ISL78234
Theory of Operation
V
EAMP
The ISL78233 and ISL78234 are step-down switching regulators
optimized for automotive battery powered applications. The
regulator operates at a 2MHz default switching frequency for
high efficiency and allow smaller form factor, when FS is
connected to VIN. By connecting a resistor from FS to SGND, the
operational frequency adjustable range is 500kHz to 4MHz. At
light load, the regulator reduces the switching frequency, unless
forced to the fixed frequency, to minimize the switching loss and
to maximize the battery life. The quiescent current when the
output is not loaded is typically only 45µA. The supply current is
typically only 3.8µA when the regulator is shut down.
V
CSA
DUTY
CYCLE
I
L
V
OUT
PWM Control Scheme
FIGURE 33. PWM OPERATION WAVEFORMS
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL78233 and ISL78234
employ the current-mode Pulse-Width Modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 3 shows the functional block diagram.
The current loop consists of the oscillator, the PWM comparator,
current-sensing circuit, and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts,
which changes proportionally with frequency. The gain for the
current-sensing circuit is typically 200mV/A. The control
reference for the current loops comes from the Error Amplifier's
(EAMP) output.
Skip Mode
Pulling the SYNC pin LO (<0.4V) forces the converter into PFM
mode. The ISL78233 and ISL78234 enter a Pulse-Skipping
mode at light load to minimize the switching loss by reducing the
switching frequency. Figure 34 on page 14 illustrates Skip mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 3 monitors the NFET current for zero crossing. When 16
consecutive cycles are detected, the regulator enters Skip mode.
During the sixteen detecting cycles, the current in the inductor is
allowed to become negative. The counter is reset to zero when
the current in any cycle does not cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
PFET and turn on the N-channel MOSFET. The NFET stays on until
the end of the PWM cycle. Figure 33 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the current-sense
amplifier’s CSA output.
When Skip mode is entered, the pulse modulation starts being
controlled by the Skip comparator shown in Figure 3 on page 3.
Each pulse cycle is still synchronized by the PWM clock. The PFET
is turned on at the clock's rising edge and turned off when the
output is higher than 1.2% of the nominal regulation or when its
current reaches the peak Skip current limit value. Then, the
inductor current is discharging to 0A and stays at zero (the
internal clock is disabled), and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the PFET is turned on again at the rising edge of the internal
clock as it repeats the previous operations.
The output voltage is regulated by controlling the V
EAMP
voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and is discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.5V.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.2% below the nominal voltage.
FN8359 Rev.9.00
Feb 21, 2019
Page 13 of 21
ISL78233, ISL78234
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
LOAD CURRENT
I
L
0
NOMINAL +1%
V
OUT
NOMINAL -1.5%
NOMINAL
FIGURE 34. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
Negative Current Protection
The frequency of operation is fixed at 2MHz when FS is tied to VIN.
Adjustable frequency ranges from 500kHz to 4MHz using a simple
resistor connecting FS to SGND according to Equation 1:
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 3. When the valley point of the inductor current
reaches -3A for four consecutive cycles, both PFET and NFET are
off. The 100Ω in parallel to the NFET activates discharging the
output into regulation. The control begins to switch when output is
within regulation. The regulator is in PFM for 20µs before
switching to PWM if necessary.
3
220 10
------------------------------
R
k =
– 14
(EQ. 1)
FS
f
kHz
OSC
The ISL78233 and ISL78234 have frequency synchronization
capability by simply connecting the SYNC pin to an external
square pulse waveform. The frequency synchronization feature
synchronizes the positive edge trigger and its switching
frequency up to 4MHz. The minimum external SYNC frequency is
half of the free running frequency (either the default frequency or
determined by the FS resistor).
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After a 1ms soft-start period delay, PG becomes
high impedance as long as the output voltage is within nominal
regulation voltage set by VFB. When VFB drops 15% below or raises
0.8V above the nominal regulation voltage, the ISL78233 and
ISL78234 pull PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 3.
The current sensing circuit has a gain of 200mV/A, from the P-FET
current to the CSA output. When the CSA output reaches the
threshold, the OCP comparator is tripled to turn off the PFET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
output voltages, connect an external pull-up resistor, R , between
1
PG and VIN. A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
If an overcurrent condition is detected, the upper MOSFET is
immediately turned off and does not turn on again until the next
switching cycle. When the initial overcurrent condition is
detected, the overcurrent fault counter is set to 1. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC fault counter is incremented. If there are 17 sequential OC
fault detections, the regulator is shut down under an overcurrent
fault condition. An overcurrent fault condition results in the
regulator attempting to restart in a Hiccup mode within the delay
of eight soft-start periods. At the end of the eighth soft-start wait
period, the fault counters are reset and soft-start is attempted
again. If the overcurrent condition goes away during the delay of
eight soft-start periods, the output resumes back into regulation
point after Hiccup mode expires.
Soft Start-Up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current and
the output voltage speed, so that the output voltage rises in a
controlled fashion. When VFB is less than 0.1V at the beginning
of the soft-start, the switching frequency is reduced to 200kHz so
that the output can start-up smoothly at light load condition.
During soft-start, the IC operates in Skip mode to support
prebiased output condition.
Tie SS to SGND for internal soft-start is approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 2.1µA current source
FN8359 Rev.9.00
Feb 21, 2019
Page 14 of 21
ISL78233, ISL78234
sets the soft-start interval of the converter, t as shown by
SS
Equation 2.
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL78233 and ISL78234
protect the typical peak current 4.9A/6.7A. The saturation
current needs to be over 7A for maximum output current
application.
C
F = 3.1 t s
SS
(EQ. 2)
SS
C
must be less than 33nF to insure proper soft-start reset after
SS
The ISL78233 and ISL78234 use an internal compensation
network and the output capacitor value is dependent on the
output voltage. The recommended ceramic capacitor is X5R or
X7R. The recommended X5R or X7R minimum output capacitor
values are shown in Table 1 on page 2.
fault condition.
Enable
The Enable (EN) input allows you to control the turning on or off
of the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft start-up
In Table 1, the minimum output capacitor value is given for the
different output voltages to make sure that the whole converter
system is stable. Additional output capacitance should be added
for better performance in applications where high load transient
or low output ripple is required. Renesas recommends checking
the system level performance along with the simulation model.
begins. EN should be held below the EN_VIL until V exceeds
IN
V
rising.
UVLO
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the V UVLO is
set, the outputs discharge to GND through an internal 100Ω
IN
Output Voltage Selection
switch.
The output voltage of the regulator can be programmed using an
external resistor divider that scales the output voltage relative to the
internal reference voltage, and feeds it back to the inverting input of
the error amplifier (see Figure 2 on page 2).
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the PFET is typically 35mΩ and the
ON-resistance for the NFET is typically 11mΩ.
The output voltage programming resistor, R , depends on the
2
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor, R ,
is typically between 10kΩ and 100kΩ, as shown in Equation 4.
3
100% Duty Cycle
The ISL78233 and ISL78234 feature 100% duty cycle operation
to maximize the battery life. When the battery voltage drops to a
level that the ISL78233 and ISL78234 can no longer maintain
the regulation at the output, the regulator completely turns on
the P-FET. The maximum dropout voltage under the 100% duty-
cycle operation is the product of the load current and the
ON-resistance of the PFET.
V
O
VFB
-----------
– 1
(EQ. 4)
R
= R
2
3
If the output voltage desired is 0.6V, then R is left unpopulated
and R is shorted. There is a leakage current from VIN to PHASE.
Renesas recommends preloading the output with 10µA
minimum. For better performance, add 15pF in parallel with R
3
2
2
(200kΩ). Check loop analysis before use in application.
Thermal Shutdown
Input Capacitor Selection
The main functions for the input capacitor are providing
decoupling of the parasitic inductance and a filtering function to
prevent the switching current flowing back to the battery rail. At
least two 22µF X5R or X7R ceramic capacitors are a good
starting point for the input capacitor selection.
The ISL78233 and ISL78234 have built-in thermal protection. When
the internal temperature reaches +150°C, the regulator is
completely shut down. As the temperature drops to +125°C, the
ISL78233 and ISL78234 resume operation by stepping through
the soft-start.
Applications Information
Output Inductor and Capacitor Selection
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL78233 and ISL78234 use
constant frequency peak current mode control architecture to
achieve a fast loop transient response. An accurate
current-sensing pilot device in parallel with the upper MOSFET is
used for peak current control signal and overcurrent protection.
The inductor is not considered as a state variable because its
peak current is constant, and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 35 on page 16
shows the small signal model of the synchronous buck regulator.
To consider steady state and transient operations, the ISL78233
and ISL78234 typically use a 1.0µH output inductor. The higher
or lower inductor value can be used to optimize the total
converter system performance. For example, for higher output
voltage 3.3V application, in order to decrease the inductor
current ripple and output voltage ripple, the output inductor value
can be increased. Renesas recommends setting the ripple
inductor current to approximately 30% of the maximum output
current for optimized performance. The inductor ripple current
can be expressed as shown in Equation 3:
V
O
---------
V
1 –
(EQ. 3)
O
V
IN
--------------------------------------
I =
L f
S
FN8359 Rev.9.00
Feb 21, 2019
Page 15 of 21
ISL78233, ISL78234
The compensator design procedure is as follows:
^
^
^
L
R
LP
i
P
i
L
v
in
o
The loop gain at crossover frequency of f has a unity gain.
c
^
d
Therefore, the compensator resistance R is determined by
V
6
in
^
^
1:D
I d
V
L
in
Equation 6.
Rc
Co
+
R
T
2f V C R
o o t
3
c
(EQ. 6)
---------------------------------
= 17.4510 f V C
c o o
Ro
R
=
6
GM V
FB
where GM is the sum of the transconductance, g , of the voltage
m
T (S)
i
^
d
error amplifier in each phase. Compensator capacitor C is then
6
K
given by Equation 7.
Fm
R C
V C
o o
I R
o 6
R C
o
o
1
c
o
(EQ. 7)
-------------- --------------
,C = max(--------------,---------------)
7
C
=
=
6
R
R
f R
6
6
s 6
T (S)
+
v
He(S)
^
Place one compensator pole at zero frequency to achieve high
DC gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. CZ2 is
v
comp
-Av(S)
FIGURE 35. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
a zero due to R and C
2
3
Place compensator zero 2 to 5 times f :
c
1
(EQ. 8)
---------------
C =
3
f R
c
2
Vo
Example: V = 5V, V = 1.8V, I = 4A, FS = 1MHz, R = 200kΩ,
IN
O
O
2
R = 100kΩ, C = 2x22µF/3mΩ, L = 1µH, f = 100kHz, then
3
o
c
R
C
3
2
compensator resistance R :
6
V
FB
3
(EQ. 9)
-
R
= 17.4510 100kHz 1.8V 44F = 138k
V
COMP
6
R
3
GM
V
REF
+
It is acceptable to use 137kΩas theclosest standard value for
R .
6
R
6
C
1.8V 44F
4A 137k
7
(EQ. 10)
(EQ. 11)
-------------------------------
= 144pF
C
6
=
C
6
3m 44F
1
C = max(--------------------------------,------------------------------------------------ )= (1pF,2.3pF)
7
137k
1MHz137k
It is also acceptable to use the closest standard values for C and
6
FIGURE 36. TYPE II COMPENSATOR
C . There is approximately 3pF parasitic capacitance from V
7
COMP
to GND; Therefore, C is optional. Use C = 150pF and C = OPEN.
7
6
7
Figure 36 shows the type II compensator and its transfer function
is expressed as Equation 5:
1
(EQ. 12)
-----------------------------------------------
C =
= 16pF
3
S
S
100kHz 200k
------------
------------
1 +
1 +
ˆ
GM R
v
comp
3
cz1
cz2
---------------- -------------------------------------------------------- --------------------------------------------------------------
A S=
=
v
ˆ
Use C = 15pF. Note that C may increase the loop bandwidth
3 3
C + C R + R
S
S
v
6
7
2
3
FB
------------
------------
S 1 +
1 +
from previous estimated value. Figure 37 on page 17 shows the
simulated voltage loop gain. It is shown that it has a 150kHz loop
bandwidth with a 42° phase margin and 10dB gain margin. It
may be more desirable to achieve an increased phase margin.
cp1
cp2
(EQ. 5)
where,
This can be accomplished by lowering R by 20% to 30%.
6
C
+ C
R + R
2 3
C R R
3 2 3
1
--------------
1
6
7
--------------
----------------------
----------------------
=
,
=
=
cp2
=
cz1
cz2
cp1
R C
R C
R C C
6
6
2
3
6
6
7
Compensator design goal:
• High DC gain
• Choose loop bandwidth f less than 100kHz
c
• Gain margin: >10dB
• Phase margin: >40°
FN8359 Rev.9.00
Feb 21, 2019
Page 16 of 21
ISL78233, ISL78234
60
45
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For the ISL78233 and
ISL78234, the power loop is composed of the output inductor L’s,
30
15
0
the output capacitor C , the PHASE pins, and the PGND pin. It is
O
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short, and wide.
The switching node of the converter, the PHASE pins and the
traces connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. Place the input
capacitor as close as possible to the VIN pin. Connect the ground
of the input and output capacitors as close as possible. The heat
of the IC is mainly dissipated through the thermal pad.
Maximizing the copper area connected to the thermal pad is
preferable. In addition, a solid ground plane is helpful for better
EMI performance. See TB389 for via placement on the copper
area of the PCB underneath the thermal pad for optimum
thermal performance.
-15
-30
100
1k
10k
100k
1M
f (fi)
180
150
120
90
60
30
0
100
1k
10k
100k
1M
f (fi)
FIGURE 37. SIMULATED LOOP GAIN
FN8359 Rev.9.00
Feb 21, 2019
Page 17 of 21
ISL78233, ISL78234
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
FN8359.9
CHANGE
Feb 21, 2019
Updated PHASE Absolute Maximum Ratings information.
Added Notes 7 and 8.
Updated links throughout document.
Updated disclaimer.
Apr 19, 2018
FN8359.8
Updated Related Literature section.
Updated Ordering Information table by adding tape and reel information, Note 3, and updating Note 1.
Adding Note 8 and its cross-referencing on page 7.
Added symbol name “EN_VIL” to the Logic Input Low parameter and the symbold name “EN_VIH” to the Logic
Input High parameter on page 7.
Updated Enable section on page 14.
Removed About Intersil section and updated disclaimer.
Dec 4, 2015
FN8359.7
FN8359.6
Added a new User Guide to Related Literature section on page 1.
Added EVAL2 part numbers to the ordering information table on page 3.
Added Table 2 on page 4.
Nov 10, 2015
Added 5x5mmWFQFN information throughout datasheet.
Updated Note 1 on page 4 from “Add “-T*” suffix for tape and reel.” to “Add “-T” suffix for 6k unit or “-T7A” suffix
for 250 unit tape and reel options.”
In “PWM Control Scheme” on page 13 (last sentence) corrected a typo by changing “1.6V to “2.5V”.
Table 1 on page 2: Updated L1 row.
Updated the “PCB Layout Recommendation” section on page 17.
Added POD L16.5x5D.
Apr 23, 2015
Apr 23, 2014
FN8359.5
FN8359.4
Updated the 4th Features bullet page 1 by changing value from “0.8%” to “-1.2%/1%”.
Updated electrical table, changed Phase minimum on-time MAX from 133ns to 100ns on page 7
Updated electrical table, modified test conditions for Error Amplifier trans-conductance and Power-good
Output Low Voltage on page 7
Removed references to VOUT = 0.8V, and 0.9V
Added typical curve for Phase minimum on-time vs VIN on page 9
Added description on synchronized control on page 14
Feb 24, 2014
FN8359.3
Updated ESD rating qual references from Jedec standard references to AEC-Q100 standard references on
page 6
Dec 13, 2013
Oct16, 2013
FN8359.2
FN8359.1
Last Features bullet on page 1: changed from “Qualified for automotive application” to “AEC-Q100 qualified”
Initial Release.
FN8359 Rev.9.00
Feb 21, 2019
Page 18 of 21
ISL78233, ISL78234
For the most recent package outline drawing, see L16.3x3D.
Package Outline Drawings
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
6
A
12X 0.50
PIN #1
INDEX AREA
B
13
16
6
PIN 1
INDEX AREA
12
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
16X 0.23±0.05
8
5
16X 0.40±0.10
BOTTOM VIEW
TOP VIEW
4
SEE DETAIL “X”
0.10 C
C
0.75 ±0.05
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) ( 1.60)
(16X 0.23)
5
0 . 2 REF
C
(16X 0.60)
0 . 02 NOM.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
JEDEC reference drawing: MO-220 WEED.
7.
FN8359 Rev.9.00
Feb 21, 2019
Page 19 of 21
ISL78233, ISL78234
For the most recent package outline drawing, see L16.5x5D.
L16.5x5D
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETTABLE FLANK)
Rev 2, 5/14
0.10 M C A B
PIN 1 ID
2.8
(2X)
0.10 C A
0.60 MAX. (4X)
0.60 MAX. (4X)
A
5.00
4.75
R0.20
16
16
(2X)
0.10 C B
0.45
0.10 M C B A
1
2
3
1
2
3
5
5.00
0.50 DIA
2.8
4.75
(0.70)
C C
(2X)
(2X)
0.10 C B
0.10 C A
0.40±0.10
0.15±0.10
B
TOP VIEW
TERMINAL TIP 4
(0.70)
0.30±0.05
0.10 M C A B
0.05 M C
0.80
BOTTOM VIEW
5
0.08 C
// 0.10 C
0.85 ± 0.05
+ 0.04
- 0.01
0.01
0.65 ± 0.05
(0.20)
0.20
0.10
(0.01)
SEE DETAIL “A”
4
4
SECTION “C-C”
SCALE: NONE
DETAIL “A” (DIMPLE DEPTH)
SCALE: NONE
12° MAX
SEATING PLANE
C
SIDE VIEW
NOTES:
1. Dimensions are in millimeters.
12X (0.80)
Dimensions in ( ) are for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
(2.80) SQ
(4.80) SQ
4. Dimension applies to the plated terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
16X (0.30)
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
16X (0.60)
TYPICAL RECOMMENDED LAND PATTERN
Reference document: JEDEC M0220.
6.
FN8359 Rev.9.00
Feb 21, 2019
Page 20 of 21
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