ISL78227ARZ-T_技术文档

DATASHEET

ISL78227

2-Phase Boost Controller with Integrated Drivers

FN8808

Rev.5.00

Jul 13, 2018

The ISL78227 is an automotive grade (AEC-Q100 Grade 1),

2-phase, 55V synchronous boost controller that simplifies the

design of high power boost applications. It integrates strong

half-bridge drivers, an analog/digital tracking input, and

comprehensive protection functions.

Features

• Input/output voltage range: 5V to 55V, withstands 60V

transients

• Supports synchronous or standard boost topology

The ISL78227 enables a simple, modular design for systems

requiring power and thermal scalability. It offers peak-current

mode control for fast line response and simple compensation.

Its synchronous 2-phase architecture enables it to support

higher current while reducing the size of input and output

capacitors. The integrated drivers feature programmable

adaptive dead time control offering flexibility in power stage

design. The ISL78227 offers a 90° output clock and supports

1-, 2-, and 4-phases.

• Peak current mode control with adjustable slope

compensation

• Secondary average current control loop

• Integrated 5V 2A sourcing/3A sinking N-channel MOSFET

drivers

• Switching frequency: 50kHz to 1.1MHz per phase

• External synchronization

• Programmable minimum duty cycle

• Programmable adaptive dead time control

• Optional diode emulation and phase dropping

• PWM and analog track function

The ISL78227 offers a highly robust solution for the most

demanding environments. Its unique soft-start control

prevents large negative current even in extreme cases, such as

a restart under high output pre-bias on high volume

capacitances. It also offers two levels of cycle-by-cycle

overcurrent protection, average current limiting, input OVP,

output UVP/OVP, and internal OTP. In the event of a fault, the

fault protection response can be selected to be latch-off or

hiccup recovery.

• Forced PWM operation with negative current limiting and

protection

• Comprehensive fault protections

• Selectable hiccup or latch-off fault response

• AEC-Q100 qualified, Grade 1: -40°C to +125°C

• 5mmx5mm 32 Ld Wettable Flank QFN (WFQFN) package

Also integrated are several functions that ease system design.

A unique tracking input controls the output voltage, allowing it

to track either a digital duty cycle (PWM) signal or an analog

reference. The ISL78227 provides input average current

limiting so the system can deliver transient bursts of high load

current while limiting the average current to avoid overheating.

Applications

• Automotive power systems (12V to 24V, 12V to 48V, etc.)

- Trunk audio amplifiers

Related Literature

For a full list of related documents, visit our website

• ISL78227 product page

- Start-stop systems

- Automotive boost applications

• Industrial and telecommunication power supplies

ISL78227

PVCC

VOUT

PVCC

PGND

BOOT1

100

95

UG1

PH1

R_SEN1

VIN

90

V_O= 18V

LG1

VIN

EN

85

ISEN1N

ISEN1P

80

EN_IC

V_O= 24V

75

V_O= 36V

POWER-

GOOD

PGOOD

70

65

60

55

50

BOOT2

UG2

PH2

TRACK

CLKOUT

SS

R_SEN2

CLOCK_OUT

LG2

ISEN2N

ISEN2P

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

COMP

LOAD CURRENT (A)

FB

NOTE: (See Typical Application in Figure 4 on page 8.)

FIGURE 2. EFFICIENCY CURVES, V = 12V, T = +25°C

FIGURE 1. SIMPLIFIED APPLICATION SCHEMATIC, 2-PHASE

SYNCHRONOUS BOOST

IN

A

FN8808 Rev.5.00

Jul 13, 2018

Page 1 of 44

ISL78227

Table of Contents

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Application - 2-Phase Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operation Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Operation Initialization and Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PGOOD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Adjustable Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Fault Protections/Indications and Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Internal 5.2V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Input Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Power MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Bootstrap Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

V

Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CC

Current Sense Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Configuration to Support Single Phase Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

FN8808 Rev.5.00

Jul 13, 2018

Page 2 of 44

ISL78227

Pin Configuration

32 LD 5x5 WFQFN

TOP VIEW

32 31 30 29 28 27 26 25

VCC

SLOPE

FB

UG1

PH1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

LG1

COMP

SS

PVCC

PGND

LG2

SGND

IMON

TRACK

PGOOD

PH2

UG2

9

10 11

12 13 14 15 16

Functional Pin Description

PIN NAME

PIN #

DESCRIPTION

VCC

1

IC bias power input pin for the internal analog circuitry. Use aminimum1µFceramic capacitorbetween VCCand groundfornoise

decoupling purposes. VCC is typically biased by PVCC or an external bias supply with voltage ranging from 4.75V to 5.5V.

Because PVCC provides pulsing drive current, a small resistor (10Ω or smaller) between PVCC and VCC can help filter out the

noises from PVCC to VCC.

SLOPE

FB

2

3

Programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Refer to

“Adjustable Slope Compensation” on page 32 for information about how to select this resistor value.

The inverting input of the error amplifier for the voltage regulation loop. A resistor network must be placed between the FB

pin and the output rail to set the boost converter’s output voltage. Refer to “Output Voltage Setting” on page 37 for more details.

Output overvoltage and undervoltage comparators also monitor this pin. Refer to “Output Overvoltage Fault Protection” and

“Output Undervoltage Indication” on page 34 for more details.

COMP

4

5

The output of the transconductance error amplifier (Gm1) for the output voltage regulation loop. Place the compensation

network between the COMP pin and ground. Refer to “Output Voltage Regulation Loop” on page 25 for more details.

The COMP pin voltage can also be controlled by the constant current control loop error amplifier (Gm2) output through a diode

(D ) when the constant current control loop is used to control the input average current. Refer to “Constant Current Control

CC

(CC)” on page 35 for more details.

SS

A capacitor placed from SS to ground sets up the soft-start ramp rate and in turn, determines the soft-start time. Refer to

“Soft-Start” on page 30 for more details.

FN8808 Rev.5.00

Jul 13, 2018

Page 3 of 44

ISL78227

Functional Pin Description(Continued)

PIN NAME

PIN #

DESCRIPTION

IMON

6

The average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting and average

current protection functions.

The sourcing current from the IMON pin is the sum of the two CSA outputs plus a fixed 17µA offset current. With each CSA sensing

individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and is the input current

for the boost. Place a resistor in parallel with a capacitor from IMON to ground. The IMON pin output current signal builds up the

average voltage signal representing the average current sense signals.

A constant average current-limiting function and an average current protection are implemented based on the IMON signal.

• Constant Current Control: A Constant Current (CC) control loop controls the IMON average current signal equal to a 1.6V

reference (VREF_CC), which ultimately limits the total input average current to a constant level.

• Average Current Protection: If the IMON pin voltage is higher than 2V, the part goes into either Hiccup or Latch-off fault

protection depending on the HIC/LATCH pin configuration.

Refer to “Average Current Sense for Two Phases - IMON” on page 31 for more details.

TRACK

PGOOD

7

8

External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either a digital or

analog signal selected by the ATRK/DTRK pin configuration. If the TRACK function is not used, connect the TRACK pin to VCC and

the internal VREF_1.6V works as the reference. Refer to “Digital/Analog Track Function” on page 25 for more details.

Provides an open-drain, power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output

voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD is

pulled HIGH. It is pulled low when output UV/OV or input OV conditions are detected. Refer to “PGOOD Signal” on page 30 for more

details.

FSYNC

9

Dual-function pin for switching frequency setting and synchronization is defined as follows:.

• The PWM switching frequency can be programmed by a resistor R

from this pin to ground. PWM frequency refers to

FSYNC

a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz to 1.1MHz.

• The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC pin

detects the input clock signal’s rising edge that it is to be synchronized with. The typical detectable minimum pulse width

of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input clock signal at the

FSYNC pin. When the internal clock is locked to the external clock, it latches to the external clock. If the external clock on

the FSYNC pin is removed, the switching frequency oscillator shuts down. The part then detects PLL_LOCK fault and goes

to either Hiccup mode or Latch-off mode, depending on the HIC/LATCHOFF pin configuration. If the part is set in Hiccup

mode, it restarts with frequency set by R

.

FSYNC

The typical synchronization frequency range is 50kHz to 1.1MHz. The phase dropping mode is not allowed with external

synchronization. Refer to “Oscillator and Synchronization” on page 27 for more details.

HIC/LATCH

10

Select either Hiccup or Latch-off response to faults including output overvoltage (monitoring the FB pin), output undervoltage

(monitoring the FB pin, default inactive), V overvoltage (monitoring the FB pin), peak overcurrent protection (OC2_PEAK),

IN

and average current protection (monitoring the IMON pin), etc.

Set HIC/LATCH = HIGH to activate the Hiccup fault response.

Set HIC/LATCH = LOW to activate the Latch-off fault response. Either toggling the EN pin or recycling VCC POR resets the IC

from Latch-off status. Refer to “Selectable Hiccup or Latch-Off Fault Response” on page 33 for more details.

DE/PHDRP

RBLANK

11

12

Selects Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode, or Continuous Conduction Mode (CCM). The three

configurable modes are: DE mode, DE plus PH_DROP mode, and CCM mode.

Refer to Table 2 on page 33 for the three configurable options. PD_DROP mode is not allowed with external synchronization.

A resistor from this pin to ground programs the blanking time for current sensing after the PWM is ON (LG is ON). This blanking

time is also called t

time, meaning the minimum ON-time when a PWM pulse is ON. Refer to “Minimum On-Time (Blank

MINON

Time) Consideration” on page 28 for the selection of R

.

BLANK

PLLCOMP

EN

13

14

Compensation node for the switching frequency clock’s PLL (Phase Lock Loop). A second order passive loop filter connected

between this pin and ground compensates the PLL. Refer to “Oscillator and Synchronization” on page 27 for more details.

Threshold-sensitive enable input for the controller. When the EN pin is driven above 1.21V (typical), the ISL78227 is enabled

and the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN pin below 0.95V disables

the IC and clears all fault states. Refer to “Enable” on page 30 for more details.

CLKOUT

15

Outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT pin is delayed

by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second ISL78227, a 4-phase

interleaving operation can be achieved. Refer to “Oscillator and Synchronization” on page 27 for more details.

FN8808 Rev.5.00

Jul 13, 2018

Page 4 of 44

ISL78227

Functional Pin Description(Continued)

PIN NAME

PIN #

DESCRIPTION

BOOT2

16

Provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external

N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor is recommended between the BOOT2 and PH2 pins.

In the typical configuration, PVCC provides the bias to BOOT2 through a fast switching diode.

In applications in which a high-side driver is not needed (for example, standard boost applications), BOOT2 is recommended

to be connected to ground. The ISL78227 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and

Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground.

UG2

PH2

17

18

Phase 2 high-side gate driver output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2 to

ground.

Represents the return path for the Phase 2 high-side gate drive. Connect this pin to the source of the Phase 2 high-side

MOSFETs and the drain of the low-side MOSFETs.

LG2

19

20

Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.

PGND

Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current, so traces connecting from

this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible. All

sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to the ground

copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias as close as

possible to the IC.

PVCC

21

Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx through

diodes), and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps to filter out

the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic capacitor should

be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 36 for more details.

LG1

PH1

22

23

Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.

Represents the return path for the Phase 1 high-side gate drive. Connect this pin to the source of the Phase 1 high-side

MOSFETs and the drain of the low-side MOSFETs.

UG1

24

25

Phase 1 high-side MOSFET gate drive output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2

to ground.

BOOT1

Provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external

N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between BOOT1 and PH1 pins. In

a typical configuration, PVCC provides the bias to BOOT1 through a fast switching diode.

In applications in which a high-side driver is not needed (for example, standard boost applications), BOOT1 is recommended

to be connected to ground. The ISL78227 IC can detect BOOT1 being grounded during start-up and both the Phase 1 and

Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground.

VIN

26

27

Connect the supply rail to this pin. Typically, connect the boost input voltage to this pin. The VIN pin can also be supplied by a

separate input source independent from the boost power stage input source. This pin is connected to the input of the internal linear

regulator, generating the power necessary to operate the chip. The DC voltage applied to VIN should not exceed 55V during normal

operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection stops it from switching to

protect itself. Refer to “Input Overvoltage Fault Protection” on page 34 for more details.

ISEN1N

The ISEN1N pin is the negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses the

Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used

for current mode control, peak current limiting, average current limiting, and diode emulation.

ISEN1P

ISEN2N

28

29

Positive potential input to the Phase 1 current sense amplifier.

Negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses the Phase 2 inductor

current through a power current sense resistor in series with the inductor. The sensed current signal is used for current mode

control, peak current limiting, average current limiting, and diode emulation.

ISEN2P

30

31

Positive phase input to the Phase 2 current sense amplifier.

ATRK/DTRK

Logic input pin to select the input signal format options for the TRACK pin. Pull this pin HIGH for the TRACK pin to accept

analog input signals. Pull this pin LOW for the TRACK pin to accept digital input signals. Refer to “Digital/Analog Track

Function” on page 25 for more details.

RDT

32

-

A resistor connected from this pin to ground programs the dead times between UGx OFF to LGx ON and LGx OFF to UGx ON

to prevent shoot-through. Refer to “Driver Configuration” on page 24 for the selection of RDT.

SGND

Signal ground bottom pad to which to refer the internal sensitive analog circuits. Also serves as thermal pad. Connect this

pad to a large ground plane. Put as many vias as possible in this pad connecting to the ground copper plane to help reduce the

IC’s  . In layout power flow planning, avoid noisy, high frequency pulse current flow through the SGND area.

JA

FN8808 Rev.5.00

Jul 13, 2018

Page 5 of 44

ISL78227

Ordering Information

PART NUMBER

(Notes 2, 3)

TAPE AND REEL

(Units) (Note 1)

PACKAGE

(RoHS COMPLIANT)

PKG.

DWG. #

PART MARKING

ISL78227ARZ

TEMP. RANGE (°C)

-40 to +125

ISL78227ARZ

-

32 Ld 5x5 WFQFN

L32.5x5H

ISL78227ARZ-T

ISL78227ARZ-T7A

ISL78227EV1Z

NOTES:

ISL78227ARZ

Evaluation Board

-40 to +125

6k

32 Ld 5x5 WFQFN

L32.5x5H

-40 to +125

250

1. Refer to TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), refer to the ISL78227 product information page. For more information about MSL, refer to TB363.

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PART

NUMBER

TOPOLOGY

PMBus™

NTC

Yes

No

TRACK FUNCTION

PACKAGE

40 Ld 6x6 WFQFN

32 Ld 5x5 WFQFN

ISL78229

2-Phase Boost Controller

Yes

ISL78227

No

FN8808 Rev.5.00

Jul 13, 2018

Page 6 of 44

ISL78227

Typical Application - 2-Phase Synchronous Boost

R_VCC

10

PVCC

VCC

PVCC

PGND

C_VCC

1µF

C_PVCC

10µF

R_PVCCBT

5.1

SGND

PVCC_BT

D_BOOT1

VOUT

VIN

EN

BOOT1

C_BOOT1

0.47µF

C_OUT

L1

EN_IC

Q1

UG1

PH1

R_SEN1

POWER-GOOD

PGOOD

VIN



1m

VCC

C_IN

R_PG

Q2

LG1

TRACK

R_BIAS1B

R_BIAS1A

ISEN1N

ISEN1P

CLOCK_OUT

CLKOUT

SS

C

220pF

ISEN1

C_SS

R_SET1B

D_BOOT2

R_SET1A

ISL78227

C_PLL1

6.8nF

PVCC_BT

BOOT2

R_PLL

C_OUT

C_BOOT2

0.47µF

PLLCOMP

3.3k

Q3

UG2

PH2

L2

R_SEN2

C_PLL2

1nF

1m

R_FS



C

IN

FSYNC

SLOPE

Q4

LG2

R_SLOPE

R_BIAS2B

R_BIAS2A

ISEN2N

ISEN2P

R_BLANK

C

220pF

ISEN2

RBLANK

RDT

R_SET2B

C_IMON

R_IMON

R_CP

R_SET2A

IMON

R_DT

ATRK/DTRK

HIC/LATCH

DE/PHDRP

R_FB2

FB

VCC

C_CP1

R_FB1

COMP

C_CP2

ATRK/DTRK:

= VCC to track analog signal

Q1, Q2, Q3, Q4: 2 BUK9Y6R0-60E in parallel

= GND to track digital signal

HIC/LATCH:

= VCC for HICCUP mode

= GND for LATCHOFF mode

DE/PHDRP:

= VCC for DE mode

= FLOAT for DE and Phase-Drop mode

= GND for CCM mode

FIGURE 4. TYPICAL APPLICATION 2-PHASE SYNCHRONOUS BOOST

FN8808 Rev.5.00

Jul 13, 2018

Page 8 of 44

ISL78227

Absolute Maximum Ratings

Thermal Information

VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V

PH1, PH2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10V(<20ns Pulse Width, 25µJ)

BOOT1, BOOT2, UG1, UG2. . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +65V

Thermal Resistance

32 Ld 5x5 WFQFN Package (Notes 4, 5). .

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to TB493

_JA(°C/W) _JC(°C/W)

30 1.2

Upper Driver Supply Voltage, V . . . . . . . . . . . . - 0.3V to +6.5V

- V

BOOTx PHx

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.9V (<10ns)

PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +6.5V

ISEN1P, ISEN1N, ISEN2P, ISEN2N . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V

Recommended Operating Conditions

V

- V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.6V

VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to +55V

PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.5V

PH1, PH2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +55V

ISENxP ISENxN

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VCC + 0.3V

ESD Rating

Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 2kV

Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . 750V

Latch-Up Rating (Tested per AEC-Q100-004) . . . . . . . . . . . . . . . . . . 100mA

Upper Driver Supply Voltage, V . . . . . . . . . . . . . . . . 3.5V to 6V

- V

BOOTx PHx

ISEN1P to ISEN1N and ISEN2P to ISEN2N Differential Voltage . . . . ±0.3V

ISEN1P, ISEN1N, ISEN2P, ISEN2N Common-Mode Voltage . . . . 4V to 55V

Operational Junction Temperature Range (Automotive). . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.

JA

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C.

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNIT

SUPPLY INPUT

Input Voltage Range

V

Switching, under the condition of internal

5

55

10.0

8.5

V

IN

LDO having dropout (V - PVCC) less than

IN

0.25V

Input Supply Current to the VIN Pin

(IC Enabled)

I

EN = 5V, V = 12V, PVCC = VCC, BOOT1 and

IN

8.0

6.0

mA

Q_SW

BOOT2 supplied by PVCC, R

= 40.2k

FSYNC

(f

= 300kHz), LGx = OPEN, UGx = OPEN

SW

I

EN = 5V, V = 12V, PVCC = VCC, BOOT1 and

IN

Q_NON-SW

BOOT2 supplied by PVCC, non-switching,

LGx = OPEN, UGx = OPEN

Input Supply Current to the VIN Pin

(IC Shutdown)

I

EN = GND, V = 55V

IN

0.2

0

1.0

1

µA

_SD_VIN_55V

Input Bias Current (IC Shutdown) to Each of

ISEN1P/ISEN1N/ISEN2P/ISEN2N Pins

I

EN = GND, V = 55V

IN

ISEN1P (or

-1

_SD_ISENxP/N

ISEN1N/ISEN2P/ISEN2N) = 55V

INPUT OVERVOLTAGE PROTECTION

V

OVP Rising Threshold (Switching Disable)

OVP Trip Delay

EN = 5V, V rising

IN

56.5

5.0

58.0

5

59.5

5.4

V

IN

EN = 5V, V rising

IN

µs

INTERNAL LINEAR REGULATOR

LDO Voltage (PVCC Pin)

V

= 6V to 55V, C = 4.7µF,

PVCC

5.2

V

PVCC

IN

I

= 10mA

PVCC

LDO Saturation Dropout Voltage (PVCC Pin)

LDO Current Limit (PVCC Pin)

V

= 4.9V, C

= 4.7µF, I_PVCC = 80mA

= 4.5V

0.3

195

100

V

DROPOUT

IN

PVCC

I

= 6V, V

130

50

250

160

mA

OC_LDO

PVCC

LDO Output Short Current Limit (PVCC Pin)

I

= 0V

OCFB_LDO

FN8808 Rev.5.00

Jul 13, 2018

Page 9 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNIT

POWER-ON RESET (For both PVCC and VCC)

Rising V

VCC

POR Threshold

V

4.35

4.05

4.50

4.15

0.4

4.75

4.25

V

PORH_VCC

Falling V

VCC

V

PORL_VCC

V

POR Hysteresis

V

VCC

PORHYS_VCC

Rising V

POR Threshold

V

4.35

3.0

4.50

3.2

4.75

3.4

V

PVCC

PORH_PVCC

Falling V

V

PVCC

PORL_PVCC

V

POR Hysteresis

V

1.3

V

PVCC

PORHYS_PVCC

Soft-Start Delay

t

From POR rising to initiation of soft-start.

0.85

ms

SS_DLY

R

= 61.9k, f

= 200kHz, PLLCOMP

FSYNC

pin network of R

SW

= 3.24k,

PLL

= 6.8nF, and C

C

= 1nF

PLL1

PLL2

EN

Enable Threshold

V

EN Rising

EN Falling

Hysteresis

EN = 4V

1.13

0.85

1.21

0.95

250

6

1.33

1.10

V

ENH

V

ENL

V

mV

MΩ

EN_HYS

Input Impedance

2

PWM SWITCHING FREQUENCY

PWM Switching Frequency (Per Phase)

F

R

= 249kΩ (0.1%)

46.0

142

290

990

50.2

150

300

1100

50

54.5

156

kHz

V

OSC

FSYNC

= 82.5kΩ (0.1%)

= 40.2kΩ (0.1%)

= 10kΩ (0.1%)

310

1170

Minimum Adjustable Switching Frequency

Maximum Adjustable Switching Frequency

FSYNC Pin Voltage

1100

0.5

Minimum ON-Time (Blanking Time) on LGx

t

Minimum duty cycle, C = C = OPEN

UG LG

315

175

100

75

410

525

325

180

105

90.5

ns

MINON_1

MINON_2

MINON_3

MINON_4

R

= 80kΩ (0.1%)

BLANK

Minimum duty cycle, C = C = OPEN

260

140

90

ns

%

UG LG

= 50kΩ (0.1%)

R

BLANK

Minimum duty cycle, C = C = OPEN

UG LG

= 25kΩ (0.1%)

R

BLANK

Minimum duty cycle, C = C = OPEN

UG LG

R

= 10k

BLANK

= T_LG_ ON/t , V = 3.5V,

SW COMP

Maximum Duty Cycle

D

88.5

89.0

MAX

f

= 300kHz, RDT = 18.2kΩ, C = OPEN,

SW

UG

C

= OPEN

LG

SYNCHRONIZATION (FSYNC PIN)

Minimum Synchronization Frequency at

FSYNC Input

50

kHz

Maximum Synchronization Frequency at

FSYNC Input

1100

Input High Threshold

Input Low Threshold

V

3.5

V

IH

V

1.5

IL

FN8808 Rev.5.00

Jul 13, 2018

Page 10 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNIT

Input Minimum Pulse Width - Rise-to-Fall

Input Minimum Pulse Width - Fall-to-Rise

Delay Time from Input Pulse Rising to LG1

20

ns

20

C

= OPEN, RDT = 50kΩ

35

1

LG

Rising Edge Minus Dead Time t

DT1

Input Impedance

Input impedance before synchronization

mode

kΩ

Input impedance after synchronization

mode

200

MΩ

CLKOUT

I

= 500µA

= -500µA

= 100pF, t

V

- 0.5

V

- 0.1

V

H

L

CLKOUT

CC

0.1

0.4

V

CLKOUT

Output Pulse Width

C

is each phase’s

= OPEN,

1/12 * t

87

CLKOUT

SW

switching period

Phase Shift from LG1 Rising Edge to CLKOUT

Pulse Rising Edge

C

f

= OPEN, C

CLKOUT

°

LG1

= 300kHz, t

= 60ns (refer to

SW

DT1

Figure 56 on page 28 for the timing

diagram)

SOFT-START

Soft-Start Current

I

4.5

5.0

0

5.5

µA

V

SS

Minimum Soft-Start Pre-Bias Voltage

Maximum Soft-Start Pre-Bias Voltage

Soft-Start Pre-bias Voltage Accuracy

Soft-Start Clamp Voltage

1.6

0

V

= 500mV

-25

25

mV

V

FB

V

3.25

3.47

3.70

SSCLAMP

HICCUP RETRY DELAY (Refer to “Selectable Hiccup or Latch-Off Fault Response” on page 33 for details)

Hiccup Retry Delay

If Hiccup fault response selected

500

ms

REFERENCE VOLTAGE FOR OUTPUT VOLTAGE REGULATION

System Reference Accuracy

FB Pin Input Bias Current

ERROR AMPLIFIER FOR OUTPUT VOLTAGE REGULATION (Gm1)

Transconductance Gain

Measured at the FB pin

1.576

-0.05

1.600

0.01

1.620

0.05

V

= 1.6V, TRACK = Open

µA

FB

2

7.5

mA/V

MΩ

MHz

V/µs

µA

Output Impedance

Unity Gain Bandwidth

C

= 100pF from COMP pin to GND

3.3

±3

COMP

Slew Rate

Output Current Capability

Maximum Output Voltage

Minimum Output Voltage

PWM CORE

±300

3.7

0.1

3.5

V

0.3

V

SLOPE Pin Voltage

480

-20

500

0

520

20

mV

%

SLOPE Accuracy

R

= 20k (0.1%)

SLOPE

= 40.2k (0.1%)

3

20

%

SLOPE

FN8808 Rev.5.00

Jul 13, 2018

Page 11 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

Duty Cycle Matching

SYMBOL

TEST CONDITIONS

= 30mV, R = 665Ω (0.1%),

(Note 6)

TYP

3

(Note 6) UNIT

V

R

%

RSENx

SLOPE

SETx

= 150kHz,

= 27k, f

SW

= 2.52V, Measure

- T )/(T

V

COMP

(T

+ T ) *2

on_lg1

on_lg2 on_lg1 on_lg2

CURRENT SENSE AMPLIFIER

Minimum ISENxN and ISENxP

Common-Mode Voltage Range

Accuracy becomes worse when lower

than 4V

4

V

Maximum ISENxN and ISENxP

Common-Mode Voltage Range

55

Maximum Input Differential Voltage Range

V

-

±0.3

123

ISENxP

ISENxN

ISENxP/ISENxN Bias Current

I

Sourcing out of pin, EN = 5V,

100

-4.0

150

6.0

µA

SENxP/N_BIAS

V

= V

, V = 4V to 55V

ISENxN

ISENxP CM

ZCD DETECTION - CSA

Zero Crossing Detection (ZCD) Threshold

V

Measures voltage threshold before R

at

SEN

1.3

mV

ZCD_CSA

CSA inputs (equivalent to the voltage

across the current sense shunt resistor),

R

= 665Ω (0.1%)

SET

PHASE DROPPING

V

Phase-Drop Falling Threshold, to Drop

V

When V

falls below V

,

1.0

1.05

45

1.1

1.15

50

1.2

1.25

55

V

IMON

Phase 2

PHDRP_TH_F

PHADD_TH_R

PHDRP_HYS

IMON

drop off Phase 2

PHDRP_TH_F

V

Phase-Add Rising Threshold, to Add

When V rise above V

,

PHADD_TH_R

IMON

Phase 2

IMON

add back Phase 2

V

Phase-Drop Threshold Hysteresis

When V <V

- V

,

mV

IMON

IMON PHDRP_TH_F PHDrop_HYS

add back Phase 2

PEAK OVERCURRENT CYCLE-BY-CYCLE LIMITNG (OC1)

Peak Current Cycle-by-Cycle Limit Threshold

for Individual Phase

V

Cycle-by-cycle current limit threshold

40

53

65

mV

OC1

(I

= 80µA, compared with I

).

OC1_TH

SENx

Measures the voltage threshold before

at CSA Inputs (equivalent to the

R

SETx

voltage across the current sense shunt

resistor), R = 665Ω (0.1%)

SETx

= OPEN, from the time V

Peak Current Cycle-by-Cycle Limit Trip Delay

C

tripped to

OC1

50

ns

LG

LG falling

PEAK OVERCURRENT FAULT PROTECTION OC2_PEAK, (Refer to “Peak Overcurrent Fault (OC2_PEAK) Protection” on page 35 for details)

Peak Current Fault Protection Threshold for

Individual Phase

V

Peak current hiccup protection threshold

(I = 105µA, compared with I ).

55

70

85

mV

OC2

OC2_TH

Measures the voltage threshold before

at CSA Inputs (equivalent to the

SENx

R

SETx

voltage across the current sense shunt

resistor), R = 665Ω (0.1%)

SETx

OC2_PEAK Trip Blanking Time

3

cycles

FN8808 Rev.5.00

Jul 13, 2018

Page 12 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

-32

(Note 6) UNIT

NEGATIVE CURRENT CYCLE-BY-CYCLE LIMITNG (OC_NEG)

Negative Current Cycle-by-Cycle Limit

Threshold for Individual Phase

V

Negative Current Cycle-by-Cycle Limit

mV

OC_NEG

(I

= -48µA, compared with

OC_NEG_TH

I

).

SENx

Measures the voltage threshold before

at CSA Inputs (equivalent to the

R

SETx

voltage across the current sense shunt

resistor), R = 665Ω (0.1%)

SET

AVERAGE CONSTANT CURRENT CONTROL LOOP

IMON Current Accuracy

V

= 30mV, R

SETx

= 665Ω (0.1%), with

27.0

16

28.3

17

29.5

18

µA

V

RSENx

ISENxP/N pins biased at 4V or 55V

common-mode voltage

IMON Offset Current

V

= 0V, R

= 665Ω (0.1%), with

SET

RSENx

ISENxP/N pins biased at 4V or 55V

common-mode voltage

Constant Current Control Reference

Accuracy

VREF

Measure the IMON pin

1.575

1.600

1.625

CC

AVERAGE OVERCURRENT FAULT PROTECTION OC_AVG, (Refer to “Average Overcurrent Fault (OC_AVG) Protection” on page 36 for details)

OC_AVG Fault Threshold at the IMON Pin

OC_AVG Fault Trip Delay

GATE DRIVERS

1.9

2.0

1

2.1

V

µs

UG Source Resistance

UG Source Current

R

100mA source current, V

- V = 4.4V

BOOT PH

1.2

2

Ω

A

UG_SOURCE

I

V

- V = 2.5V, V

UG PH

- V = 4.4V

BOOT PH

UG_SOURCE

UG Sink Resistance

R

100mA sink current, V - V = 4.4V

0.6

2.0

1.2

2.0

0.55

3

Ω

UG_SINK

BOOT PH

UG Sink Current

I

V

- V = 2.5V, V

UG PH

- V = 4.4V

A

UG_SINK

BOOT PH

100mA source current, PVCC = 5.2V

- PGND = 2.5V, PVCC = 5.2V

LG Source Resistance

LG Source Current

R

Ω

LG_SOURCE

I

V

A

LG_SOURCE

LG

100mA sink current, PVCC = 5.2V

- PGND = 2.5V, PVCC = 5.2V

LG Sink Resistance

R

Ω

LG_SINK

LG Sink Current

I

V

A

LG_SINK

LG

UG to PH Internal Resistor

LG to PGND Internal Resistor

BOOT-PH UVLO Detection Threshold

50

kΩ

V

50

2.8

3.0

0.15

3.2

BOOT-PH UVLO Detection Threshold

Hysteresis

0.09

0.22

V

Dead Time Delay - UG Falling to LG Rising

Dead Time Delay - LG Falling to UG Rising

Dead Time Delay - UG Falling to LG rising

Dead Time Delay - LG Falling to UG Rising

Dead Time Delay - UG Falling to LG Rising

Dead Time Delay - LG Falling to UG Rising

Dead Time Delay - UG Falling to LG Rising

Dead Time Delay - LG Falling to UG Rising

t

C

= C = OPEN, R = 10k (0.1%)

LG DT

55

65

70

85

ns

DT1

DT2

DT1

DT2

DT1

DT2

DT1

DT2

UG

= C = OPEN, R = 10k (0.1%)

LG DT

80

95

= C = OPEN, R = 18.2kΩ (0.1%)

LG DT

85

100

110

210

230

265

290

115

125

240

260

295

320

= C = OPEN, R = 18.2kΩ (0.1%)

LG DT

95

= C = OPEN, R = 50kΩ (0.1%)

LG DT

185

205

235

260

= C = OPEN, R = 50kΩ (0.1%)

LG DT

= C = OPEN, R = 64.9kΩ (0.1%)

LG DT

= C = OPEN, R = 64.9kΩ (0.1%)

LG DT

FN8808 Rev.5.00

Jul 13, 2018

Page 13 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

(Note 6)

MAX

(Note 6) UNIT

PARAMETER

SYMBOL

TEST CONDITIONS

TYP

OUTPUT OVERVOLTAGE DETECTION/PROTECTION MONITOR THE FB PIN, (Refer to “Output Overvoltage Fault Protection” on page 34 for details)

FB Overvoltage Rising Trip Threshold

V

Percentage of VREF_1.6V

(Selectable Hiccup/Latch-off response)

118

120

122

%

FBOV_RISE

FB Overvoltage Falling Recovery Threshold

V

Percentage of VREF_1.6V

114

116

118

FBOV_FALL

(Selectable Hiccup/Latch-off response)

Overvoltage Threshold Hysteresis

FB Overvoltage Trip Delay

4

1

%

µs

OUTPUT UNDERVOLTAGE DETECTION (MONITOR THE FB PIN), (Refer to “Output Undervoltage Indication” on page 34 for details)

Undervoltage Falling Trip Threshold

Undervoltage Rising Recovery Threshold

Undervoltage Threshold Hysteresis

POWER-GOOD MONITOR (PGOOD PIN)

PGOOD Leakage Current

V

Percentage of VREF_1.6V

78

80

84.0

4

82

%

FBUVREF_FALL

FBUVREF_RISE

V

82.5

86.5

PGOOD HIGH, V

= 5V

= 0.5mA

1

µA

V

PGOOD

PGOOD Low Voltage

PGOOD LOW, I

PGOOD

0.06

0.5

0.40

PGOOD Rising Delay (DE Mode)

The PGOOD rising delay from

= V (3.47V) and

ms

V

SSPIN

SSPCLAMP

VREF_TRK ≥ 0.3V to PGOOD HIGH when DE

mode is selected (DE/PHDRP = VCC or

FLOAT)

PGOOD Rising Delay (CCM Mode)

PGOOD Falling Blanking Time

The PGOOD rising delay from

100

10

ms

µs

V

= V (3.47V) and

SSPIN

SSPCLAMP

VREF_TRK ≥ 0.3V to PGOOD HIGH when

CCM mode is selected (DE/PHDRP = GND)

HIC/LATCH, ATRK/DTRK PIN DIGITAL LOGIC INPUT

Input Leakage Current

EN <1V

-1

1

µA

V

Input Pull Down Current

EN >2V, pin voltage = 2.1V

0.7

1.0

2.0

0.8

Logic Input Low

Logic Input High

2.1

V

DE/PHDRP PIN DIGITAL LOGIC INPUT (HIGH/LOW/FLOAT)

Input Leakage Current

-1

1

µA

kΩ

V

Float Impedance - Pin to VCC

Float Impedance - Pin to GND

Output Voltage on DE/PHDRP Pin

Tri-State Input Voltage MAX

Tri-State Input Voltage MIN

Logic Input Low

Pin = GND

Pin = VCC

Pin = Float

100

2.1

200

2.6

300

2.7

3

V

1.8

V

Pin voltage falling

Pin voltage rising

0.7

V

Logic Input High

V

- 0.4

V

CC

TRACK PIN - DIGITAL INPUT LOGIC

Input Leakage Current

EN <1V, pin voltage = 5V, V = 0V

CC

-1

1

µA

Input Pull-Up Current

EN >2V, pin voltage = 0V, V = 5V

CC

0.8

1.1

1.5

FN8808 Rev.5.00

Jul 13, 2018

Page 14 of 44

ISL78227

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: V = 12V, V

= 5.2V and V = 5.2V, T = -40°C to +125°C (Note 7). Typical values are at T = +25°C. Boldface limits apply across

VCC A A

IN

PVCC

the operating temperature range, -40°C to +125°C. (Continued)

MIN

(Note 6)

MAX

(Note 6) UNIT

PARAMETER

Input Pull-Up Current Compliance Voltage

Logic Input Low

SYMBOL

TEST CONDITIONS

EN >2V, pin open

TYP

2.5

V

PIN voltage falling

0.8

V

Logic Input High

PIN voltage rising

2

Duty Cycle Conversion (FB Accuracy)

0% duty cycle input, measure at the FB pin

0

25% duty cycle input, frequency = 400kHz,

measure at the FB pin

0.600

1.218

1.45

0.625

0.650

1.288

1.53

50% duty cycle input, frequency = 400kHz,

measure at the FB pin

1.253

1.49

V

60% duty cycle input, measure at the FB

TRACK PIN - ANALOG INPUT

Input Leakage Current

V

= 1.6V, leakage current into this

-1.0

-0.6

-0.3

µA

TRACK

pin to ground

TRACK Input Reference Voltage Range

TRACK Input Reference Voltage Accuracy

0

1.6

4.0

V

%

V

Measure at the FB pin, V

= 1.5V

= 0.5V

-4.0

-6.0

0.29

-0.5

1.8

TRACK

6.0

TRACK SS_DONE Detection Threshold

OVER-TEMPERATURE PROTECTION

Over-Temperature Trip Point

Over-Temperature Recovery Threshold

NOTES:

0.30

0.31

160

145

°C

6. Compliance to datasheet limits are assured by one or more methods: production test, characterization, and/or design.

7. The IC is tested in conditions with minimum power dissipations in the IC, meaning T ≈ T .

A

J

FN8808 Rev.5.00

Jul 13, 2018

Page 15 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C.

A

OUT

V

1.0V/DIV WITH 36V OFFSET

OUT

100

95

90

85

80

75

70

65

60

55

50

I

5.0A/DIV

L1

DE WITH PHASE DROP

PH1 30.0V/DIV

SS 3.0V/DIV

DE WITHOUT PHASE DROP

CCM

0.01

0.10

1.00

10.00

100.00

NOTE: (See Typical Application in Figure 4 on page 8.)

LOAD CURRENT (A)

10ms/DIV

FIGURE 5. EFFICIENCY vs LOAD, 2-PHASE BOOST, 3 MODES

FIGURE 6. EN INTO PRE-BIASED OUTPUT, CCM MODE

(DE/PHDRP = GND), I = 0A

OPERATION, f

= 200kHz, V = 12V, V = 36V,

SW

IN OUT

OUT

T

= +25°C

A

V

20.0V/DIV

OUT

PVCC 2.0V/DIV

PGOOD 5.0V/DIV

PLLCOMP 500mV/DIV

SS 700mV/DIV

PH1 30.0V/DIV

SS 3.0V/DIV

PH1 30.0V/DIV

20ms/DIV

500µs/DIV

FIGURE 7. EN ON AND INITIALIZATION TO START-UP, I

= 0A

FIGURE 8. SOFT-START, CCM MODE (DE/PHDRP = GND), I

= 8A

OUT

V

20.0V/DIV

PLLCOMP 500mV/DIV

CLKOUT 5.0V/DIV

OUT

PGOOD 5.0V/DIV

PH1 30.0V/DIV

SS 2.0V/DIV

PVCC 2.0V/DIV

SS 3.0V/DIV

200µs/DIV

5ms/DIV

FIGURE 9. EN ON AND INITIALIZATION TO START-UP, I

= 0A

FIGURE 10. SOFT-START, DE+PHDROP MODE (DE/PHDRP = FLOAT),

= 8A

OUT

I

OUT

FN8808 Rev.5.00

Jul 13, 2018

Page 16 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

V

20.0V/DIV

OUT

PVCC 2.0V/DIV

PGOOD 5.0V/DIV

PH1 30.0V/DIV

PGOOD 3.0V/DIV

SS 2.0V/DIV

SS 3.0V/DIV

PH1 30.0V/DIV

5ms/DIV

20ms/DIV

FIGURE 11. SOFT-START, DE MODE (DE/PHDRP = VCC), I

= 8A

FIGURE 12. EN SHUTDOWN, PVCC/PGOOD/SS FALL, I

= 0A

OUT

I

4.0A/DIV

L1

PGOOD 5.0V/DIV

LG2 5.0V/DIV

LG1 5.0V/DIV

V

20.0V/DIV

OUT

PH1 40.0V/DIV

PH2 40.0V/DIV

V

30.0V/DIV

OUT

20µs/DIV

10µs/DIV

FIGURE 13. EN SHUTDOWN, I

= 8A

FIGURE 14. CCM MODE (DE/PHDRP = GND), PHASE 1 INDUCTOR

RIPPLE CURRENT, I = 0A

OUT

I

4.0A/DIV

L2

PGOOD 4.0V/DIV

V

20.0V/DIV

OUT

LG2 5.0V/DIV

LG1 5.0V/DIV

PH2 30.0V/DIV

PH1 30.0V/DIV

V

30.0V/DIV

OUT

10µs/DIV

5ms/DIV

FIGURE 15. EN SHUTDOWN, I

= 8A

FIGURE 16. CCM MODE (DE/PHDRP = GND), PHASE 2 INDUCTOR

RIPPLE CURRENT, I = 0A

OUT

FN8808 Rev.5.00

Jul 13, 2018

Page 17 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

V

10.0V/DIV

OUT

PGOOD 4.0V/DIV

V

1.0V/DIV WITH 36V OFFSET

PH2 20.0V/DIV

OUT

PH2 30.0V/DIV

PH1 30.0V/DIV

PH1 20.0V/DIV

2µs/DIV

5µs/DIV

FIGURE 18. DE MODE (DE/PHDRP = V ), DIODE EMULATION

CC

FIGURE 17. DE MODE (DE/PHDRP = V ), DIODE EMULATION

CC

OPERATION, I

= 29mA

OPERATION, PULSE SKIPPING, I

= 0A

OUT

V

10.0V/DIV

V

10.0V/DIV

OUT

PH2 30.0V/DIV

PH1 30.0V/DIV

PH2 30.0V/DIV

10µs/DIV

2µs/DIV

FIGURE 19. DE MODE (DE/PHDRP = V ), PH1 AND PH2 DIODE

CC

FIGURE 20. DE+PH_DROP MODE (DE/PHDRP = FLOAT), PH1 DIODE

EMULATION WITH PH2 DROPPED, I = 29mA

EMULATION OPERATION, PULSE SKIPPING, I

= 7mA

OUT

V

10.0V/DIV

OUT

IMON 300mV/DIV

I_LOAD 5.0A/DIV

PH1 30.0V/DIV

PH2 30.0V/DIV

PH1 30.0V/DIV

PH2 30.0V/DIV

10ms/DIV

10µs/DIV

FIGURE 22. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH2 ADDED

AND DROPPED, UNDER TRANSIENT STEP LOAD OF 1A

TO 8A

FIGURE 21. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH1 DIODE

EMULATION WITH PH2 DROPPED, I = 7mA

OUT

FN8808 Rev.5.00

Jul 13, 2018

Page 18 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

FB 300mV/DIV

V 6.8V/DIV

OUT

FB 300mV/DIV

V

6.8V/DIV

OUT

TRACK 300mV/DIV

PH1 20.0V/DIV

2ms/DIV

FIGURE 23. ANALOG TRACKING 100Hz SINUSOIDAL SIGNAL, CCM

MODE (DE/PHDRP = GND), ATRK/DTRAK = VCC,

FIGURE 24. ANALOG TRACKING 300Hz SINUSOIDAL SIGNAL AT THE

TRACK PIN, CCM MODE (DE/PHDRP = GND),

I

= 1A

ATRK/DTRAK = VCC, I

= 1A

OUT

TRACK 4.0V/DIV

IMON 500mV/DIV

I_IN 16A/DIV

V

7.0V/DIV

OUT

PH1 30.0V/DIV

PH2 40.0V/DIV

PH1 40.0V/DIV

V

30.0V/DIV

OUT

50µs/DIV

1µs/DIV

FIGURE 25. STEADY-STATE OPERATION OF INPUT CONSTANT

FIGURE 26. DIGITAL TRACKING (TRACKING SIGNAL,

FREQUENCY = 400kHz, D_TRACK = 0.5), V

CURRENT MODE, I CONTROLLED AT 43A CONSTANT,

= 28.3V

IN

OUT

V

= 19.5V

OUT

TRACK 4.0V/DIV

IMON 500mV/DIV

I_IN 16A/DIV

V

7.0V/DIV

OUT

PH1 30.0V/DIV

PH2 40.0V/DIV

PH1 40.0V/DIV

V

30.0V/DIV

OUT

1s/DIV

1µs/DIV

FIGURE 27. LOAD CURRENT KEEP INCREASING FROM NO LOAD TO

OVERLOAD (25A), V STARTS TO DROP WHEN INPUT

FIGURE 28. DIGITAL TRACKING (TRACKING SIGNAL,

FREQUENCY = 400kHz, D_TRACK = 0.3), V

OUT

= 17V

OUT

CONSTANT CURRENT MODE STARTS TO WORK, INPUT

CURRENT IS FINALLY CONTROLLED TO BE CONSTANT

FN8808 Rev.5.00

Jul 13, 2018

Page 19 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

TRACK 4.0V/DIV

V

2.0V/DIV WITH 36V OFFSET

OUT

V

1.0V/DIV WITH 28V OFFSET

OUT

I_LOAD 5.0A/DIV

PH1 30.0V/DIV

PH2 40.0V/DIV

PH1 40.0V/DIV

PH2 30.0V/DIV

10µs/DIV

10ms/DIV

FIGURE 29. DIGITAL TRACKING, (TRACKING SIGNAL,

FREQUENCY = 200kHz, D_TRACK = 0.5), V

FIGURE 30. DE MODE (DE/PHDRP = VCC), TRANSIENT RESPONSE,

= 0.03A TO 8A STEP LOAD

= 28.3V

I

OUT

V

1.0V/DIV WITH 36V OFFSET

OUT

V

1.0V/DIV WITH 36V OFFSET

OUT

I_LOAD 5.0A/DIV

PH1 30.0V/DIV

I_LOAD 5.0A/DIV

PH1 30.0V/DIV

PH2 30.0V/DIV

5ms/DIV

1ms/DIV

FIGURE 31. CCM MODE (DE/PHDRP = GND), TRANSIENT RESPONSE,

= 0A TO 8A STEP LOAD

FIGURE 32. DE+PH_DROP MODE (DE/PHDRP = FLOAT), TRANSIENT

I

RESPONSE, I

= 1A TO 8A STEP LOAD

OUT

0.5

0.4

0.3

0.2

0.1

0.0

10

9

8

7

6

5

4

3

2

1

0

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 33. SHUTDOWN CURRENT AT THE VIN PIN I_SD vs

TEMPERATURE, V = 55V

FIGURE 34. IC OPERATIONAL QUIESCENT CURRENT vs

TEMPERATURE, IC SWITCHING, NO LOAD ON LGX AND

UGX

IN

FN8808 Rev.5.00

Jul 13, 2018

Page 20 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

10

1.610

1.609

1.608

1.607

1.606

1.605

1.604

1.603

1.602

1.601

1.600

1.599

1.598

1.597

1.596

1.595

1.594

1.593

1.592

1.591

1.590

9

8

7

6

5

4

3

2

1

0

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 36. V

SYSTEM ACCURACY vs TEMPERATURE,

FIGURE 35. IC OPERATIONAL QUIESCENT CURRENT vs

TEMPERATURE, IC NOT SWITCHING

REF_CC

MEASURED AT THE IMON PIN, VREF_CC = 1.6V

1.610

1.609

1.608

1.607

1.606

1.605

1.604

1.603

1.602

1.601

1.600

1.599

1.598

1.597

1.596

1.595

1.594

1.593

1.592

1.591

1.590

29.0

28.5

28.0

V_IN= 4V

V_IN= 55V

27.5

27.0

26.5

26.0

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 37. IMON OUTPUT CURRENT ACCURACY

(CURRENT-SENSING SIGNAL OUTPUT) vs

TEMPERATURE, V = 30mV, R = 665Ω (0.1%)

FIGURE 38. VREF_1.6V SYSTEM ACCURACY vs TEMPERATURE,

MEASURED AT THE FB PIN

RSENx

SETx

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

220

210

200

190

180

170

IOC_LDO (mA)

160

150

140

130

120

110

100

90

80

IOCFB_LD O (mA)

70

60

50

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 39. INTERNAL LDO DROPOUT VOLTAGE vs TEMPERATURE,

80mA LOAD CURRENT ON LDO OUTPUT (PVCC)

FIGURE 40. INTERNAL LDO OVERCURRENT THRESHOLD AND ITS

FOLDBACK OVERCURRENT THRESHOLD vs

TEMPERATURE

FN8808 Rev.5.00

Jul 13, 2018

Page 21 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

OUT

A

4.6

4.5

4.4

4.3

4.2

60

59

58

57

56

55

VPORH_PVCC (V)

VPOR H_VCC (V)

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 41. V OV RISING THRESHOLD vs TEMPERATURE

IN

FIGURE 42. PVCC/VCC POR RISING THRESHOLD vs TEMPERATURE

4.5

4.4

60

55

50

45

40

35

30

VPORL_VCC (V)

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

VPORL_PVCC (V)

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 44. PVCC/VCC POR FALLING THRESHOLD vs TEMPERATURE

FIGURE 43. OC1 VOLTAGE THRESHOLD (ACROSS RSEN) vs

TEMPERATURE

1.5

1.3

1.1

0.9

0.7

0.5

3

2

1

0

-1

-2

-3

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 45. ANALOG TRACKING REFERENCE SYSTEM ACCURACY vs

TEMPERATURE, MEASURED AT THE FB PIN,

FIGURE 46. ANALOG TRACKING REFERENCE SYSTEM ACCURACY vs

TEMPERATURE, MEASURED AT THE FB PIN,

V

= 0.5V

V

= 1.5V

TRACK

FN8808 Rev.5.00

Jul 13, 2018

Page 22 of 44

ISL78227

Performance Curves Unless otherwise specified, operating conditions for the oscilloscope waveforms are V = 12V,

IN

V

= 36V, and T = +25°C. (Continued)

A

OUT

1.265

1.263

1.261

1.259

1.257

1.255

1.253

1.251

1.249

1.247

1.245

100

90

80

70

60

50

40

30

20

10

0

t_DT2

t_DT1

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 48. GATE DRIVE DEAD TIME vs TEMPERATURE, R = 10k,

DT

FIGURE 47. DIGITAL TRACKING REFERENCE SYSTEM ACCURACY vs

TEMPERATURE, MEASURED AT THE FB PIN, DUTY

CYCLE OF TRACK PIN SIGNAL IS 0.5

t

REFERS TO UG FALLING TO LG RISING, t

DT1

REFERS TO LG FALLING TO UG RISING

DT2

150

140

130

120

t_DT2

110

100

90

t_DT1

80

70

60

50

-50

-25

0

25

50

75

100

125

150

TEMPERATURE (°C)

FIGURE 49. GATE DRIVE DEAD TIME vs TEMPERATURE, R = 18.2k, t

DT

REFERS TO UG FALLING TO LG RISING, t

REFERS TO LG FALLING TO

DT2

DT1

UG RISING

FN8808 Rev.5.00

Jul 13, 2018

Page 23 of 44

ISL78227

DRIVER CONFIGURATION

Operation Description

The ISL78227 is a 2-phase, synchronous boost controller with

integrated drivers. It supports wide input and output ranges of 5V

to 55V during normal operation and the VIN pin withstands

transients up to 60V.

As shown in Figure 4 on page 8, the upper side UGx drivers are

biased by the C

voltage between BOOTx and PHx (where “x”

BOOTx

indicates the specific phase number and same note applied

throughout this document). C is charged by a charge pump

BOOTx

mechanism. PVCC charges BOOTx through the Schottky diode

when LGx is high, pulling PHx low. BOOTx rises with PHx

D

The ISL78227 is integrated with 2A sourcing/3A sinking strong

drivers to support high efficiency and high current synchronous

boost applications. The drivers have a unique feature of adaptive

dead time control of which the dead time can be programmed

for different external MOSFETs, achieving both optimized

efficiency and reliable MOSFET driving. The ISL78227 has

selectable diode emulation and phase dropping functions for

enhanced light-load efficiency.

BOOTx

and maintains the voltage to drive UGx as the D

biased.

is reverse

BOOTx

At start-up, charging to C

from 0 to ~4.5V causes PVCC to

dip slightly. So a typical 5.1Ω resistor R is recommended

BOOTx

PVCCBT

to prevent PVCC from falling below

between PVCC and D

BOOTx

VPORL_PVCC. The typical value for C

is 0.47µF.

BOOTx

The BOOTx to PHx voltage is monitored by UVLO circuits. When

BOOTx to PHx falls below a 3V threshold, the UGx output is

disabled. When BOOTx to PHx rises back above this threshold

plus 150mV hysteresis, the high-side driver output is enabled.

The PWM modulation method is a constant frequency, Peak

Current Mode Control (PCMC), which has benefits of input voltage

feed-forward, a simpler loop to compensate compared to voltage

mode control, and inherent current sharing capability.

For standard boost applications when upper side drivers are not

needed, both UG1 and UG2 can be disabled by connecting either

BOOT1 or BOOT2 to ground before part start-up initialization. PHx

should be connected to ground.

The ISL78227 offers a track function with unique features of

accepting either digital or analog signals for the user to adjust

reference voltage externally. The digital signal track function

greatly reduces the complexity of the interface circuits between

the central control unit and the boost regulator. Equipped with

cycle-by-cycle positive and negative current limiting, the track

function can be reliably facilitated to achieve an envelope

tracking feature in audio amplifier applications, which can

significantly improve system efficiency.

PROGRAMMABLE ADAPTIVE DEAD TIME CONTROL

The UGx and LGx drivers are designed to have an adaptive dead

time algorithm that optimizes operation with varying operating

conditions. In this algorithm, the device detects the off timing of

LGx (UGx) voltages before turning on UGx (LGx).

In addition to the cycle-by-cycle current limiting, the ISL78227 is

implemented with a dedicated, average Constant Current (CC)

control loop for input current. For devices having only peak

current limiting, the average current under peak current limiting

varies significantly because the inductor ripple varies with

In addition to the adaptive dead time control, the dead time

between UGx ON and LGx ON can be programmed by the resistor

at the RDT pin while the adaptive dead time control is still

functioning at the same time. The typical range of programmable

dead time is 55ns to 200ns, or larger. This is intended for

different external MOSFETs applications to adjust the dead time,

maximizing the efficiency while at the same time preventing

shoot-through. Refer to Figure 50 on page 25 for the selection of

changes of V and V

and tolerances of f

and inductors.

IN OUT

SW

The ISL78227’s unique CC control feature accurately controls the

average input current accurately to be constant without

shutdown. Under certain constant input voltage, this means

constant power limiting, which is especially useful for the boost

converter. It helps the user optimize the system with the power

devices’ capability fully utilized by well-controlled constant input

power.

the RDT resistor and dead time, where t

time between UG Falling to LG Rising, and t

DT2

refers to the dead

DT1

time between LG Falling to UG Rising. The dead time is smaller

with a lower value RDT resistor, and it is clamped to minimum

57ns when RDT is shorted to ground. Because a current as large

as 4mA is pulled from the RDT pin if the RDT pin is shorted to

ground, it is recommended to use 5kΩ as the smallest value for

the RDT resistor where the current drawing from the RDT pin is

0.5V/5kΩ = 100µA.

The following sections describe the details of the functions.

Synchronous Boost

To improve efficiency, the ISL78227 employs synchronous boost

architecture as shown in Figure 4 on page 8. The UGx output

drives the high-side synchronous MOSFET, which replaces the

freewheeling diode and reduces the power losses due to the

voltage drop of the freewheeling diode.

While the boost converter is operating in steady state Continuous

Conduction Mode (CCM), each phase’s low-side MOSFET is

controlled to turn on with duty cycle D and ideally, the upper

MOSFET is ON for (1-D). Equation 1 shows the input to output

voltage DC transfer function for boost is:

V

IN

-------------

(EQ. 1)

V

=

OUT

1 – D

FN8808 Rev.5.00

Jul 13, 2018

Page 24 of 44

ISL78227

Digital/Analog Track Function

300

250

200

150

100

50

The TRACK input provides an external reference voltage to be

applied for the output voltage loop to follow, which is useful if the

user wants to change the output voltage as required. An example

is to employ envelope tracking technology in audio power

amplifier applications. The ISL78227 boost stage output is

powering the audio power amplifier stage input, where the boost

output tracks the music envelope signal applied at the TRACK

pin. Ultimately, higher system efficiency can be achieved.

t_DT2

t_DT1

The TRACK pin can accept either a digital signal or an analog

signal by configuring the ATRK/DTRK pin to be connected to

ground or VCC. Figure 51 on page 26 shows the track function

block diagram. VREF_TRK is fed into Gm1 as one of the

reference voltages. The Gm1 takes the lowest voltage of SS,

VREF_TRK, and VREF_1.6V as the actual reference. When

VREF_TRK is the lowest voltage, it becomes the actual reference

voltage for Gm1 and the output voltage can be adjusted with

TRACK signal changes. Regarding the effective VREF_TRK range:

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

RD T (k)

FIGURE 50. DEAD TIME vs RDT, t

REFERS TO UG FALLING TO LG

DT1

REFERS TO LG FALLING TO UG RISING

RISING, t

DT2

• There is no limit for the minimum voltage on the TRACK pin,

but note the lower reference voltage and the lower voltage

feedback regulation accuracy. Note the SS_DONE signal is

checking VREF_TRK ≥0.3V as one of the conditions (refer to

PWM Control

The ISL78227 uses fixed frequency peak current mode control

architecture. As shown in Figure 3 on page 7 and the typical

schematic diagram (Figure 4 on page 8), error amplifier (Gm1)

compares the FB pin voltage and reference voltage and

generates a voltage loop error signal at the COMP pin. This error

signal is compared with the current ramp signal (VRAMP) by the

PWM comparator. The PWM comparator output combined with

fixed frequency clock signal controls the SR flip-flop to generate

the PWM signals (refer to “Peak Current Mode Control” on

page 26).

Figure 58 on page 29 and the t -t description on page 29).

8 9

Also, for the boost converter, the regulated output minimum

voltage is usually the input voltage minus the upper MOSFET’s

body diode drop, in which case, the corresponding voltage at

FB voltage is the minimum effective voltage for the VREF_TRK.

• The Gm1 takes the lowest voltage of SS, VREF_TRK, and

VREF_1.6V as the actual reference. The maximum effective

range for VREF_TRK is determined by VREF_1.6V or SS signal,

whichever is lower. For example, after soft-start, when the SS

pin equals to 3.47V (typical), the maximum effective voltage

for VREF_TRK is 1.6V (VREF_1.6V).

OUTPUT VOLTAGE REGULATION LOOP

The resistor divider R

FB2

page 8) can be selected to set the desired V . V

and R

FB1

from V

OUT

to FB (Figure 4 on

can be

OUT OUT

calculated by Equation 2.

When ATRK/DTRK = GND (DTRK mode), the TRACK pin accepts

digital signal inputs. VREF_TRK (as one of the references input

for the error amplifier Gm1) equals to the average duty cycle

value of the PWM signal’s at the TRACK pin. As shown in

Figure 51 on page 26, the MUX is controlled by the ATRK/DTRK

pin configurations. When ATRK/DTRK = GND, the MUX connects

the output of the Q1 and Q2 switch bridge to the input of a

R









FB2

--------------

V

= V

 1 +



(EQ. 2)

OUT

REF

R



FB1

where in normal operation after soft-start, V

REF

VREF_1.6V or VREF_TRK, whichever is lower.

can be either

Gm1 has three inputs for reference voltage: soft-start ramp SS,

VREF_TRK, and VREF_1.6V. The Gm1 uses the lowest value

among SS, VREF_TRK, and VREF_1.6V. SS, VREF_TRK, and

VREF_1.6V are valid for Gm1 during and after soft-start. In

general operation, VREF_TRK is normally HIGH before soft-start

and SS normally ramps up from a voltage lower than VREF_TRK

and VREF_1.6V, in which case SS controls the output voltage

ramp-up during soft-start. After soft-start is complete, the user

can adjust VREF_TRK for the desired voltage. Because VREF_TRK

is valid before soft-start, setting VREF_TRK lower than SS can

make the SS ramp ineffective because Gm1 uses the lower

VREF_TRK voltage. In such a case, the VREF_TRK becomes the

real soft-start ramp that controls the output voltage ramp-up.

2-stage RC filter (R , C , R , and C ). The PWM signal at the

1

2

TRACK pin controls Q1 and Q2 to chop the 2.5V internal

reference voltage. The phase node of Q1 and Q2 is a PWM signal

with accurate 2.5V amplitude and duty cycle D, where D is the

input PWM duty cycle on the TRACK input pin. The RC filter

smooths out the PWM AC components and the voltage

VREF_TRK after the RC filter becomes a DC voltage equal to

2.5V*D:

(EQ. 3)

V

= 2.5  D

REFTRK

According to Equation 3, the PWM signals’ amplitude at the TRACK

pin does not affect the VREF_TRK accuracy and only the duty cycle

value changes the VREF_TRK value. In general, the VREF_TRK

reference accuracy is as good as the 2.5V reference. The built-in low

pass filter (R , C , R , and C ) converts the PWM signal’s duty

1

2

cycle value to a low noise reference. The low pass filter has a

cutoff frequency of 1.75kHz and a gain of -40dB at 400kHz. The

FN8808 Rev.5.00

Jul 13, 2018

Page 25 of 44

ISL78227

2.5V PWM signal at phase node of Q1 and Q2 has around 25mV at

VREF_TRK, which is 1.56% of 1.6V reference. This will not affect the

boost output voltage because of the limited bandwidth of the

system. A frequency of 400kHz is recommended for the PWM signal

at the TRACK pin. Lower frequency at the TRACK input is possible,

but VREF_TRK has a higher AC ripple. Bench test evaluation is

needed to make sure the output voltage is not affected by this

VREF_TRK AC ripple.

PEAK CURRENT MODE CONTROL

As shown in Figure 3 on page 7, each phase’s PWM operation is

initialized by the fixed clock for this phase from the oscillator

(refer to “Oscillator and Synchronization” on page 27). The clocks

for Phase 1 and Phase 2 are 180° out of phase. The low-side

MOSFET is turned on (LGx) by the clock (after a dead time delay

of t

) at the beginning of a PWM cycle and the inductor current

DT1

ramps up. The ISL78227’s Current Sense Amplifiers (CSA) sense

each phase inductor current and generate the current sense

When ATRK/DTRK = VCC (ATRK mode), the MUX connects the

TRACK pin voltage to the input of the 2-stage RC filter

signal I

. The I

is added with the compensating slope and

SENx

generates V

. When V reaches the error amplifier

RAMPx

R /C /R /C . The TRACK pin accepts analog signal inputs, with the

RAMPx

1

2

(Gm1) output voltage, the PWM comparator is triggered and LGx

is turned off to shut down the low-side MOSFET. The low-side

MOSFET stays off until the next clock signal comes for the next

cycle.

Gm1’s VREF_TRK input equal to the voltage on the TRACK pin. The

low-pass filter has the same cutoff frequency of 1.75kHz.

If not used, the TRACK pin should be left floating or tied to VCC

and the internal VREF_1.6V working as the reference.

After the low-side MOSFET is turned off, the high-side MOSFET

The TRACK function is enabled before the SS pin soft-start. The

turns on after dead time t

. The turn-off time of the high-side

DT2

V

reference can be controlled by TRACK inputs at start-up.

OUT

MOSFET is determined by either the PWM turn-on time at the

next PWM cycle, or when the inductor current becomes zero if

the Diode Emulation mode is selected.

After the SS pin ramps up to the upper clamp AND the VREF_TRK

reaches 0.3V, the upper side FET is controlled to turn on

gradually to achieve smooth transitions from DCM mode to CCM

mode, of which the transition duration is 100ms (when set at

CCM mode). After this transition, PGOOD is allowed to be pulled

HIGH as long as output voltage is in regulation (within OV/UV

threshold).

Multiphase Power Conversion

For an n-phase, interleaved, multiphase boost converter, the

PWM switching of each phase is distributed evenly with 360°/n

phase shift. The total combined current ripples at the input and

output are reduced where smaller input and output capacitors

can be used. In addition, it is beneficial to have a smaller

equivalent inductor for a faster loop design. Also in some

applications, especially in a high current case, multiphase makes

it possible to use a smaller inductor for each phase rather than

one big inductor (single-phase), which is sometimes more costly

or unavailable on the market at the high current rating. Smaller

size inductors also help to achieve low profile design.

The maximum TRACK reference frequency for the boost V

OUT

to

track (VREF_TRK at Figure 51) is limited by the boost converter's

loop bandwidth. Generally, the tracking reference signal’s

frequency should be 10 times lower than the boost loop

crossover frequency. Otherwise, the boost output voltage cannot

track the tracking reference signal and the output voltage is

distorted. For example, for a boost converter with 4kHz loop

crossover frequency, the boost can track reference signals up to

400Hz, typically. Figures 23 and 24 on page 19 show

The ISL78227 is a controller for 2-phase interleaved converter

where the two phases are operating with 180° phase shift,

meaning each PWM pulse is triggered 1/2 of a cycle after the

start of the PWM pulse of the previous phase. Figure 52 on

page 27 illustrates the interleaving effect on input ripple current.

performances tracking 100Hz and 300Hz signals.

The AC component of the two phase currents (I and I ) are

L1 L2

interleaving each other and the combined AC current ripple

(I + I ) at input are reduced. Equivalently, the frequency of the

L1 L2

AC inductor ripple at input is two times of the switching

frequency per phase.

ATRAK/

DTRK

ATRK/DTRK

1k

TRACK

VREF_2.5V

SS

+

M

U

X

VREF_1.6V

2.5*D

Q1

R₁

2M

R₂

2M

+

Gm1

VREF_TRK

+

-

C₂

20p

C₁

20p

Q2

IC INTERNAL CIRCUITS

FB

COMP

FIGURE 51. TRACK FUNCTION BLOCK DIAGRAM

FN8808 Rev.5.00

Jul 13, 2018

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ISL78227

CURRENT SHARING BETWEEN PHASES

I

L1

The peak current mode control inherently has current sharing

capability. As shown in Figure 3 on page 7, the current sense

ramp, V

, of each phase is compared to the same error

RAMPx

amplifier’s output at the COMP pin by the PWM comparators to

turn off LGx when V reaches COMP. Thus, the V

t

180°

RAMPx

I

peaks are controlled to be the same for each phase. V

is

L2

RAMPx

the sum of instantaneous inductor current sense ramp and the

compensating slope. Because the compensating slopes are the

same for both phases, the inductor peak current of each phase is

controlled to be the same.

I

+ I

L1 L2

The same mechanism applies if multiple ISL78227s are

configured in parallel for a multiphase boost converter. The

COMP pin of each ISL78227 is tied together for each phase’s

current sense ramp peak to be compared with the same COMP

t

voltage (V

= COMP), thus, the inductor peak currents of all

RAMPx

the phases are controlled to be the same. The “4-Phase

Operation” section describes how to configure two ISL78227s in

parallel for a 4-phase, interleaved boost converter.

FIGURE 52. PHASE NODE AND INDUCTOR-CURRENT WAVEFORMS

FOR 2-PHASE CONVERTER

To understand the reduction of the ripple current amplitude in the

multiphase circuit, refer to Equation 4, which represents an

individual phase’s peak-to-peak inductor current.

4-PHASE OPERATION

Two ISL78227s can be used in parallel to achieve interleaved

4-phase operation. Figure 54 shows the recommended

configuration. The CLKOUT from the master IC drives FSYNC of

the slave IC to synchronize the switching frequencies. This

achieves a 90° phase shift for the four phases switching and the

respective COMP, FB, SS, EN, and IMON pins of the two ICs are

connected.

In Equation 4, V and V

IN OUT

respectively, L is the single-phase inductor value, and f

switching frequency.

are the input and output voltages

is the

SW

V

– V  V

IN IN

OUT

Lf

(EQ. 4)

I

= -----------------------------------------------

PPCH

V

SW

OUT

CLKOUT is 90°out-of-phase with the rising edge of LG1.

Therefore, the two phases of the second IC are interleaved with

the two phases of the first IC.

The input capacitors conduct the ripple component of the

inductor current. In the case of a 2-phase boost converter, the

capacitor current is the sum of the ripple currents from each of

the individual phases. Use Equation 5 to calculate the

CLKOUT

COMP

FB

FSYNC

COMP

FB

peak-to-peak ripple of the total input current which goes through

the input capacitors, where K

the specific duty cycle.

can be found in Figure 53 under

P-P

MASTER IC

ISL78227

SLAVE IC

ISL78227

SS

IMON

EN

I

= K

 I

P-P PPCH

(EQ. 5)

IMON

EN

PPALL

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

FIGURE 54. CONFIGURATIONS FOR DUAL IC, 4-PHASE OPERATION

Oscillator and Synchronization

The switching frequency is determined by the selection of the

frequency-setting resistor, R

, connected from the FSYNC

pin to GND. Equation 6 is provided to assist in selecting the

FSYNC

correct resistor value, where f

each phase.

is the switching frequency of

SW

10

–8



0.505







--------------

R

= 2.49x10

– 5.5X10

(EQ. 6)

FSYNC

f

SW

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE

FIGURE 53. K

P-P

vs DUTY CYCLE

FN8808 Rev.5.00

Jul 13, 2018

Page 27 of 44

ISL78227

Figure 55 shows the relationship between R

frequency.

and switching

FSYNC

LG1_IC_Master

t

/4 - t

SW DT1

300

250

200

150

100

50

CLKOUT_IC_Master

FSYNC_IC_Slave

LG1_IC_Slave

35ns + t

DT1

t1 t2 t3

FIGURE 56. TIMING DIAGRAM OF CLKOUT vs LG1 AND FSYNC vs LG1

(CLKOUT_MASTER CONNECTED TO FSYNC_SLAVE)

0

After the ISL78227 latches to being synchronized with the

external clock, if the external clock on the FSYNC pin is removed,

the switching frequency oscillator shuts down. The part then

detects PLL_LOCK fault (refer to Table 3 on page 34), and goes to

either Hiccup mode or Latch-off mode, depending on the

HIC/LATCHOFF pin configuration. If the part is set in Hiccup

mode, it restarts with frequency set by the resistor at the FSYNC

pin.

0

100 200 300 400 500 600 700 800 900 1000 1100

f_SW(kHz)

FIGURE 55. f

vs R

FS

SW

The ISL78227 contains a Phase Lock Loop (PLL) circuit.

Referring to Figure 4 on page 8, the PLL is compensated with a

series resistor-capacitor (R

to GND and a capacitor (C

and C

) from the PLLCOMP pin

) from PLLCOMP to GND. At the

PLL

PLL1

PLL2

300kHz switching frequency, typical values are R

= 3.24kΩ,

= 1nF. The PLL locking time is around

PLL

The switching frequency range of the ISL78227 set by R

by synchronization is typically 50kHz to 1.1MHz.

or

FSYNC

C

= 6.8nF, and C

PLL2

PLL1

0.7ms. Generally, the same PLL compensating network can be

used in the frequency range of 50kHz to 1.1MHz. With the same

PLL compensation network, at a frequency range higher than

500kHz, the PLL is overcompensated. However, the PLL is stable

just with slow frequency response. If a faster frequency response

is required at a higher operating frequency, the PLL

compensation network can be tuned to have a faster response.

An Excel spreadsheet to calculate the PLL compensation is

provided on the ISL78227 product page.

The low end 50kHz is determined by a PLL_LOCK fault

protection, which shuts down the IC when frequency is lower than

37kHz typical.

The phase dropping mode is not allowed with external

synchronization.

MINIMUM ON-TIME (BLANK TIME) CONSIDERATION

The minimum ON-time (also called BLANK time) of LGx is the

minimum ON pulse width as long as LGx is turned ON. It is also

intended for the internal circuits to blank out the noise spikes

The ISL78227’s switching frequency can be synchronized to the

external clock signals applied at the FSYNC pin. The ISL78227

detects the input clock’s rising edge and synchronizes the rising

edge of LG1 to the input clock’s rising edge with a dead time

after LGx turns on. The t

at the RBLANK pin.

can be programmed by a resistor

MINON

delay of t

. The switching frequency of each phase equals the

DT1

The selection of the t

MINON

depends on two considerations.

fundamental frequency of the clock input at FSYNC. Because the

ISL78227 detects only the edge of the input clock instead of its

pulse width, the input clock’s pulse width can be as low as 20ns

(as minimum), tens of ns, or hundreds of ns, depending on the

capability of the specific system to generate the external clock.

1. The noise spike durations after LGx turns on, which is

normally in a range of tens of ns to 100ns or longer,

depending on the external MOSFET switching characteristic

and noise coupling path to current sensing.

2. Ensure the charging of the boot capacitor during operations of

The CLKOUT pin outputs a clock signal with the same frequency

LGx operating at t

. One typical case is an operation

MINON

when the input voltage is close to the output voltage. The duty

cycle is smallest at t , and C is charged by PVCC

of the per-phase switching frequency. Its amplitude is V and

CC

the pulse width is 1/12 of the per-phase switching period

MINON

BOOTx

(t /12). Figure 56 shows the application example to put two

SW

via D

with short duration of t

minus the delay to

BOOTx

MINON

pull phase low. If such operation is required, especially when

a large MOSFET with large Q is used to support heavy load

ISL78227s in parallel for 4-phase, interleaved operation, with the

master IC’s CLKOUT being connected to the FSYNC pin of the

slave IC. The master IC outputs CLKOUT signal with a delay of

g

application, larger t

resistor at the RBLANK pin to ensure C

BOOTx

can be programmed with the

can be

MINON

t

/4 - t

after LG1_master. The slave IC FSYNC pin takes the

SW

DT1

CLKOUT_master as the input and the slave’s IC LG1 is delayed by

a time of 35ns + t . Therefore, the LG1_slave is delayed by

sufficiently charged during minimum duty cycle operation.

DT1

/4+35ns to LG1_master, which is approximately a 90° phase

t

SW

shift. With 90°phase shift between LG1 and respective LG2 for

each IC, an interleaved 4-phases with 90° phase shift boost is

achieved.

FN8808 Rev.5.00

Jul 13, 2018

Page 28 of 44

ISL78227

Refer to Figure 57 for the selection of RBLANK resistor and

t - t : The enable comparator holds the ISL78227 in shutdown

1 2

t

time. A 5kΩ resistor is recommended as the minimum

until the V rises above 1.2V (typical) at the time of t . During

MINON

EN

1

R

resistor.

t - t , V

gradually increases and reaches the internal

BLANK

1

2

PVCC/VCC

Power-On Reset (POR) rising threshold 4.5V (typical) at t .

2

500

450

400

350

300

250

200

150

100

50

t - t : During t - t , the ISL78227 self-calibrates to detect

2

3

2

3

certain pin configurations (HIC/LATCH, DE/PHDRP,

ATRK/DTRAK) to latch in the selected operation modes. The time

duration for t - t is typically 195µs.

2

3

t - t : During this period, the ISL78227 waits until the internal

3

4

PLL circuits are locked to the preset oscillator frequency. When

PLL locking is achieved at t , the oscillator generates output at

4

the CLK_OUT pin. The time duration for t - t depends on the

3

4

PLLCOMP pin configuration. The PLL is compensated with a

series resistor-capacitor (R

and C

) from the PLLCOMP pin

) from PLLCOMP to GND. At the

PLL

PLL1

to GND and a capacitor (C

PLL2

0

300kHz switching frequency, typical values are R

= 3.24kΩ,

PLL

5

10 15 20 25 30 35 40 45 50 55 60 65 70

C

= 6.8nF, and C

= 1nF. With this PLLCOMP

PLL1

PLL2

R

(k)

BLANK

compensation, the time duration for t - t is around 0.7ms.

3

4

FIGURE 57. t

vs RBLANK

MINON

t - t : During this period, the PLL locks the frequency t and the

4

5

4

system prepares to soft-start. The ISL78227 has one unique

feature to pre-bias the SS pin voltage to be equal to V during

Operation Initialization and Soft-Start

FB

Before converter initialization, the EN pin voltage must be higher

than its rising threshold and the PVCC/VCC pin must be higher

than the rising POR threshold. When these conditions are met, the

controller begins initialization and soft-start. Figure 58 shows the

ISL78227 internal start-up timing diagram from the power-up to

soft-start.

t - t , which is around 50µs.

4

5

t - t : At t , the soft-start ramps up at the SS pin (V ) and

SSPIN

5

6

5

the COMP voltage starts to ramp up as well. Drivers are enabled

but not switching during t - t because the COMP is still below

5

6

the current sense ramp offset. The device operates in diode

emulation mode during soft-start period t - t . The slew rate of

5

8

the SS ramp and the duration of t - t are determined by the

5

8

capacitor used at the SS pin.

EN

1.2V

t - t : At t , COMP is above the current sense ramp offset and

6

7

6

the drivers start switching. Output voltage ramps up while FB

POR_R

PVCC/VCC

voltage is following SS ramp during this soft-start period. At t ,

7

output voltage reaches the regulation level and FB voltage

reaches VREF_1.6V.

PLLCOMP

CLKOUT

t - t : At this stage, SS continues ramping up until it reaches the

7

8

SS clamp voltage (V

) 3.47V at t , indicating the SS pin

SSPCLAMP

8

ramp-up is completed. At t , the ISL78227 generates an internal

8

SS_DONE signal, which goes HIGH when both V

=

SSPIN

(3.47V) and VREF_TRK ≥ 0.3V (as shown in Figure 3

LG

UG

V

SSPCLAMP

on page 7). This indicates the soft-start has completed.

t - t : After t , a delay time of either 0.5ms or 100ms is inserted

8

9

8

before the PGOOD pin is released HIGH at t , depending on the

selected mode (refer to Table 2 on page 33).

9

COMP_Ramp_Offset

COMP

SS

1. If the DE/PHDRP pin = VCC or FLOAT to have DE mode

selected, the PGOOD rising delay from V

(3.47V) and VREF_TRK ≥0.3V to PGOOD rising is 0.5ms.

= V

SSPIN

SSPCLAMP

VFB

2. If the DE/PHDRP pin = GND to have CCM mode selected, the

PGOOD rising delay from V

= V (3.47V) and

PGOOD

SSPIN

SSPCLAMP

VREF_TRK ≥0.3V to PGOOD rising is 100ms, during which

period the device is transitioning from DE mode to CCM mode.

The high-side gate UGx is controlled to gradually increase the

ON-time to finally merge with CCM ON-time. This synchronous

MOSFET “soft-ON” feature is unique and ensures smooth

transition from DCM mode to CCM mode after soft-start

completes. More importantly, this “SYNC FET soft-ON”

function eliminates the large negative current, which often

t t

2 3

t

4 5

t

8 9

t

1

6

7

FIGURE 58. CIRCUIT INITIALIZATION AND SOFT-START

Assuming input voltage is applied to the VIN pin before t and VCC

1

is connected to PVCC, as shown on Figure 58, the descriptions for

start-up procedures are described as follows:

FN8808 Rev.5.00

Jul 13, 2018

Page 29 of 44

ISL78227

occurs when starting up to a high pre-biased output voltage.

the output voltage is within 80% to 120% of the reference

voltage VREF_1.6V.

This feature makes the system robust for all the challenging

start-up conditions and greatly improves the system

reliability.

As described at the t - t duration in “Operation Initialization

8

9

and Soft-Start” on page 29, the PGOOD pin is pulled low during

soft-start and it is released high after SS_DONE with a 0.5ms or

100ms delay.

Enable

To enable the device, the EN pin needs to be driven higher than

1.2V (typical) by the external enable signal or resistor divider

between VIN and GND. The EN pin has an internal, 5MΩ (typical),

pull-down resistor. This pin also has an internal 5.2V (typical)

clamp circuit with a 5kΩ (typical) resistor in series to prevent

excess voltage applied to the internal circuits. When applying the

EN signal using resistor divider from VIN, internal pull-down

resistance needs to be considered. Also, the resistor divider ratio

needs to be adjusted as its EN pin input voltage may not exceed

5.2V.

PGOOD is pulled low if any of the comparators for FB_UV, FB_OV

or VIN_OV, is triggered for a duration longer than 10µs.

In normal operation after start-up, under fault recovery, PGOOD

is released high with the same 0.5ms delay time after the fault is

removed.

Current Sense

The ISL78227 peak current control architecture senses the

inductor current continuously for fast response. A sense resistor

is placed in series with the power inductor for each phase. The

ISL78227 Current Sense Amplifiers (CSA) continuously sense the

respective inductor current as shown in Figure 60 on page 31 by

To disable or reset all fault status, the EN pin needs to be driven

lower than 1.1V (typical). When the EN pin is driven low, the

ISL78227 turns off all of the blocks to minimize the off-state

quiescent current.

sensing the voltage signal across the sense resistor, R

SENx

(where “x” indicates the specific phase number and same note

applied throughout this document). The sensed current for each

active phase is used for peak current mode control loop, phase

current balance, individual phase cycle-by-cycle peak current

limiting (OC1), individual phase overcurrent fault protection

(OC2_PEAK), input average Constant Current (CC) control and

average overcurrent protection (OC_AVG), diode emulation, and

phase drop control. The internal circuitry shown in Figure 60

represents a single phase. This circuitry is repeated for each

phase.

VIN

VCC

EN

5k

TO INTERNAL

CIRCUITS

FROM

EXTERNAL

EN CONTROL

+

-

5.2V

CLAMP

5M

1.2V

FIGURE 59. ENABLE BLOCK

Soft-Start

Soft-start is implemented by an internal 5µA current source

charging the soft-start capacitor (C ) at SS to ground. The

SS

voltage on the SS pin slowly ramps up as the reference voltage

for the FB voltage to follow during soft-start.

Typically, for boost converter before soft-start, its output voltage

is charged up to be approximately a diode drop below the input

voltage through the upper side MOSFETs’ body diodes. To more

accurately correlate the soft-start ramp time to the output

voltage ramp time, the ISL78227 SS pin voltage is pre-biased

with voltage equal to FB voltage before soft-start begins. The

soft-start ramp time for the boost output voltage ramping from

V

to the final regulated voltage V

, can be calculated by

is 1.6V (VREF_1.6V) with the TRACK pin

IN

OUTreg

Equation 7, where V

tied HIGH:

REF

V

C

SS

5A





IN

------------------------ -----------

t

= V

 1 –







(EQ. 7)

SS

REF

V





OUTreg

PGOOD Signal

The PGOOD pin is an open-drain logic output to indicate that the

soft-start period is completed, the input voltage is within safe

operating range, and the output voltage is within the specified

range. The PGOOD comparator monitors the FB pin to check if

FN8808 Rev.5.00

Jul 13, 2018

Page 30 of 44

ISL78227

Equation 11, where I is the per-phase current flowing through

Lx

CURRENT SENSE FOR INDIVIDUAL PHASE - I

SENX

R

.

SENx

R_SENx

I_L

L

R

-

+

V_IN

V_OUT

SENx

------------------

I

= I



Lx

(EQ. 11)

SENx

R

SETx

+

R_SETxA

-

R_BIASxA

-

R

is normally selected with smallest resistance to minimize

SENx

the power loss on it. With R

C_ISENx

selected, R

is selected by

SENx

SETx

I_SENx+112µA

112µA

the desired cycle-by-cycle peak current limiting level OC1 (refer to

“Peak Current Cycle-by-Cycle Limiting (OC1)” on page 35).

+

R_SETxB

R_BIASxB

-

AVERAGE CURRENT SENSE FOR TWO PHASES - IMON

ISENxP

ISENxN

The IMON pin serves to monitor the total average input current of

the 2-phase boost. As shown in Figure 3 on page 7, the individual

I_BIAS

112µA

current sense signals (I

) are divided by eight and summed

112µA

SENx

together. A 17µA offset current is added to form a current source

output at the IMON pin with the value calculated as shown in

Equation 12.

CSA

I_SENx

I

 R

I

 R

L2

SEN2

R

SET2













L1

–6

SEN1

------------------------------- -------------------------------

IMON =

+

 0.125 + 17  10

R

SET1

(EQ. 12)

I_SENx

Assume R

= R

, R

= R

, and I = I + I

,

SEN1

SEN2 SET1

SET2

IN L1 L2

IC INTERNAL CIRCUITS

FIGURE 60. CURRENT-SENSING BLOCK DIAGRAM

which is the total boost input average current:

R

–6

SEN

The RC network between the R

SENx

in Figure 60 is the recommended configuration. The ISENxP pin

should be connected to the positive potential of the R

and ISENxP/N pins as shown

---------------

IMON = I



 0.125 + 17  10

(EQ. 13)

IN

R

SET

SEN_CHx

is composed by

through resistor R

, where in Figure 60, R

SETx

As shown in Figure 4 on page 8, a resistor R

is placed

IMON

between the IMON pin and ground, which turns the current sense

output from the IMON pin to a voltage V . A capacitor C

R

plus R

. R

is used to set the current sense gain

SETxA

externally.

SETxB SET

IMON

should be used in parallel with R

to filter out the ripple such

IMON

R

= R

+ R

SETxB

(EQ. 8)

SETx

SETxA

that V

represents the total average input current of the

IMON

2-phase boost. V

can be calculated using Equation 14.

IMON

Because there is an 112µA bias current sinking to each of the

ISENxP and ISENxN pins, R with the same value to R

(EQ. 14)

V

= IMON  R

IMON

BIASx

should be placed between the ISENxN pin to the low potential of

the R , where in Figure 60, R is composed by R

SETx

As shown in Figure 3 on page 7, V

IMON

is sent to inputs of Gm2

SENx BIASx BIASxA

plus R

.

and comparators of CMP_PD and CMP_OCAVG for the following

functions:

BIASxB

R

= R

+ R

BIASxB

(EQ. 9)

(EQ. 10)

BIASx

BIASxA

1. V

is compared with 1.6V (VREF_CC) at error amplifier

IMON

Gm2 inputs to achieve constant current control function. The

CC control threshold for the boost input current is typically set

in a way that the per-phase average inductor current (when CC

control) is lower than the per-phase cycle-by-cycle peak

current limiting (OC1) threshold. Refer to “Constant Current

Control (CC)” on page 35 for detailed descriptions.

R

= R

SETx

It is recommended to have R

SETxA

= R

BIASxA

and

) between them

R

= R

, and insert a capacitor (C

SETxB

BIASxB ISENx

as shown in Figure 60. This will form a symmetric noise filter for

the small current sense signals. The differential filtering time

constant equals to (R

is typically selected in range of tens of ns depending on the

actual noise levels.

2. V

is compared with phase dropping thresholds (1.1V

IMON

+R

)*C

. This time constant

SETxA BIASxA

ISENx

falling to drop Phase 2, 1.15V rising to add Phase 2). Refer to

“Automatic Phase Dropping/Adding” on page 33 for detailed

descriptions.

CSA generates the sensed current signal I

by forcing ISENxP

SENx

voltage to be equal to ISENxN voltage. Because R

3. V

is compared with 2V for OC_AVG fault protections.

IMON

is equal to

SETx

incurred by the

Refer to “Average Overcurrent Fault (OC_AVG) Protection” on

page 36 for detailed descriptions.

R

, the voltage drop across R

and R

BIASx

fixed 112µA bias current cancels each other. Therefore, the

resulting current at CSA output I is proportional to each

SETx

BIASx

SENx

per phase can be derived in

phase inductor current, I . I

Lx SENx

FN8808 Rev.5.00

Jul 13, 2018

Page 31 of 44

ISL78227

The typical scenario when fast overloading is applied is described

as follows: When a large overload is suddenly applied at boost

output, the phase inductor peak currents are initially limited by

OC1 cycle-by-cycle, during which time the IMON voltage slowly

R_SENx

I_L

L

-

+

V_OUT

V_IN

R_SETx

R_BIASx

rises due to the filter delay of R

and C

. When V

IMON

reaches 1.6V, the CC loop starts to limit and control the average

current to be constant, which lowers the inductor current (as

described previously, CC threshold normally is set lower than the

OC1 cycle-by-cycle limiting threshold). Typically, tens of nF are

k1*I_SENx

V_RAMP

ISENxN

CSA

used for C

. When a longer time delay is needed, larger

can be used. Refer to “Constant Current Control (CC)” on

IMON

ISENxP

SLOPE

C

R_RAMP

IMON

I_SLOPE= k2*0.5V/R_SLOPE

VSL

page 35 for a more detailed description.

I_SL

0.5V

R_SLOPE

Adjustable Slope Compensation

C_SL

LGx

For a boost converter with peak current mode control, slope

compensation is needed when the duty cycle is larger than 50%.

It is advised to add slope compensation when the duty cycle is

approximately 30% to 40% because a transient load step can

push the duty cycle higher than the steady state level. When

slope compensation is too low, the converter suffers from

subharmonic oscillation, which may result in noise emissions at

half the switching frequency. On the other hand,

I_SL0

m_a

m_b

I_SENx

overcompensation of the slope may reduce the phase margin.

Therefore, proper design of the slope compensation is needed.

m_SL

The ISL78227 features adjustable slope compensation by setting

I_SL

the resistor value, R

, from the SLOPE pin to ground. This

SLOPE

function eases the compensation design and provides more

flexibility in choosing the external components.

m_a1= m_a+ m_SL

V_RAMP

_RAMP= (I_SENx+I_SL)*R_RAMP

Figure 61 shows the block diagram related to slope compensation.

For current mode control, in theory, the compensation slope slew

V

rate m needs to be larger than 50% of the inductor current

down ramp slope slew rate m .

b

SL

FIGURE 61. SLOPE COMPENSATION BLOCK DIAGRAM

Light-Load Efficiency Enhancement

Equation 15 shows the resistor value, R

to create a compensation ramp:

, at the SLOPE pin

SLOPE

For switching mode power supplies, the total loss is related to

conduction loss and switching loss. The conduction loss

dominates at heavy load, while the switching loss dominates at

light-load condition. Therefore, if a multiphase converter is

running at a fixed phase number for the entire load range, the

efficiency starts to drop significantly below a certain load current.

The ISL78227 has selectable automatic phase dropping,

cycle-by-cycle diode emulation and pulse skipping features to

enhance the light-load efficiency. By observing the total input

current on-the-fly and dropping an active phase, the system can

achieve optimized efficiency over the entire load range.

5

6.67  10  L  R

x

SETx

---------------------------------------------------------------------------------------



(EQ. 15)

R

=

SLOPE

K

 V

– V   R

OUT IN

SENx

SLOPE

where K

is the selected gain of compensation slope over

SLOPE

inductor down slope. For example, K

= 1 gives the R

SLOPE

value generating a compensation slope equal to inductor current

down ramp slope. Theoretically, the K needs to be larger

SLOPE

than 0.5, but practically more than 1.0 is used in the actual

application. To cover the operating range, the maximum of V

OUT

and minimum of V should be used in Equation 15 to calculate

IN

The Phase Dropping (PH_DROP) and Diode Emulation (DE)

functions can be selected to be active or inactive by setting the

DE/PHDRP pin. Refer to Table 2 on page 33 for the three

configuration modes.

the R

.

SLOPE

1. When DE/PHDRP = V , Diode Emulation function is enabled

CC

and Phase Drop function is disabled.

2. When DE/PHDRP = FLOAT, both Diode Emulation and Phase

Drop functions are enabled.

3. When DE/PHDRP = GND, both Diode Emulation and Phase

Drop functions are disabled. The part is set in Continuous

Conduction Mode (CCM).

FN8808 Rev.5.00

Jul 13, 2018

Page 32 of 44

ISL78227

DIODE EMULATION AT LIGHT-LOAD CONDITION

TABLE 2. CCM/DE/PH_DROP MODE SETTING (DE/PHDRP PIN)

When the Diode Emulation mode (DE) is selected to be enabled

(Mode 1 and Mode 2 in Table 2), the ISL78227 has cycle-by-cycle

diode emulation operation at light load achieving Discontinuous

Conduction Mode (DCM) operation. With DE mode operation,

negative current is prevented and the conduction loss is reduced,

therefore, high efficiency can be achieved at light-load

conditions.

MODE NUMBER

(NAME)

DE/PHDRP PIN

SETTING

PHASE-DROP

MODE

DE MODE

Enabled

Disabled

1 (DE)

VCC

FLOAT

GND

Disabled

Enabled

Disabled

2 (DE+PH_DROP)

3 (CCM)

AUTOMATIC PHASE DROPPING/ADDING

Diode emulation occurs during t -t (on Figure 58 on page 29),

5 8

regardless of the DE/PHDRP operating modes (Table 2).

When the Phase Drop function is enabled, the ISL78227

automatically drops or adds Phase 2 by comparing the V

to

IMON

PULSE SKIPPING AT DEEP LIGHT-LOAD CONDITION

the phase dropping/adding thresholds. V

is proportional to

IMON

If the converter enters Diode Emulation mode and the load is still

reducing, eventually pulse skipping occurs to increase the deep

light-load efficiency. Either Phase 1, Phase 2, or both, pulse skips

at these deep light-load conditions.

the average input current indicating the level of the load.

The phase dropping mode is not allowed with external

synchronization.

Phase Dropping

Fault Protections/Indications and Current

Limiting

The ISL78227 is implemented with comprehensive fault

protections/indications and current limitings to design a highly

reliable boost converter. Most of the fault protections’ responses

can be selected to be either Hiccup or Latch-off by configuring

the HIC/LATCH pin, which offers the flexibility upon the specific

requirements for different applications.

When load current drops and V

IMON

falls below 1.1V, Phase 2 is

disabled. For better transient response during phase dropping,

the ISL78227 gradually reduces the duty cycle of the phase from

steady state to zero, typically within 8 to 10 switching cycles. This

gradual dropping scheme helps smooth the change of the PWM

signal and stabilizes the system when phase dropping happens.

From Equations 13 and 14, the phase dropping current threshold

level for the total, 2-phase boost input current can be calculated

by Equation 16.

SELECTABLE HICCUP OR LATCH-OFF FAULT RESPONSE

Table 3 on page 34 lists the fault protections that can have either

Hiccup or Latch-off fault response determined by HIC/LATCH pin

configurations.

R

–6



1.1

SET







(EQ. 16)

------------------

---------------

I

=

– 17  10



 8A

INphDRP

R

IMON

SEN

• When the HIC/LATCH pin is pulled high (VCC), the fault response

is in Hiccup mode.

Phase Adding

Phase adding is decided by the two mechanisms listed below.

Phase 2 is added immediately if either of the two following

conditions are met.

• When the HIC/LATCH pin is pulled low (GND), the fault response is

in Latch-off mode.

In Hiccup mode, the device stops switching when a fault

condition in Table 3 on page 34 is detected, and restarts from

soft-start after 500ms (typical). This operation is repeated until

fault conditions are completely removed.

1. V

>1.15V, the IMON pin voltage is higher than phase

IMON

adding threshold 1.15V. The phase adding current threshold

level for the total 2-phase boost input current can be

calculated by Equation 17.

In Latch-off mode, the device stops switching when a fault

condition in Table 3 on page 34 is detected and PWM switching

being kept off even after fault conditions are removed. In

Latch-off status, the internal LDO is alive to keep PVCC voltage

regulated. By either toggling the EN pin or cycling VCC/PVCC

below the POR threshold restarts the system.

R

–6



1.15

SET







(EQ. 17)

------------------

---------------

I

=

– 17  10



 8A

INphADD

R

IMON

SEN

2. I

>80µA (OC1), individual phase current triggers OC1.

SENx

The first is similar to the phase dropping scheme. When the load

increases causing V >1.15V, Phase 2 is added back

IMON

immediately to support the increased load demand. Because the

IMON pin normally has large RC filter and V is average

IMON

current signal, this mechanism has a slow response and is

intended for slow load transients.

The second mechanism is intended to handle the case when load

increases quickly. If the quick load increase triggers OC1

(I

>80µA) in either of the two phases, Phase 2 is added back

SENx

immediately.

After Phase 2 is added, the phase dropping function is disabled

for 1.5ms. After this 1.5ms expires, the phase dropping circuit is

activated again and Phase 2 can be dropped automatically as

usual.

FN8808 Rev.5.00

Jul 13, 2018

Page 33 of 44

ISL78227

TABLE 3. FAULT NAMES LIST FOR THE HICCUP OR LATCH-OFF FAULT RESPONSE

FAULT RESPONSE

HIC/LATCH = VCC: HICCUP

FAULT NAME

HIC/LATCH = GND: LATCH-OFF

DESCRIPTION

VIN_OV

Set by the HIC/LATCH pin

Input overvoltage fault (VIN_PIN >58V) protection

response is Hiccup when HIC/LATCH = VCC, and Latch-off

when HIC/LATCH = GND

OC_AVG

OC2_PEAK

VOUT_OV

Set by the HIC/LATCH pin

Input average overcurrent fault (IMON_PIN >2V) protection

response is Hiccup when HIC/LATCH = VCC, and Latch-off

when HIC/LATCH = GND

Peak overcurrent fault (I

SENx

>105µA) protection response

is Hiccup when HIC/LATCH = VCC, and Latch-off when

HIC/LATCH = GND

Output overvoltage fault (FB_PIN >120%*VREF_1.6V)

protection response is Hiccup when HIC/LATCH = VCC, and

Latch-off when HIC/LATCH = GND

PLLCOMP_SHORT

PLL_LOCK

PLLCOMP_SHORT fault (PLLCOMP_PIN >1.7V) protection

response is Hiccup when HIC/LATCH = VCC, and Latch-off

when HIC/LATCH = GND

PLL fault (detect the minimum frequency of 37kHz as

typical) protection response is Hiccup when

HIC/LATCH = VCC, and Latch-off when HIC/LATCH = GND

the PWM switching and enters either Hiccup or Latch-off mode,

depending on HIC/LATCH pin configuration as described in

“Selectable Hiccup or Latch-Off Fault Response” on page 33 and

Table 3 on page 34.

INPUT OVERVOLTAGE FAULT PROTECTION

As shown in Figure 3 on page 7, the ISL78227 monitors the VIN

pin voltage divided by 48 (VIN/48) as the input voltage

information. This fault detection is active at the beginning of

soft-start (t as shown in Figure 58 on page 29).

Under the selection of Hiccup response for the VOUT_OV fault,

when the output voltage falls down to be lower than the VOUT_OV

threshold of 120% * VREF_1.6V minus 4% hysteresis, the device

returns to normal switching through Hiccup soft-start. The

PGOOD pin is released to be pulled high after 0.5ms delay.

5

The VIN_OV comparator compares VIN/48 to 1.21V reference to

detect if VIN_OV fault is triggered. Equivalently, when V >58V

(for 5µs), VIN_OV fault event is triggered. The PGOOD pin is pulled

low.

IN

Equivalently, the V

OUT

overvoltage threshold is set at the same

(set by

At the same time the VIN_OV fault condition is triggered, the

ISL78227 responds with fault protection actions to shut down

the PWM switching and enters either Hiccup or Latch-off mode,

depending on HIC/LATCH pin configuration as described in

“Selectable Hiccup or Latch-Off Fault Response” on page 33 and

Table 3 on page 34.

percentage of V

target voltage V

OUT

OUT_TARGET

VREF_1.6V) because the device uses the same FB voltage to

regulate the output voltage with the same resistor divider

between V

and the FB pin (refer to Equation 2 on page 25).

OUT

Therefore, the V

overvoltage protection threshold is set at

OUT

120% of V

. According to Equation 2 on page 25, the

OUT_TARGET

Under the selection of Hiccup response for the VIN_OV fault,

when the output voltage falls lower than the VIN_OV threshold

58V, the device returns to normal switching through Hiccup

soft-start. PGOOD is released to be pulled high after a 0.5ms

delay.

V

overvoltage protection threshold can be calculated using

OUT

Equation 18.

R









FB2

--------------

VOUT

= 1.2  1.6  1 +



(EQ. 18)

OVP

R



FB1

OUTPUT OVERVOLTAGE FAULT PROTECTION

OUTPUT UNDERVOLTAGE INDICATION

The ISL78227 monitors the FB pin voltage to detect if an output

overvoltage fault (VOUT_OV) occurs. This fault detection is active

The ISL78227 monitors the FB pin voltage to detect if an output

undervoltage (VOUT_UV) occurs.

at the beginning of soft-start (t as shown in the Figure 58 on

5

If the FB pin voltage is lower than 80% of the voltage regulation

reference VREF_1.6V, the VOUT_UV comparator is triggered to

indicate VOUT_UV occurring and the PGOOD pin is pulled low.

However, there is no fault protection action for the VOUT_UV

condition; the ISL78227 continues PWM switching and normal

operation when VOUT_UV occurs.

page 29).

If the FB pin voltage is higher than 120% of the voltage

regulation reference, VREF_1.6V, the VOUT_OV comparator is

triggered to indicate an VOUT_OV fault and the PGOOD pin is

pulled low.

At the same time, when a VOUT_OV fault is triggered, the

ISL78227 responds with fault protection actions to shut down

FN8808 Rev.5.00

Jul 13, 2018

Page 34 of 44

ISL78227

When the output voltage rises back above the VOUT_UV

threshold of 80% * VREF_1.6V plus 4% hysteresis, PGOOD is

released to be pulled high after a 0.5ms delay.

Peak Overcurrent Fault (OC2_PEAK) Protection

If either of the two individual phase’s current sense signals I

(calculated by Equation 11 on page 31) reaches 105µA

SENx

(OC2_TH = 105µA) for three consecutive switching cycles, the

Peak Overcurrent fault (OC2_PEAK) is triggered. The ISL78227

responds with fault protection actions to shut down the PWM

switching and enters either Hiccup or Latch-off mode depending

on HIC/LATCH pin configuration as described in “Selectable

Hiccup or Latch-Off Fault Response” on page 33 and Table 3 on

page 34.

Equivalently, the V

OUT

undervoltage threshold is set at the same

(set by

percentage of V

target voltage V

OUT

OUT_TARGET

VREF_1.6V) because the device uses the same FB voltage to

regulate the output voltage with the same resistor divider

between V

Therefore, the V

OUT

and the FB pin (refer to Equation 2 on page 25).

undervoltage threshold is set at 80% of

OUT

V

. According to Equation 2 on page 25, the V

OUT_TARGET OUT

undervoltage protection threshold can be calculated using

Equation 19.

This fault protection is intended to protect the device by

shutdown (Hiccup or Latch-off) from the worst case condition

where OC1 cannot limit the inductor peak current.

R









FB2

--------------

FB1

VOUT

= 0.8  1.6  1 +



(EQ. 19)

UV

R



This fault detection is active at the beginning of soft-start (t as

5

shown in the Figure 58 on page 29).

OVERCURRENT LIMITING AND FAULT PROTECTION

Under the selection of Hiccup response for the OC2_PEAK fault,

The ISL78227 has multiple levels of overcurrent

when both phases’ peak current sense signals I

no longer

SENx

protection/limiting. Each phase’s peak inductor current is

protected from overcurrent conditions by limiting its peak

current. The combined total current is protected on an average

basis. Also, each phase is implemented with instantaneous,

cycle-by-cycle negative current limiting (OC_NEG_TH = -48µA).

trip the OC2_PEAK thresholds (105µA), the device returns to

normal switching and regulation through Hiccup soft-start.

The equivalent inductor peak current threshold for the

OC2_PEAK fault protection can be calculated by Equation 22:

R

–6

SETx

------------------

Peak Current Cycle-by-Cycle Limiting (OC1)

I

= 105  10



A

(EQ. 22)

OC2x

R

SENx

Each individual phase’s inductor peak current is protected with

cycle-by-cycle peak current limiting (OC1) without triggering

Hiccup or Latch-off shutdown of the IC. The controller

Constant Current Control (CC)

A dedicated constant average Current Control (CC) loop is

continuously compares the CSA output current sense signal,

implemented in the ISL78227 to control the input current to be

constant at overload conditions, which means constant input

power control under certain constant input voltage.

I

(calculated by Equation 11 on page 31) to an overcurrent

SENx

limiting threshold (OC1_TH = 80µA) in every cycle. When I

SENx

reaches 80µA, the respective phase’s LGx is turned off to stop

inductor current further ramping up. In such a way, peak current

cycle-by-cycle limiting is achieved.

As shown in Figure 3 on page 7, the V

IMON

represents the total

input average current and is sent to the error amplifier Gm2 input to

be compared with the internal CC reference V (1.6V). Gm2

REF_CC

The equivalent cycle-by-cycle peak inductor current limiting for

OC1 can be calculated using Equation 20:

output is driving the COMP voltage through a diode, D . Thus, the

CC

COMP voltage can be controlled by either Gm1 output or Gm2

R

–6

SETx

(EQ. 20)

------------------

output through D depending on load conditions.

I

= 80  10



A

CC

OC1x

R

SENx

At normal operation without overloading, V

IMON

is lower than the

V

(1.6V at default). Therefore, Gm2 output is HIGH and D is

REF_CC

reversely blocked and not forward conducting. In this case, the

CC

Negative Current Cycle-by-Cycle Limiting (OC_NEG)

Each individual phase’s inductor current is protected with

cycle-by-cycle negative current limiting (OC_NEG) without

triggering Hiccup or Latch-off shutdown of the IC. The controller

continuously compares the CSA output current sense signal,

COMP voltage is controlled by the voltage loop error amplifier Gm1’s

output to have the output voltage regulated.

At input average current overloading case, when V

IMON

reaches

V

(1.6V), Gm2 output falls, D is forward conducting, and

I

, (calculated by Equation 11 on page 31) to a negative

REF_CC

CC

SENx

Gm2 output overrides Gm1 output to drive COMP. In this way, the CC

loop overrides the voltage loop, meaning V is controlled to be

current limiting threshold (OC_NEG_TH = -48µA) in every cycle.

When I falls below -48µA, the respective phase’s UGx is

IMON

SENx

constant and input average constant current operation is achieved.

Under certain constant input voltage, input CC makes input power

constant for the boost converter. Compared to peak current limiting

schemes, the average constant current control is more accurate to

control the average current to be constant, which is beneficial for the

user to accurately control the maximum average power for the

converter to handle.

turned off to stop the inductor current further ramping down. In

such a way, negative current cycle-by-cycle limiting is achieved.

The equivalent negative inductor current-limiting level can be

calculated by Equation 21:

R

–6

SETx

------------------

I

= –48  10



A

(EQ. 21)

OCNEGx

R

SENx

The CC current threshold should be set lower than the OC1 peak

current threshold with margin. Generally, the OC1 peak current

threshold (per phase) is set 1.5 to 2 times higher than the CC

current threshold (here referred to per phase average current).

FN8808 Rev.5.00

Jul 13, 2018

Page 35 of 44

ISL78227

This matches with the physics of the power devices that normally

have higher transient peak current rating and lower average

current ratings. The OC1 provides protection against the transient

peak current. The CC controls the average current with slower

response, but with much more accurate control of the maximum

power the system has to handle at overloading conditions.

INTERNAL DIE OVER-TEMPERATURE PROTECTION

The ISL78227 PWM is disabled if the junction temperature

reaches +160°C (typical) while the internal LDO is alive to keep

PVCC/VCC biased (VCC connected to PVCC). A +15°C hysteresis

ensures that the device restarts with soft-start when the junction

temperature falls below +145°C (typical).

1. When fast changing overloading occurs, because V

has

IMON

, CC does not trip at the

Internal 5.2V LDO

a sensing delay of R

*C

IMON IMON

initial transient load current until it reaches the CC reference

of 1.6V. OC1 is triggered at the beginning to limit the inductor

peak current cycle-by-cycle.

The ISL78227 has an internal LDO with input at VIN and a fixed

5.2V/100mA output at PVCC. The internal LDO tolerates an input

supply range of VIN up to 55V (60V absolute maximum). A 10µF,

10V or higher X7R type of ceramic capacitor is recommended

between PVCC to GND. At low VIN operation when the internal

LDO is saturated, the dropout voltage from the VIN pin to the

PVCC pin is typically 0.3V under 80mA load at PVCC, as shown in

the “Electrical Specifications” table on page 9. This is one of the

constraints to estimate the required minimum VIN voltage.

2. After the delay of R

*C

, when V

reaches the CC

IMON

IMON IMON

reference of 1.6V, CC control starts to work and limit duty

cycles to reduce the inductor current and keep the sum of the

two phases’ inductor currents constant. The time constant of

the R is typically on the order of 10 times slower

*C

IMON IMON

than the voltage loop bandwidth so that the two loops do not

interfere with each other.

The output of this LDO is mainly used as the bias supply for the

gate drivers. With VCC connected to PVCC as in the typical

application, PVCC also supplies other internal circuitry. To provide

a quiet power rail to the internal analog circuitry, it is

recommended to place an RC filter between PVCC and VCC. A

minimum of 1µF ceramic capacitor from VCC to ground should

be used for noise decoupling purpose. Because PVCC is providing

noisy drive current, a small resistor (10Ω or smaller) between the

PVCC and VCC helps to prevent the noises from interfering from

PVCC to VCC.

CC loop is active at the beginning of soft-start.

From Equations 13 and 14 on page 31, the constant current

control current threshold level for the total 2-phase boost input

current can be calculated by Equation 23.

R

–6



1.6

SET







------------------

---------------

I

=

– 17  10



 8A

(EQ. 23)

INCC

R

IMON

SEN

Average Overcurrent Fault (OC_AVG) Protection

Figure 62 shows the internal LDO output voltage (PVCC)

regulation versus its output current. The PVCC drops to 4.5V

(typical) when the load is 195mA (typical) because of the LDO

current-limiting circuits. When the load current further increases,

the voltage drops further and finally enters current foldback

mode where the output current is clamped to 100mA (typical). At

the worst case when LDO output is shorted to ground, the LDO

output is clamped to 100mA.

The ISL78227 monitors the IMON pin voltage (which represents

the boost total input average current signal) to detect if the

Average Overcurrent (OC_AVG) fault occurs. As shown in Figure 3

on page 7, the comparator CMP_OCAVG compares V

to 2V

IMON

threshold to detect this fault. This fault detection is active at the

beginning of soft-start (t as shown in Figure 58 on page 29).

5

When V

IMON

is higher than 2V, the OC_AVG fault is triggered. The

ISL78227 responds with fault protection actions to shut down

the PWM switching and enters either Hiccup or Latch-off mode,

depending on HIC/LATCH pin configuration as described in

“Selectable Hiccup or Latch-Off Fault Response” on page 33 and

Table 3 on page 34.

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Under the selection of Hiccup response for the OC_AVG fault,

when the IMON voltage falls to lower than the 2V threshold, the

device returns to normal switching through Hiccup soft-start.

From Equations 13 and 14 on page 31, the OC_AVG fault’s

current threshold level for the total 2-phase boost input current

can be calculated using Equation 24.

0.00

0.05

0.10

IOUT_PVCC (A)

0.15

0.20

0.25

R

–6



2

SET







------------------

---------------

I

=

– 17  10



 8A

(EQ. 24)

INOCAVG

R

IMON

SEN

FIGURE 62. INTERNAL LDO OUTPUT VOLTAGE vs LOAD

Based on the junction to ambient thermal resistance, R , of the

JA

Because the Constant Current Loop uses the same IMON signal

and has a lower threshold (1.6V) than the OC_AVG threshold (2V),

the OC_AVG can hardly be tripped. The CC loop limits the IMON

signal around 1.6V, which is below 2V. Generally, the OC_AVG

functions as a worst-case backup protection.

package, the maximum junction temperature should be kept below

+125°C. However, the power losses at the LDO need to be

considered, especially when the gate drivers are driving external

MOSFETs with large gate charges. At high V , the LDO has

IN

significant power dissipation that may raise the junction

temperature where the thermal shutdown occurs.

FN8808 Rev.5.00

Jul 13, 2018

Page 36 of 44

ISL78227

With an external PNP transistor as shown in Figure 63, the power

dissipation of the internal LDO can be moved from the ISL78227

Equation 1 on page 24. With the required input and output voltage,

duty cycle D can be calculated by Equation 25:

V

to the external transistor. Set R to 68Ω so that the LDO delivers

S

IN

---------------

D = 1 –

(EQ. 25)

about 10mA when the external transistor begins to turn on. The

external circuit increases the minimum input voltage to

approximately 6.5V.

V

OUT

where D is the on-duty of the boost low-side power transistor.

Under this CCM condition, the inductor peak-to-peak ripple

current of each phase can be calculated using Equation 26:

VIN

R

S

VIN

L

(EQ. 26)

----------

= D  T 

I

LP-P

where T is the switching cycle 1/f

inductor’s inductance.

and L is each phase

SW

VIN

From the previous equations, the inductor value is determined

using Equation 27:

PVCC

ISL78227

V





IN

--------------- --------------------------------

(EQ. 27)

L = 1 –







V

I

 f

LP-P SW





OUT

FIGURE 63. SUPPLEMENTING LDO CURRENT

Use Equation 27 to calculate L, where values of V , V

IN OUT

and

I

are based on the considerations described in following:

L(P-P)

Application Information

• One method is to select the minimum input voltage and the

maximum output voltage under long term operation as the

conditions to select the inductor. In this case, the inductor DC

current is the largest.

There are several ways to define the external components and

parameters of boost regulators. This section shows one example

of how to decide the parameters of the external components

based on the typical application schematics as shown in Figure 4

on page 8. In the actual application, the parameters may need to

be adjusted and additional components may be needed for the

specific applications regarding noise, physical sizes, thermal,

testing, and/or other requirements.

• The general rule to select the inductor is to have its ripple

current I

around 30% to 50% of maximum DC current.

L(P-P)

The individual maximum DC inductor current for the 2-phase

boost converter can be calculated using Equation 28, where

P

is the maximum DC output power, and EFF is the

OUTmax

estimated efficiency:

Output Voltage Setting

P

OUTmax

The Output Voltage (V

) of the regulator can be programmed

to FB and FB

OUT

-------------------------------------------

(EQ. 28)

I

=

Lmax

V

 EFF  2

by an external resistor divider connecting from V

OUT

INmin

to GND as shown in Figure 4 on page 8. Use Equation 2 on

page 25 to calculate the desired V , where V can be either

VREF_1.6V or VREF_TRK, whichever is lower. In the actual

application, the resistor value should be decided by considering

the quiescent current requirement and loop response. Typically,

Using Equation 27 with the two conditions listed above, a

reasonable starting point for the minimum inductor value can be

estimated from Equation 29, where K is typically selected as

OUT

REF

30%.

2

V

 EFF  2









between 4.7kΩ to 20kΩ is used for the R

.

INmin

FB1

-------------------------- --------------------------------------------------

(EQ. 29)

L

=

1 –





min

V

P

 K  f

OUTmax SW



OUTmax

Switching Frequency

Increasing the value of the inductor reduces the ripple current

and therefore, the ripple voltage. However, the large inductance

value may reduce the converter’s response time to a load

transient. This also reduces the current sense ramp signal and

may cause a noise sensitivity issue.

Switching frequency is determined by requirements of transient

response time, solution size, EMC/EMI, power dissipation and

efficiency, ripple noise level, input, and output voltage range.

Higher frequency may improve the transient response and help

to reduce the solution size. However, this may increase the

switching losses and EMC/EMI concerns. Thus, a balance of

these parameters is needed when deciding the switching

frequency.

The peak current at maximum load condition must be lower than

the saturation current rating of the inductor with enough margin.

In the actual design, the largest peak current may be observed at

some transient conditions like the start-up or heavy load

transient. Therefore, the inductor’s size needs to be determined

with the consideration of these conditions. To avoid exceeding

the inductor’s saturation rating, OC1 peak current limiting (refer

to “Peak Current Cycle-by-Cycle Limiting (OC1)” on page 35) should

be selected below the inductor’s saturation current rating.

When the switching frequency f

is decided, the frequency

can be determined by Equation 6 on

SW

setting resistor R

page 27.

FSYNC

Input Inductor Selection

While the boost converter is operating in steady state Continuous

Conduction Mode (CCM), the output voltage is determined by

FN8808 Rev.5.00

Jul 13, 2018

Page 37 of 44

ISL78227

minimum V threshold is higher than 1.2V, but does not exceed

GS

2.5V, in order to prevent false turn-on by noise spikes due to high

Output Capacitor

To filter the inductor current ripples and to have sufficient

transient response, output capacitors are required. A

combination of electrolytic and ceramic capacitors is normally

used.

dv/dt during phase node switching and to maintain low r

DS(ON)

under limitation of maximum gate drive voltage, which is 5.2V

(typical) for low-side MOSFET and 4.5V (typical) due to diode drop

of boot diode for high-side MOSFET.

The ceramic capacitors filter the high frequency spikes of the

main switching devices. In layout, these output ceramic

capacitors must be placed as close as possible to the main

switching devices to maintain the smallest switching loop in

layout. To maintain capacitance over the biased voltage and

temperature range, good quality capacitors such as X7R or X5R

are recommended.

Bootstrap Capacitor

The power required for high-side MOSFET drive is provided by the

boot capacitor connected between BOOT and PH pins. The

bootstrap capacitor can be chosen using Equation 32:

Q

gate

(EQ. 32)

-----------------------

C



BOOT

dV

BOOT

The electrolytic capacitors normally handle the load transient

and output ripples. The boost output ripples are mainly

dominated by the load current and output capacitance volume.

where Q

is the total gate charge of the high-side MOSFET and

gate

dV

is the maximum droop voltage across the bootstrap

BOOT

capacitor while turning on the high-side MOSFET.

For boost converter, the maximum output voltage ripple can be

estimated using Equation 30, where I

is the load current

OUTmax

at output, C is the total capacitance at output, and D

Though the maximum charging voltage across the bootstrap

capacitor is PVCC minus the bootstrap diode drop (~4.5V), large

excursions below GND by PH node requires at least 10V rating for

this ceramic capacitor. To keep enough capacitance over the

biased voltage and temperature range, a good quality capacitor

such as X7R or X5R is recommended.

is the

MIN

minimum duty cycle at VIN

and VOUT

.

max

min

I

 1 – D



OUTmax

MIN

(EQ. 30)

----------------------------------------------------------

V

=

OUTripple

C  2  f

SW

For 2-phase boost converter, the RMS current going through the

output current can be calculated by Equation 30 for D > 0.5,

RESISTOR ON BOOTSTRAP CIRCUIT

In the actual application, sometimes a large ringing noise at the

PH node and the BOOT node occurs. This noise is caused by high

dv/dt phase node switching, parasitic PH node capacitance due

to PCB routing, and the parasitic inductance. To reduce this

noise, a resistor can be added between the BOOT pin and the

bootstrap capacitor. A large resistor value reduces the ringing

noise at PH node, but limits the charging of the bootstrap

capacitor during the low-side MOSFET on-time, especially when

the controller is operating at very low duty cycle. Also, large

resistance causes a voltage dip at BOOT each time the high-side

driver turns on the high-side MOSFET. Make sure this voltage dip

does not trigger the high-side BOOT to PH UVLO threshold 3V

where I is per phase inductor DC current. For D < 0.5, time

L

domain simulation is recommended to get the accurate calculation

of the input capacitor RMS current.

I

= I  1 – D  2D – 1

L

CoutRMS

(EQ. 31)

It is recommended to use multiple capacitors in parallel to

handle this output RMS current.

Input Capacitor

Depending upon the system input power rail conditions, the

aluminum electrolytic type capacitor is normally used to provide

a stable input voltage. The input capacitor should be able to

handle the RMS current from the switching power devices. Refer

to Equation 5 and Figure 53 on page 27 to estimate the RMS

current the input capacitors need to handle.

(typical), especially when a MOSFET with large Q is used.

g

Loop Compensation Design

The ISL78227 uses constant frequency peak current mode

control architecture with a Gm amp as the error amplifier.

Figures 64 and 65 on page 39 show the conceptual schematics

and control block diagram, respectively.

Ceramic capacitors must be placed near the VIN and PGND pin of

the IC. Multiple ceramic capacitors including 1µF and 0.1µF are

recommended. Place these capacitors as close as possible to the IC.

Power MOSFET

The external MOSFETs driven by the ISL78227 controller must be

carefully selected to optimize the design of the synchronous

boost regulator.

The MOSFET's BV

rating must have enough voltage margin

DSS

against the maximum boost output voltage plus the phase node

voltage transient spikes during switching.

As the UG and LG gate drivers are 5V output, the MOSFET V

need to be in this range.

GS

The MOSFET should have low Total Gate Charge (Q ), low

g

ON-resistance (r

) at VGS = 4.5V, and small gate resistance

DS(ON)

(R <1.5Ω is recommended). It is recommended that the

g

FN8808 Rev.5.00

Jul 13, 2018

Page 38 of 44

ISL78227

V_OUT

SLOPE

V_IN

R_SET

R_SEN

+

Gm

-

R₁

C₁

Gvcvo(s)

RFB2

RFB1

L

+

V_OUT

FB

Vfb

COMP

+

Vc

-

Gm

-

Resr

C_OUT

ROEA

CCP2

V_REF

RCP

R_LOAD

H_e1(s)

CCP1

H_e2(s)

FIGURE 64. CONCEPTUAL BLOCK DIAGRAM OF PEAK CURRENT MODE CONTROLLED BOOST REGULATOR

where:

CURRENT MODE

ERROR AMP

CONTROL +POWER STAGE

+

Vfb

Vc

V_OUT

• N is the number of phases, R is the output capacitor’s

ESR

V_REF

H_e2(s)

Gvcvo(s)

Equivalent Series Resistance (ESR) of the total capacitors,

is the load resistance, L is the equivalent inductance

-

R

LOAD

eq

Vfb

for multiphase boost with N number of phases, and L is each

phase’s inductor’s inductance.

H_e₁(s)

L

N

---

L

=

eq

FIGURE 65. CONCEPTUAL CONTROL BLOCK DIAGRAM

TRANSFER FUNCTION FROM V TO V

OUT

C

• K

ISEN

is the current sense gain as shown in Equation 34,

and R are per-phase current sense resistors

Transfer function from error amplifier output V to output voltage

C

where R

SENx

SETx

and setting resistors described in “Current Sense for Individual

V

G

(s) can be expressed as Equation 33.

OUT vcvo

Phase - I

” on page 31.

SENX

R

s















-----------

---------------

1 +

 1 –



 6500



(EQ. 34)

SENx

N  R

esr

RHZ

(EQ. 33)

------------------------------------

---------------------------------------------------------------------------------------------

K

=

G

s = K



ISEN

vcvo

DC

2

s

SETx







 

---------------

------------------

------

1 +

 1 +

+







 

 PS

Q

 



p

n

• Se/Sn is the gain of the selected compensating slope over the

sensed inductor current up-ramp. It can be calculated in

The expressions of the poles and zeros are listed below:

Equation 35, where K

is the gain of selected

SLOPE

R

 1 – D

compensating slope over the sensed IL down slope (refer to

Equation 15 on page 32).

LOAD

------------------------------------------

=

K

DC

2  K

ISEN

S

V

OUT









e

(EQ. 35)

------

---------------

= K



– 1





2

SLOPE

S

n

V

R

 1 – D

IN

LOAD

---------------------------------------------



=

RHZ

L

eq

Equation 33 shows that the system is mainly a single order

system plus a Right Half Zero (RHZ), which commonly exists for

1

---------------------------------

=

esr

C

 R

OUT

esr

boost converters. The main pole ω

output capacitance and the ESR zero ω

is determined by load and

is the same as the

pPS

ESR

2

----------------------------------------

OUT



=

buck converter.

pPS

C

 R

LOAD

Because the ω

converter crossover frequency is set 1/5 to 1/3 of the ω

frequency.

changes with load, typically the boost

RHZ

1

--------------------------------------------------------------------

RHZ

Q

=

p

S

e

------

  1 – D 

+ 0.5 – D

S

n

The double pole ω is at half of the f

SW

and has minimum

n

effects at crossover frequency for most of the cases when the

crossover frequency is fairly low.



=   f

SW

n

FN8808 Rev.5.00

Jul 13, 2018

Page 39 of 44

ISL78227

The total transfer function with compensation network and gain

stage is expressed as:

COMPENSATOR DESIGN

Generally, a simple Type-2 compensator can be used to stabilize

the system. In the actual application, however, an extra phase

margin is provided by a Type-3 compensator.

G

s = G

s  H s  H s

vcvo e1 e2

(EQ. 39)

open

Use f = ω/2π to convert the pole and zero expressions to

V_OUT

frequency domain, and from Equations 33, 38, and 39, select

the compensator’s pole and zero locations.

In general, as described earlier, a Type-2 compensation is

enough. Typically, the crossover frequency is set 1/5 to 1/3 of

R₁

R_FB2

the ω

frequency. As a general rule, set the compensator

RHZ

C₁

ω

/2π at the very low end frequency; set ω /2π at 1/5 of the

p2 z2

Vc

FB

V_OUT

crossover frequency, and set ω /2π at the ESR zero or the RHZ

COMP

+

p3

Gm

-

frequency ω

RHZ

/2π, whichever is lower.

V_REF

R_OEA

R_FB1

R_CP

V

Input Filter

CC

C_CP2

To provide a quiet power rail to the internal analog circuitry, it is

recommended to place an RC filter between PVCC and VCC. A

10Ω resistor between PVCC and VCC and at least 1µF ceramic

capacitor from VCC to GND are recommended.

C_CP1

H_e1(s)

H_e2(s)

FIGURE 66. TYPE-3 COMPENSATOR

Current Sense Circuit

The transfer function at the error amplifier and its compensation

network can be expressed as Equation 36.

To set the current sense resistor, the voltage across the current

sense resistor should be limited to within ±0.3V. In a typical

application, it is recommended to set the voltage across the

current sense resistor in range around 30mV to 100mV for the

typical load current condition.

V

C

----------

s =

= g  Z

=

(EQ. 36)

e2

g

m

COMP

V

FB

1 + sR

C

R

OEA

CP

CP1

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

m

2

1 + sR

C

+ R

C

+ C

 + C

CP2

C

R

S

CP CP1

CP1

OEA

CP2

CP1

CP

Configuration to Support Single Phase

Boost

The IC can be configured to support single phase operation either

using Phase 1 or Phase 2. The configurations needed to use

Phase 1 for single phase operation are listed below (to use

Phase 2 for single phase operation, change the corresponding

phase number to the other phase number):

OEA

If R

>>R , C

>>C

, and R

= infinite, the equation

OEA

CP CP1

CP2 OEA

can be simplified as shown in Equation 37:

s

---------

1 +

1 + s  R

 C



CP

CP1

 C 

CP2

1

z2

---------------------------------------------------------------------------------



m

------ -------------------

H

s = g

=



e2

s  C

 1 + s  R

s

CP1

CP

---------

1 +



p2

(EQ. 37)

• BOOT2 = GND (UG2 disabled)

• ISEN2P = ISEN2N = GND

• PH2 = GND

where:

g

m

--------------



=

p2

z2

p3

C

CP1

The extra notes are listed below with upper single phase

configurations:

1

 C

-------------------------------

=

R

CP

CP1

• LG2 can be left floating. LG2 has PWM signals which are fine

with no external MOSFET to drive.

1

-------------------------------

R

 C

CP2

CP

• IMON pin output current signal has only Phase 1’s inductor

current sensed signal. Equation 12, which calculates the IMON

output current, is expressed as Equation 40.

If Type-3 compensation is needed, the transfer function at the

feedback resistor network is:

s

---------

1 +

I

 R

SEN1

R



L1

FB1

+ R

z1

–6

----------------------------------- -------------------

H

s =



-------------------------------

IMON =

 0.125 + 17  10

(EQ. 38)

e1

R

s

R

FB1

FB2

1 +

SET1

----------

(EQ. 40)



p1

The Constant Current Loop works on the same principle.

where:

1

---------------------------------------------

1



=

z1

C

 R

+ R 

FB2 1

1

----------------------------------------------------------------------------------------------------------------



=

p1

R

 R

+ R

 R + R

 R

FB1 1

FB2

FB1

FB2

1

----------------------------------------------------------------------------------------------------



C

1

R

+ R

FB1

FB2

FN8808 Rev.5.00

Jul 13, 2018

Page 40 of 44

ISL78227

recommended. Assuming the R

SENx

is placed in the top layer

Layout Considerations

For DC/DC converter design, the PCB layout is very important to

ensure the desired performance.

(red), route one current sense connection from the middle of

one R pad in the top layer under the resistor (red trace).

SENx

For the other current-sensing trace, from the middle of the

other pad on R in the top layer, after a short distance, via

SENx

1. Place input ceramic capacitors as close as possible to the IC's

VIN and PGND/SGND pins.

down to the second layer and route this trace right under the

top layer current sense trace.

2. Place the output ceramic capacitors as close as possible to

the power MOSFETs. Keep this loop (output ceramic capacitor

and MOSFETs for each phase) as small as possible to reduce

voltage spikes induced by the trace parasitic inductances

when MOSFETs switching ON and OFF.

13. Keep the current-sensing traces far from the noisy traces such

as gate driving traces (LGx, UGx, and PHx), phase nodes in

power stage, BOOTx signals, output switching pulse currents,

driving bias traces, and input inductor ripple current signals,

etc.

3. Place the output aluminum capacitors close to the power

MOSFETs.

4. Keep the phase node copper area small, but large enough to

handle the load current.

5. Place the input aluminum and some ceramic capacitors close

to the input inductors and power MOSFETs.

6. Place multiple vias under the bottom pad of the IC. Connect

the bottom pad to the ground copper plane with as large an

area as possible in multiple layers to effectively reduce the

thermal impedance. Figure 67 shows the layout example for

vias in the IC bottom pad.

FIGURE 68. RECOMMENDED LAYOUT PATTERN FOR CURRENT

SENSE TRACES REGULATOR

FIGURE 67. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE

IC BOTTOM PAD

7. Place the 10µF decoupling ceramic capacitor at the PVCC pin

and as close as possible to the IC. Put multiple vias close to

the ground pad of this capacitor.

8. Place the 1µF decoupling ceramic capacitor at the VCC pin

and as close as possible to the IC. Put multiple vias close to

the ground pad of this capacitor.

9. Keep the bootstrap capacitors as close as possible to the IC.

10. Keep the driver traces as short as possible and with relatively

large width (25 mil to 40 mil is recommended), and avoid

using via or minimal number of vias in the driver path to

achieve the lowest impedance.

11. Place the current sense setting resistors and the filter

capacitors (shown as R

, R

, and C in

SETxB BIASxB

ISENx

Figure 60 on page 31) as close as possible to the IC. Keep

each pair of the traces close to each other to avoid undesired

switching noise injections.

12. The current-sensing traces must be laid out very carefully

because they carry tiny signals with only tens of mV.

For the current-sensing traces close to the power sense

resistor (R

), the layout pattern shown in Figure 68 is

SENx

FN8808 Rev.5.00

Jul 13, 2018

Page 41 of 44

ISL78227

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure that you have the latest revision.

DATE

REVISION

FN8808.5

CHANGE

Jul 13, 2018

Updated the ordering information table by adding tape and reel column, adding tape and reel parts to

table, and updating Note 1.

Added two lines to the “Absolute Maximum Ratings” on page 9.

Changed “If the DE/PHDRP pin = GND” to “If the DE/PHDRP pin = VCC” in “Operation Initialization and

Soft-Start” on page 29.

Removed the About Intersil section.

Sep 18, 2017

Feb 6, 2017

FN8808.4

FN8808.3

Fixed Equation 7 on page 30.

Applied new header/footer.

-Added Related Literature on page 1.

-Added third sentence in the VIN pin description on page 5.

-Figures 26 and 28 on page 19, changed "D" to "D_TRACK" in the title to avoid confusion.

-Figure 44 on page 22, swapped VPORL_PVCC and VPORL_VCC data labels for the 2 curves.

-Added “while the adaptive dead time control is still functioning at the same time” to the first sentence in

“Programmable Adaptive Dead Time Control” on page 24.

-Added “for three consecutive switching cycles” to the first sentence in “Peak Overcurrent Fault

(OC2_PEAK) Protection” on page 35.

-Added the last paragraph in “Average Overcurrent Fault (OC_AVG) Protection” on page 36.

-Updated Figures 64, 65, and 66.

-Updated Equation 33 on page 39, and expressions K , wpPS, Q , and w .

DC

p

n

-Updated Equation 34 on page 39.

-Added section “Configuration to Support Single Phase Boost” on page 40.

Feb 24, 2016

FN8808.2

-Figure 16 on page 17:

changed the label "IL1" to "IL2" and in figure title, changed "PHASE1" to "PHASE 2".

-Updated POD L32.5x5H to most recent revision with change as follows:

Detail "X" - Added dimple dimension 0.10 ±0.05 back on (left side).

Detail "X" - Changed the tolerance back (in the seating plane box) to 0.08.

Bottom View - Removed 0.15 ±0.10 this is a duplicate dim with detail A.

Bottom View - Extended the dimension line to the bottom of the exposed pad

Dec 24, 2015

Nov 23, 2015

FN8808.1

FN8808.0

Updated expression Qp and Equation 35 on page 39.

Removed text after Equation 35 on page 39 and before paragraph that begins with “Equation 33”.

Initial release

FN8808 Rev.5.00

Jul 13, 2018

Page 42 of 44

ISL78227

For the most recent package outline drawing, see L32.5x5H.

Package Outline Drawing

L32.5x5H

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETABLE FLANK)

Rev 2, 1/16

2X

0.10 C A

SEE DETAIL “A”

3.3

A

5.00

4.75

CAB

0.10 M

PIN 1

INDEX AREA

5

4X 0.42 ±0.18

2X

PIN #1 ID

R0.20

0.45

N

0.10 C B

N

1

2

3

1

2

3

0.50

DIAMETER

3.3

4.75 5.00

0.10

M C AB

0.10 C B

(0.45)

0.25 ±0.05

2X

B

0.50

0.40 ±0.10

M

0.10

0.05 M

CAB

C

0.10 C

2X

A

(0.45)

TOP VIEW

BOTTOM VIEW

SEE DETAIL “X”

0.85 ±0.05

0.50

0.15 ±0.10

SIDE VIEW

0.15 ±0.05

0.25 ±0.05

0.40 ±0.10

0 - 12

0.10

C A B

M

4

C

0.10 ±0.05

SEATING PLANE

0.08 C

DETAIL “A”

0.00 MIN

0.05 MAX

DETAIL “X”

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for reference only.

(4.80)Sq

2. Dimensioning and tolerancing conform to ASMEY 14.5m-1994.

28X (0.50)

32X (0.25)

(3.30)Sq

3.

4.

Unless otherwise specified, tolerance: Decimal ± 0.05

Dimension applies to the plated terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

5.

32X (0.60)

TYPICAL RECOMMENDED LAND PATTERN

6. Reference document: JEDEC MO220

FN8808 Rev.5.00

Jul 13, 2018

Page 43 of 44

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	ISL78227ARZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	2-Phase Boost Controller with Integrated Drivers; WFQFN32; Temp Range: -40° to 125°C 开关
文件：	总44页 (文件大小：2384K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL78227ARZ-T [RENESAS]

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