ICL3245ECVZ [RENESAS]
±15kV ESD Protected, +3V to +5.5V, 1mA, 1Mbps, RS-232 Transceivers with Enhanced Automatic Powerdown; SOIC28, SSOP28, TSSOP28; Temp Range: See Datasheet;
| 型号： | ICL3245ECVZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ±15kV ESD Protected, +3V to +5.5V, 1mA, 1Mbps, RS-232 Transceivers with Enhanced Automatic Powerdown; SOIC28, SSOP28, TSSOP28; Temp Range: See Datasheet 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总22页 (文件大小：997K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ICL3225E, ICL3227E, ICL3245E
±15kV ESD Protected, +3V to +5.5V, 1µA, 1Mbps, RS-232 Transceivers with
Enhanced Automatic Powerdown
FN4900
Rev 12.00
December 12, 2016
The Intersil ICL3225E, ICL3227E, and ICL3245E devices are
Features
3.0V to 5.5V powered RS-232 transmitters/receivers which
• Pb-free (RoHS compliant)
meet ElA/TIA-232 and V.28/V.24 specifications, even at
= 3.0V. Additionally, they provide ±15kV ESD protection
V
• ESD protection for RS-232 I/O pins to ±15kV (IEC61000)
• Manual and enhanced automatic powerdown features
CC
(IEC61000-4-2 Air Gap and Human Body Model) on transmitter
outputs and receiver inputs (RS-232 pins). Targeted
applications are PDAs, Palmtops, and notebook and laptop
computers where the low operational, and even lower standby,
power consumption is critical. Efficient on-chip charge pumps,
coupled with manual and enhanced automatic powerdown
functions, reduce the standby supply current to a 1µA trickle.
Small footprint packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 1Mbps are guaranteed at worst case load
conditions. This family is fully compatible with 3.3V only
systems, mixed 3.3V and 5.0V systems, and 5.0V only
systems.
• Drop in replacements for MAX3225E, MAX3227E,
MAX3245E
• RS-232 compatible with V = 2.7V
CC
• Meets EIA/TIA-232 and V.28/V.24 specifications at 3V
• Latch-up free
• On-chip voltage converters require only four external 0.1µF
capacitors
• Guaranteed mouse driveability (ICL3245E)
• “Ready to Transmit” indicator output (ICL3225E/ICL3227E)
• Receiver hysteresis for improved noise immunity
The ICL3245E is a 3-driver, 5-receiver device that provides a
complete serial port suitable for laptop or notebook
computers. It also includes a noninverting always-active
receiver for “wake-up” capability.
• Guaranteed minimum data rate . . . . . . . . . . . . . . . . . 1Mbps
• Low skew at transmitter/receiver input trip points . . . . . . 10ns
• Guaranteed minimum slew rate . . . . . . . . . . . . . . . . . 24V/µs
• Wide power supply range . . . . . . . . . . . . single +3V to +5.5V
• Low supply current in powerdown state . . . . . . . . . . . . . . 1µA
These devices, feature an enhanced automatic powerdown
function, which powers down the on-chip power supply and
driver circuits. This occurs when all receiver and transmitter
inputs detect no signal transitions for a period of 30s. These
devices power back up automatically, whenever they sense a
transition on any transmitter or receiver input.
Applications
• Any system requiring RS-232 communication ports
- Battery powered, hand-held, and portable equipment
- Laptop computers, notebooks, palmtops
- Modems, printers, and other peripherals
- Digital cameras
Table 1 summarizes the features of the device represented by
this datasheet, while Application Note AN9863 summarizes
the features of each device comprising the ICL32xxE 3V family.
Related Literature
• For a full list of related documents, visit our website
- ICL3225E, ICL3227E, and ICL3245E product pages
- Cellular/mobile phones
TABLE 1. SUMMARY OF FEATURES
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
NO. OF NO. OF NO. OF MONITOR
DATA RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWER-DOWN?
PART NUMBER
ICL3225E
Tx.
Rx.
Rx. (R
)
OUTB
2
2
0
1000
1000
1000
No
No
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
ICL3227E
1
1
0
1
ICL3245E
3
5
FN4900 Rev 12.00
December 12, 2016
Page 1 of 22
ICL3225E, ICL3227E, ICL3245E
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG. DWG. #
M20.209
ICL3225ECAZ
ICL3225ECAZ
0 to +70
0 to +70
20 Ld SSOP
ICL3225ECPZ (No longer available, recommended 3225ECPZ
replacement: ICL3225ECAZ) (Note 3)
20 Ld PDIP
E20.3
ICL3225EIAZ
ICL3227ECAZA
ICL3227EIAZA
ICL3245ECAZ
ICL3225EIAZ
3227ECAZ
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
20 Ld SSOP
16 Ld SSOP
16 Ld SSOP
28 Ld SSOP
28 Ld SOIC
M20.209
M16.209
M16.209
M28.209
M28.3
3227EIAZ
ICL3245ECAZ
ICL3245ECBZ (No longer available, recommended ICL3245ECBZ
replacement: ICL3245EIAZ)
ICL3245ECVZ (No longer available, recommended ICL3245ECVZ
replacement: ICL3245EIAZ)
0 to +70
28 Ld TSSOP
28 Ld SSOP
M28.173
M28.209
ICL3245EIAZ
NOTES:
ICL3245EIAZ
-40 to +85
1. Add “-T” suffix for 1k unit tape and reel option. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
4. For Moisture Sensitivity Level (MSL), see product information page for ICL3225E, ICL3227E, ICL3245E. For more information on MSL, see tech brief
TB363.
Pin Configurations
ICL3225E (PDIP, SSOP)
TOP VIEW
ICL3227E (SSOP)
TOP VIEW
READY
C1+
V+
1
20 FORCEOFF
19 V
READY
C1+
V+
1
2
3
4
5
6
7
8
16 FORCEOFF
15 V
2
3
CC
CC
18 GND
17 T1
14 GND
13 T1
C1-
4
C1-
OUT
OUT
C2+
C2-
5
16 R1
15 R1
C2+
C2-
12 FORCEON
IN
6
11 T1
IN
OUT
V-
7
14 FORCEON
V-
10 INVALID
T2
8
13 T1
IN
R1
IN
9 R1
OUT
OUT
R2
IN
9
12
T2
IN
11 INVALID
10
R2
OUT
FN4900 Rev 12.00
December 12, 2016
Page 2 of 22
ICL3225E, ICL3227E, ICL3245E
Pin Configurations (Continued)
ICL3245E (SOIC, SSOP, TSSOP)
TOP VIEW
C2+
C2-
V-
1
2
28 C1+
27 V+
3
26 V
CC
25 GND
R1
R2
R3
R4
R5
4
IN
IN
IN
IN
IN
5
24 C1-
6
23 FORCEON
22 FORCEOFF
21 INVALID
7
8
T1
9
20
R2
OUT
OUT
OUT
OUTB
OUT
OUT
OUT
OUT
OUT
10
11
12
13
14
19 R1
18 R2
17 R3
16 R4
15 R5
T2
T3
T3
T2
T1
IN
IN
IN
Pin Descriptions
PIN
FUNCTION
V
System power supply input (3.0V to 5.5V).
CC
V+
V-
Internally generated positive transmitter supply (+5.5V).
Internally generated negative transmitter supply (-5.5V).
Ground connection.
GND
C1+
C1-
C2+
C2-
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Inputs.
T
IN
T
±15kV ESD protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs.
OUT
R
IN
R
OUT
R
TTL/CMOS level, noninverting, always enabled receiver outputs.
OUTB
INVALID
READY
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active high output that indicates when the ICL32xxE is ready to transmit (i.e., V- ≤ -4V).
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2 on
page 10).
FORCEON Active high input to override automatic powerdown circuitry, thereby keeping transmitters active. (FORCEOFF must be high).
FN4900 Rev 12.00
December 12, 2016
Page 3 of 22
ICL3225E, ICL3227E, ICL3245E
Typical Operating Circuits
+3.3V
+
0.1µF
19
2
+
4
C
0.1µF
C1+
V
3
1
CC
C
0.1µF
3
+
V+
V-
C1-
5
C
0.1µF
2
C2+
+
7
C
4
0.1µF
6
C2-
+
T
T
1
2
13
17
8
T1
T2
T1
T2
IN
OUT
OUT
12
15
IN
TTL/CMOS
RS-232
16
LOGIC LEVELS
LEVELS
R1
R2
R1
R2
OUT
IN
IN
5kΩ
5kΩ
R
1
10
9
OUT
R
2
1
20
11
READY
V
FORCEOFF
INVALID
CC
14
TO POWER
CONTROL LOGIC
FORCEON
GND
18
FIGURE 1. ICL3225E
+3.3V
+
15
0.1µF
2
+
C
1
0.1µF
3
C1+
V
C
0.1µF
CC
3
+
V+
V-
4
C1-
5
C
2
C2+
+
7
0.1µF
C
4
0.1µF
6
C2-
+
T
1
11
9
13
T1
T1
OUT
IN
TTL/CMOS
RS-232
LOGIC LEVELS
8
LEVELS
R1
R1
IN
OUT
5kΩ
R
1
1
READY
16
10
V
CC
FORCEOFF
INVALID
12
TO POWER
CONTROL LOGIC
FORCEON
GND
14
FIGURE 2. ICL3227E
FN4900 Rev 12.00
December 12, 2016
Page 4 of 22
ICL3225E, ICL3227E, ICL3245E
Typical Operating Circuits(Continued)
+3.3V
+
26
0.1µF
28
27
C
C1+
1
V
CC
C
0.1µF
3
+
+
V+
V-
0.1µF
24
1
C1-
C
2
C2+
3
9
+
C
4
0.1µF
2
0.1µF
C2-
+
T
T
T
1
2
3
14
T1
T1
IN
OUT
13
12
20
10
11
RS-232
LEVELS
T2
T3
T2
T3
IN
IN
OUT
OUT
R2
OUTB
TTL/CMOS
LOGIC LEVELS
19
18
4
5
R1
R1
R2
OUT
OUT
IN
R
1
2
5kΩ
5kΩ
R2
IN
R
17
16
6
7
RS-232
LEVELS
R3
R4
R3
R4
OUT
OUT
IN
R
R
5kΩ
3
4
IN
5kΩ
5kΩ
15
23
8
R5
R5
OUT
IN
R
5
FORCEON
22
21
V
CC
FORCEOFF
TO POWER
CONTROL LOGIC
GND
25
INVALID
FIGURE 3. ICL3245E
FN4900 Rev 12.00
December 12, 2016
Page 5 of 22
ICL3225E, ICL3227E, ICL3245E
Absolute Maximum Ratings
Thermal Information
V
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 5)
JA (°C/W)
CC
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 Ld SSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 Ld SSOP and TSSOP Packages. . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile (SOIC, SSOP, TSSOP). . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
80
75
145
135
100
T
, FORCEOFF, FORCEON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
IN
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
T
OUT
R
, INVALID, READY . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
OUT CC
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32xxEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICL32xxEI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test conditions: V = 3V to 5.5V, C - C = 0.1µF; unless otherwise specified.
CC
1
4
Typicals are at T = +25°C
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
-
TYP
1.0
MAX
10
UNIT
µA
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All R open, FORCEON = GND, FORCEOFF = V
IN
+25
CC
Supply Current, Powerdown
FORCEOFF = GND
+25
+25
-
-
1.0
0.3
10
µA
Supply Current,
All outputs unloaded, FORCEON = FORCEOFF = V
CC
1.0
mA
Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
Input Logic Threshold High
T
T
, FORCEON, FORCEOFF
, FORCEON, FORCEOFF
Full
Full
Full
Full
Full
Full
Full
-
-
0.8
V
V
IN
V
V
= 3.3V
= 5.0V
2.0
-
-
IN
CC
2.4
-
-
±1.00
±10
0.4
-
V
CC
Input Leakage Current
Output Leakage Current
Output Voltage Low
Output Voltage High
RECEIVER INPUTS
T
, FORCEON, FORCEOFF
-
-
-
±0.01
±0.05
-
µA
µA
V
IN
FORCEOFF = GND, ICL3245E only
I
= 1.6mA
= -1.0mA
OUT
OUT
I
V
- 0.6
V
- 0.1
V
CC
CC
Input Voltage Range
Input Threshold Low
Full
+25
+25
+25
+25
+25
+25
-25
-
25
V
V
V
V
V
V
= 3.3V
= 5.0V
= 3.3V
= 5.0V
0.6
1.2
1.5
1.5
1.8
0.5
5
-
-
CC
CC
CC
CC
0.8
V
Input Threshold High
-
-
2.4
2.4
-
V
V
Input Hysteresis
Input Resistance
-
V
3
7
kΩ
FN4900 Rev 12.00
December 12, 2016
Page 6 of 22
ICL3225E, ICL3227E, ICL3245E
Electrical Specifications Test conditions: V = 3V to 5.5V, C - C = 0.1µF; unless otherwise specified.
CC
1
4
Typicals are at T = +25°C (Continued)
A
TEMP
(°C)
PARAMETER
TRANSMITTER OUTPUTS
Output Voltage Swing
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All transmitter outputs loaded with 3kΩ to Ground
Full
Full
Full
Full
±5.0
±5.4
10M
±35
-
-
V
Ω
Output Resistance
V
= V+ = V- = 0V, transmitter output = ±2V
300
-
CC
Output Short-Circuit Current
Output Leakage Current
-
-
±60
±25
mA
µA
V
= ±12V, V = 0V or 3V to 5.5V, automatic powerdown
CC
OUT
or FORCEOFF = GND
MOUSE DRIVEABILITY
Transmitter Output Voltage
(See Figure 14 on page 13)
T1 = T2 = GND, T3 = V , T3
loaded with 3kΩto
Full
±5
-
-
V
IN
IN
IN
CC
OUT
GND, T1
and T2
loaded with 2.5mA each
OUT
OUT
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
INVALID High
See Figure 9 on page 11
Full
Full
Full
Full
+25
-2.7
-0.3
-
-
-
2.7
0.3
0.4
-
V
V
Receiver Input Thresholds to
INVALID Low
See Figure 9 on page 11
INVALID, READY Output Voltage
Low
I
I
= 1.6mA
= -1.0mA
-
V
OUT
INVALID, READY Output Voltage
High
V
- 0.6
-
V
OUT
CC
Receiver Positive or Negative
Threshold to INVALID High Delay
-
-
1
-
µs
(t
)
INVH
Receiver Positive or Negative
Threshold to INVALID Low Delay
+25
30
-
µs
(t
)
INVL
Receiver or Transmitter Edge to
Transmitters Enabled Delay (t
(Note 6)
(Note 6)
25
-
100
30
-
µs
)
WU
Receiver or Transmitter Edge to
Transmitters Disabled Delay
Full
15
60
sec
(t
)
AUTOPWDN
TIMING CHARACTERISTICS
Maximum Data Rate
R
= 3kΩone transmitter C = 1000pF
Full
Full
Full
250
1000
1000
-
-
-
-
-
-
kbps
kbps
kbps
L
L
switching
V
= 3V to 4.5V, C = 250pF
L
CC
CC
V
= 4.5V to 5.5V,
= 1000pF
C
L
Receiver Propagation Delay
Receiver input to receiver
t
t
+25
+25
+25
+25
+25
+25
+25
-
0.15
0.15
200
200
25
-
µs
µs
PHL
PLH
output, C = 150pF
L
-
-
Receiver Output Enable Time
Receiver Output Disable Time
Transmitter Skew
Normal operation (ICL3245E only)
Normal operation (ICL3245E only)
-
-
ns
-
-
-
ns
t
t
- t
PHL PLH
(Note 7)
(Note 7)
-
-
ns
Receiver Skew
- t
PHL PLH
-
50
ns
Transition Region Slew Rate
V
= 3.3V, R = 3kΩto 7kΩmeasured from 3V to -3V or -3V
24
-
150
V/µs
CC
L
to 3V, C = 150pF to 1000pF
L
FN4900 Rev 12.00
December 12, 2016
Page 7 of 22
ICL3225E, ICL3227E, ICL3245E
Electrical Specifications Test conditions: V = 3V to 5.5V, C - C = 0.1µF; unless otherwise specified.
CC
1
4
Typicals are at T = +25°C (Continued)
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ESD PERFORMANCE
RS-232 Pins (T , R
)
Human body model
+25
+25
+25
+25
+25
+25
+25
-
-
-
-
-
-
-
±15
±8
-
-
-
-
-
-
-
kV
kV
kV
kV
kV
kV
kV
OUT IN
IEC61000-4-2 contact discharge
IEC61000-4-2 air gap discharge
±15
±2
All Other Pins
ICL3245E
Human body model (HBM)
Charged Device Model (CDM)
Human body model (HBM)
Charged Device Model (CDM)
±1.5
±4
ICL3225E, ICL3227E
±2
NOTES:
6. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
7. Skews are measured at the receiver input switching points (1.4V).
FN4900 Rev 12.00
December 12, 2016
Page 8 of 22
ICL3225E, ICL3227E, ICL3245E
The ICL3245E inverting receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(see Table 2). Conversely, the monitor receiver remains active
even during manual powerdown making it extremely useful for
Ring Indicator monitoring. Standard receivers driving powered
down peripherals must be disabled to prevent current flow
through the peripheral’s protection diodes (see Figures 5 and
6). This renders them useless for wake-up functions, but the
corresponding monitor receiver can be dedicated to this task
as shown in Figure 6.
Detailed Description
These ICL32xxE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 1Mbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge Pump
Intersil’s new ICL32xxE family utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
V
CC
generate ±5.5V transmitter supplies from a V supply as low
R
R
XIN
XOUT
CC
as 3.0V. This allows these devices to maintain RS-232
GND V
V
-25V V
+25V
5k
ROUT
CC
RIN
compliant output levels over the ±10% tolerance range of 3.3V
powered systems. The efficient on-chip power supplies require
only four small, external 0.1µF capacitors for the voltage
GND
FIGURE 4. INVERTING RECEIVER CONNECTIONS
doubler and inverter functions at V = 3.3V. See the
CC
“Capacitor Selection”, and Table 3 on page 13 for capacitor
recommendations for other operating conditions. The charge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal values),
resulting in significant power savings.
V
CC
V
CC
CURRENT
FLOW
V
CC
V
= V
CC
OUT
Transmitters
Rx
The transmitters are proprietary, low dropout, inverting drivers
that translate TTL/CMOS inputs to EIA/TIA-232 output levels.
Coupled with the on-chip ±5.5V supplies, these transmitters
deliver true RS-232 levels over a wide range of single supply
system voltages.
POWERED
DOWN
UART
Tx
OLD
SHDN = GND
GND
RS-232 CHIP
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see
Table 2 on page 10). These outputs may be driven to ±12V
when disabled.
FIGURE 5. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
All devices guarantee a 1Mbps data rate for full load
conditions (3kΩ and 250pF), V ≥ 3.0V, with one transmitter
operating at full speed. Under more typical conditions of
CC
V
CC
V
≥ 3.3V, R = 3kΩ, and C = 250pF, one transmitter easily
CC
L L
operates at 1.4Mbps. Transmitter skew is extremely low on
these devices, and is specified at the receiver input trip points
(1.4V), rather than the arbitrary 0V crossing point typical of
other RS-232 families.
TRANSITION
DETECTOR
TO
ICL3245E
WAKE-UP
LOGIC
Transmitter inputs float if left unconnected, and may cause I
CC
V
CC
increases. Connect unused inputs to GND for the best
performance.
R2
OUTB
R
T
V
= HI-Z
X
OUT
Receivers
R2
OUT
POWERED
DOWN
UART
R2
IN
All the ICL32xxE devices contain standard inverting receivers,
but only the ICL3245E receivers can tristate, via the FORCEOFF
control line. Additionally, the ICL3245E includes a noninverting
T1
IN
X
T1
OUT
(monitor) receiver (denoted by the R
label) that is always
OUTB
FORCEOFF = GND
active, regardless of the state of any control lines. Both
receiver types convert RS-232 signals to CMOS output levels
and accept inputs up to ±25V while presenting the required
3kΩ to 7kΩ input impedance (see Figure 4) even if the power
FIGURE 6. DISABLED RECEIVERS PREVENT POWER DRAIN
is off (V = 0V). The receivers’ Schmitt trigger input stage
CC
uses hysteresis to increase noise immunity and decrease
errors due to slow input signal transitions.
FN4900 Rev 12.00
December 12, 2016
Page 9 of 22
ICL3225E, ICL3227E, ICL3245E
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RS-232
LEVEL
PRESENT
AT
RCVR OR
XMTR EDGE
R
OUTB
WITHIN 30
SEC?
FORCEOFF
INPUT
FORCEON
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
OUTPUTS
(Note 8)
RECEIVER
INPUT?
INVALID
OUTPUT
MODE OF OPERATION
ICL3225E, ICL3227E
NO
NO
YES
YES
NO
NO
X
H
H
H
H
H
H
L
H
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
Active
Active
Active
Active
Active
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
No
Yes
No
L
H
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
Normal Operation (Enhanced
Auto Powerdown Enabled)
L
Yes
No
H
L
L
Powerdown Due to Enhanced
Auto Powerdown Logic
L
Yes
No
H
L
X
X
Manual Powerdown
X
L
Yes
H
ICL322XE - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
Note 9
Note 9
Note 9
Note 9
Active
High-Z
Active
Active
N.A.
N.A.
Yes
No
H
L
Normal Operation
X
ICL3245E
NO
Forced Auto Powerdown
H
H
H
H
H
H
L
H
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
Active
Active
Active
High-Z
High-Z
Active
Active
Active
Active
Active
Active
Active
Active
No
Yes
No
L
H
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
NO
YES
YES
NO
Normal Operation (Enhanced
Auto Powerdown Enabled)
L
Yes
No
H
L
L
Powerdown Due to Enhanced
Auto Powerdown Logic
NO
L
Yes
No
H
L
X
X
X
Manual Powerdown
X
L
Yes
H
ICL3245E - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
X
Note 9
Note 9
Note 9
Note 9
Active
High-Z
Active
High-Z
Active
Active
Yes
No
H
L
Normal Operation
Forced Auto Powerdown
NOTES:
8. Applies only to the ICL3245E.
9. Input is connected to INVALID Output.
Software Controlled (Manual) Powerdown
Powerdown Functionality
These three devices allow the user to force the IC into the low
power, standby state, and utilize a two pin approach where the
FORCEON and FORCEOFF inputs determine the IC’s mode. For
always enabled operation, FORCEON and FORCEOFF are both
strapped high. To switch between active and powerdown
modes, under logic or software control, only the FORCEOFF
input need be driven. The FORCEON state isn’t critical, as
FORCEOFF dominates over FORCEON. Nevertheless, if strictly
manual control over powerdown is desired, the user must strap
FORCEON high to disable the enhanced automatic powerdown
circuitry. ICL3245E inverting (standard) receiver outputs also
disable when the device is in powerdown, thereby eliminating
This 3V family of RS-232 interface devices requires a nominal
supply current of 0.3mA during normal operation (not in
powerdown mode). This is considerably less than the 5mA to
11mA current required of 5V RS-232 devices. The already low
current requirement drops significantly when the device enters
powerdown mode. In powerdown, supply current drops to 1µA,
because the on-chip charge pump turns off (V+ collapses to
V
, V- collapses to GND), and the transmitter outputs tristate.
CC
Inverting receiver outputs may or may not disable in
powerdown; refer to Table 2 for details. This micro-power mode
makes these devices ideal for battery powered and portable
applications.
FN4900 Rev 12.00
December 12, 2016
Page 10 of 22
ICL3225E, ICL3227E, ICL3245E
the possible current path through a shutdown peripheral’s
input protection diode (see Figures 5 and 6).
block should power down. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off
(powered down) or when the RS-232 interface cable is
disconnected. In the case of a disconnected interface cable
where all the receiver inputs are floating (but pulled to GND by
the internal receiver pull down resistors), the INVALID logic
detects the invalid levels and drives the output low. The power
management logic then uses this indicator to power down the
interface block. Reconnecting the cable restores valid levels at
the receiver inputs, INVALID switches high, and the power
management logic wakes up the interface block. INVALID can
also be used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to GND
(as in the case of a powered down driver).
Connecting FORCEOFF and FORCEON together disables the
enhanced automatic powerdown feature, enabling them to
function as a manual SHUTDOWN input (see Figure 7).
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs.
FORCEOFF
PWR
FORCEON
MGT
LOGIC
INVALID
ICL32xxE
VALID RS-232 LEVEL - INVALID = 1
2.7V
INDETERMINATE
I/O
UART
0.3V
INVALID LEVEL - INVALID = 0
-0.3V
CPU
INDETERMINATE
-2.7V
VALID RS-232 LEVEL - INVALID = 1
FIGURE 7. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO
VALID RECEIVER SIGNALS ARE PRESENT
FIGURE 9. DEFINITION OF VALID RS-232 RECEIVER LEVELS
When using both manual and enhanced automatic powerdown
(FORCEON = 0), the ICL32xxE will not power up from manual
powerdown until both FORCEOFF and FORCEON are driven
high, or until a transition occurs on a receiver or transmitter
input. Figure 8 illustrates a circuit for ensuring that the
ICL32xxE powers up as soon as FORCEOFF switches high. The
rising edge of the Master Powerdown signal forces the device
to power up, and the ICL32xxE returns to enhanced automatic
powerdown mode an RC time constant after this rising edge.
The time constant isn’t critical, because the ICL32xxE remains
powered up for 30 seconds after the FORCEON falling edge,
even if there are no signal transitions. This gives slow-to-wake
systems (e.g., a mouse) plenty of time to start transmitting,
and as long as it starts transmitting within 30 seconds both
systems remain enabled.
Enhanced Automatic Powerdown
Even greater power savings is available by using these devices,
which feature an enhanced automatic powerdown function.
When the enhanced powerdown logic determines that no
transitions have occurred on any of the transmitter nor receiver
inputs for 30 seconds, the charge pump and transmitters
powerdown, thereby reducing supply current to 1µA. The
ICL32xxE automatically powers back up whenever it detects a
transition on one of these inputs. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
Enhanced automatic powerdown operates when the FORCEON
input is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input. Table 2
on page 10 summarizes the enhanced automatic powerdown
functionality.
MASTER POWERDOWN LINE
0.1µF
POWER
MANAGEMENT
UNIT
1MΩ
FORCEOFF
EDGE
T_IN
DETECT
FORCEOFF
FORCEON
S
ICL32xxE
30s
AUTOSHDN
TIMER
EDGE
R_IN
FIGURE 8. CIRCUIT TO ENSURE IMMEDIATE POWER UP WHEN
EXITING FORCED POWERDOWN
DETECT
R
INVALID Output
FORCEON
The INVALID output always indicates (see Table 2 on page 10)
whether or not 30µs have elapsed with invalid RS-232 signals
(see Figures 9 and 11) persisting on all of the receiver inputs,
giving the user an easy way to determine when the interface
FIGURE 10. ENHANCED AUTOMATIC POWERDOWN LOGIC
FN4900 Rev 12.00
December 12, 2016
Page 11 of 22
ICL3225E, ICL3227E, ICL3245E
Figure 10 illustrates the enhanced powerdown control logic.
Note that once the ICL32xxE enters powerdown (manually or
automatically), the 30 second timer remains timed out (set),
keeping the ICL32xxE powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
FORCEON
ICL32xxE
INVALID
FORCEOFF
The INVALID output signal switches low to indicate that invalid
levels have persisted on all of the receiver inputs for more than
30µs (see Figure 11), but this has no direct effect on the state
of the ICL32xxE (see the next sections for methods of utilizing
INVALID to power down the device). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
I/O
UART
CPU
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry.
FIGURE 11. CONNECTIONS FOR AUTOMATIC POWERDOWN WHEN
NO VALID RECEIVER SIGNALS ARE PRESENT
The time to recover from automatic powerdown mode is
typically 100µs.
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable
cable, connecting INVALID to FORCEOFF (with FORCEON = 0)
may be a desirable configuration. While the cable is attached
INVALID and FORCEOFF remain high, so the enhanced
automatic powerdown logic powers down the RS-232 device
whenever there is 30 seconds of inactivity on the receiver and
transmitter inputs. Detaching the cable allows the receiver
inputs to drop to an invalid level (GND), so INVALID switches
low and forces the RS-232 device to power down. The
ICL32xxE remains powered down until the cable is
reconnected (INVALID = FORCEOFF = 1) and a transition occurs
on a receiver or transmitter input (see Figure 10 on page 11).
For immediate power up when the cable is reattached,
connect FORCEON to FORCEOFF through a network similar to
that shown in Figure 8 on page 11.
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature (mimics
the function on the ICL3221E/ICL3223E/ICL3243E) by
connecting the INVALID output to the FORCEON and FORCEOFF
inputs, as shown in Figure 12. After 30µs of invalid receiver levels,
INVALID switches low and drives the ICL32xxE into a forced
powerdown condition. INVALID switches high as soon as a
receiver input senses a valid RS-232 level, forcing the ICL32xxE to
power on. See the “INVALID DRIVING FORCEON AND FORCEOFF”
section of Table 2 on page 10 for an operational summary. This
operational mode is perfect for handheld devices that
communicate with another computer via a detachable cable.
Detaching the cable allows the internal receiver pull-down
resistors to pull the inputs to GND (an invalid RS-232 level),
causing the 30µs timer to time out and drive the IC into
powerdown. Reconnecting the cablerestores valid levels, causing
the IC to power back up.
RECEIVER
INPUTS
INVALID
REGION
}
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
t
INVH
INVALID
OUTPUT
t
INVL
t
AUTOPWDN
t
WU
t
WU
t
AUTOPWDN
READY
OUTPUT
V+
V
CC
0
V-
FIGURE 12. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
FN4900 Rev 12.00
December 12, 2016
Page 12 of 22
ICL3225E, ICL3227E, ICL3245E
Ready Output (ICL3225E and ICL3227E
Only)
The Ready output indicates that the ICL322xE is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when V-
reaches -4V or lower.
Mouse Driveability
The ICL3245E is specifically designed to power a serial mouse
while operating from low voltage supplies. Figure 14 shows the
transmitter output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will supply at
least ±5V during worst case conditions (15mA for paralleled V+
transmitters, 7.3mA for single V- transmitter).
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V operation.
For other supply voltages refer to Table 3 for capacitor values.
Do not use values smaller than those listed in Table 3.
Increasing the capacitor values (by a factor of 2) reduces ripple
on the transmitter outputs and slightly reduces power
5V/DIV
2V/DIV
FORCEOFF
T1
V
= +3.3V
C1 - C4 = 0.1µF
CC
consumption. C , C , and C can be increased without
2
3
4
increasing C ’s value, however, do not increase C without also
1
1
increasing C , C , and C to maintain the proper ratios (C to
2
3
4
1
the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s Equivalent Series Resistance (ESR)
usually rises at low temperatures and it influences the amount
of ripple on V+ and V-.
T2
5V/DIV
READY
TIME (20µs/DIV)
FIGURE 13. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
TABLE 3. REQUIRED CAPACITOR VALUES
V
(V)
C
(µF)
C , C , C (µF)
2 3 4
CC
1
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
0.1
0.1
6
5
0.047
0.1
0.33
0.47
V
+
OUT
4
3
V
= 3.0V
CC
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is adequate.
In applications that are particularly sensitive to power supply
2
T1
1
V
+
OUT
0
T2
T3
-1
-2
-3
-4
-5
-6
noise, decouple V to ground with a capacitor of the same
ICL3245E
CC
value as the charge-pump capacitor C . Connect the bypass
1
V
V
-
CC
OUT
capacitor as close as possible to the IC.
V
-
OUT
8
Operation Down to 2.7V
ICL32xxE transmitter outputs meet RS-562 levels (±3.7V), at
0
1
2
3
4
5
6
7
9
10
LOAD CURRENT PER TRANSMITTER (mA)
full data rate, with V as low as 2.7V. RS-562 levels typically
CC
ensure inter-operability with RS-232 devices.
FIGURE 14. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT
(PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS
Transmitter Outputs when
Exiting Powerdown
Figure 13 shows the response of two transmitter outputs when
exiting powerdown mode. As they activate, the two transmitter
outputs properly go to opposite RS-232 levels, with no
glitching, ringing, nor undesirable transients. Each transmitter
is loaded with 3kΩin parallel with 2500pF. Note that the
transmitters enable only when the magnitude of the supplies
exceed approximately 3V.
FOR TOTAL V
+ CURRENT)
OUT
High Data Rates
The ICL32xxE maintain the RS-232 ±5V minimum transmitter
output voltages even at high data rates. Figure 15 on page 14
details a transmitter loopback test circuit, and Figure 16 on
page 14 illustrates the loopback test result at 250kbps. For
this test, all transmitters were simultaneously driving RS-232
loads in parallel with 1000pF, at 250kbps. Figure 17 on
page 14 shows the loopback results for a single transmitter
driving 250pF and an RS-232 load at 1Mbps. The static
transmitters were also loaded with an RS-232 receiver.
FN4900 Rev 12.00
December 12, 2016
Page 13 of 22
ICL3225E, ICL3227E, ICL3245E
V
Interconnection with 3V and 5V
Logic
CC
+
0.1µF
The ICL32xxE directly interfaces with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32xx at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32xx
V
CC
V+
V-
+
+
C1+
+
C
C
1
2
C
3
4
C1-
C2+
C2-
inputs, but ICL32xx outputs do not reach the minimum V for
IH
ICL32xxE
these logic families. See Table 4 for more information.
C
+
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY
VOLTAGES
T
T
IN
OUT
SYSTEM
V
CC
POWER-SUPPLY SUPPLY
C
L
R
IN
R
OUT
VOLTAGE
(V)
VOLTAGE
(V)
COMPATIBILITY
FORCEON
5k
3.3
5
3.3
5
Compatible with all CMOS families.
V
CC
FORCEOFF
Compatible with all TTL and CMOS
logic families.
FIGURE 15. TRANSMITTER LOOPBACK TEST CIRCUIT
5
3.3
Compatible with ACT and HCT CMOS,
and with TTL. ICL32XX outputs are
incompatible with AC, HC, and CD4000
CMOS inputs.
5V/DIV
T1
IN
±15kV ESD Protection
All pins on ICL32xx devices include ESD protection structures,
but the ICL32xxE family incorporates advanced structures,
which allow the RS-232 pins (transmitter outputs and receiver
inputs) to survive ESD events up to ±15kV. The RS-232 pins are
particularly vulnerable to ESD damage because they typically
connect to an exposed port on the exterior of the finished
product. Simply touching the port pins, or connecting a cable,
can cause an ESD event that might destroy unprotected ICs.
These new ESD structures protect the device whether or not it
is powered up, protect without allowing any latchup
mechanism to activate, and don’t interfere with RS-232
signals as large as ±25V.
T1
OUT
OUT
R1
V
C
= +3.3V
CC
- C = 0.1µF
1
4
2µs/DIV
FIGURE 16. LOOPBACK TEST AT 250kbps (C = 1000pF)
L
Human Body Model (HBM) Testing
5V/DIV
T1
As the name implies, this test method emulates the ESD event
delivered to an IC during human handling. The tester delivers
the charge through a 1.5kΩ current limiting resistor, making
the test less severe than the IEC61000 test which utilizes a
330Ω limiting resistor. The HBM method determines an ICs
ability to withstand the ESD transients typically present during
handling and manufacturing. Due to the random nature of
these events, each pin is tested with respect to all other pins.
The RS-232 pins on “E” family devices can withstand HBM ESD
events to ±15kV.
IN
T1
OUT
OUT
R1
IEC61000-4-2 Testing
V
C
= +3.3V
CC
- C = 0.1µF
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge storage
capacitor yields a test that is much more severe than the HBM
1
4
0.5µs/DIV
FIGURE 17. LOOPBACK TEST AT 1Mbps (C = 250pF)
L
FN4900 Rev 12.00
December 12, 2016
Page 14 of 22
ICL3225E, ICL3227E, ICL3245E
test. The extra ESD protection built into this device’s RS-232 pins
allows the design of equipment meeting Level 4 criteria without
the need for additional board level protection on the RS-232 port.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the tested
pin before the probe tip is energized, thereby eliminating the
variables associated with the air-gap discharge. The result is a
more repeatable and predictable test, but equipment limits
prevent testing devices at voltages higher than ±8kV. All “E”
family devices survive ±8kV contact discharges on the RS-232
pins.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the IC pin
until the voltage arcs to it. The current waveform delivered to the
IC pin depends on approach speed, humidity, temperature, etc.,
so it is difficult to obtain repeatable results. The “E” device RS-
232 pins withstand ±15kV air-gap discharges.
Typical Performance Curves
V
= 3.3V, T = +25°C
CC A
6
110
90
70
50
30
V
+
OUT
4
2
+SLEW
1 TRANSMITTER AT 1Mbps
OTHER TRANSMITTERS AT 30kbps
0
-SLEW
-2
-4
V
-
OUT
10
0
-6
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 19. SLEW RATE vs LOAD CAPACITANCE
FIGURE 18. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
90
90
80
70
60
50
ICL3225E
80
ICL3227E
1Mbps
1Mbps
70
60
50
250kbps
120kbps
40
40
30
250kbps
30
120kbps
20
10
20
10
4000
5000
2000
3000
1000
0
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 20. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN
TRANSMITTING DATA
FIGURE 21. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN
TRANSMITTING DATA
FN4900 Rev 12.00
December 12, 2016
Page 15 of 22
ICL3225E, ICL3227E, ICL3245E
Typical Performance Curves
V
= 3.3V, T = +25°C (Continued)
A
CC
90
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
NO LOAD
ALL OUTPUTS STATIC
1Mbps
ICL3245E
80
70
60
50
250kbps
40
30
120kbps
20
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
1000
2000
3000
4000
5000
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 22. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN
TRANSMITTING DATA
Die Characteristics
MSUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
ICL3225E: 937
ICL3227E: 825
ICL3245E: 1109
PROCESS
Si Gate CMOS
FN4900 Rev 12.00
December 12, 2016
Page 16 of 22
ICL3225E, ICL3227E, ICL3245E
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure that you have the latest revision.
DATE
REVISION
CHANGE
December 12, 2016
FN4900.12
Updated entire datasheet applying Intersil’s new standards.
Updated Ordering information table on page 2.
-Updated Tape and Reel note.
-Updated Note 2.
-Added MSL note.
-Removed all non-compliant products.
In the “Electrical Specifications” table under “ESD PERFORMANCE” on page 8, Updated All Other pins section
by changing typical value for the ICL3245E from “±3” to “±2” and adding ICL3225E and ICL3227E information.
December 3, 2015
August 31, 2015
FN4900.11
FN4900.10
Updated Ordering Information Table on page 2: Added replacement part numbers for ICL3245ECBZ and
ICL3245ECVZ.
Ordering Information Table on page 2.
Added Revision History.
Added About Intersil Verbiage.
Updated POD M28.3 to latest revision changes: Added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN4900 Rev 12.00
December 12, 2016
Page 17 of 22
ICL3225E, ICL3227E, ICL3245E
Dual-In-Line Plastic Packages (PDIP)
N
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2
3
N/2
INCHES MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
0.980
0.005
0.300
0.240
0.39
2.93
0.356
1.55
0.204
24.89
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
1.060
-
4.95
0.558
1.77
0.355
26.9
-
-
-C-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
0.325
0.280
8.25
7.11
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
20
20
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be
A
-C-
perpendicular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN4900 Rev 12.00
December 12, 2016
Page 18 of 22
For the most recent package outline drawing, see E20.3.
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
MAX
E
GAUGE
PLANE
SYMBOL
MIN
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
0.078
-
-
0.002
0.065
0.009
0.004
0.233
0.197
0.05
1.65
0.22
0.09
5.90
5.00
-
1
2
3
0.072
0.014
0.009
0.255
0.220
1.85
0.38
0.25
6.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
-
D
D
3
-C-
E
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
H
L
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 3 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension
at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
FN4900 Rev 12.00
December 12, 2016
Page 19 of 22
For the most recent package outline drawing, see M16.209.
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
N
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
M
M
B
0.25(0.010)
H
E
INCHES MILLIMETERS
MIN MAX
GAUGE
PLANE
-B-
SYMBOL
MIN
MAX
NOTES
A
A1
A2
B
0.068
0.002
0.066
0.010’
0.004
0.278
0.205
0.078
0.008’
0.070’
0.015
0.008
0.289
0.212
1.73
0.05
1.68
0.25
0.09
7.07
5.20’
1.99
0.21
1.78
0.38
0.20’
7.33
5.38
1
2
3
L
0.25
0.010
SEATING PLANE
A
9
-A-
D
C
D
3
4
-C-
E
A2
e
A1
e
0.026 BSC
0.65 BSC
C
B
0.10(0.004)
0.301
0.025
0.311
0.037
7.65
0.63
7.90’
0.95
H
L
M
M
S
B
0.25(0.010)
C
A
6
7
N
20
20
0 deg.
8 deg.
0 deg.
8 deg.
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
Rev. 3 11/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN4900 Rev 12.00
December 12, 2016
Page 20 of 22
For the most recent package outline drawing, see M20.209.
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
C
0.0091
0.6969
0.2914
0.32
-
-A-
D
E
0.7125 17.70
18.10
7.60
3
h x 45o
D
0.2992
7.40
4
e
0.05 BSC
1.27 BSC
-
-C-
a
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
H
e
A1
C
5
h
L
B
0.10(0.004)
0.016
6
0.25(0.010) M
C
A M B S
N
28
28
7
o
o
o
o
0
8
0
8
-
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
(1.50mm)
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
(1.27mm TYP)
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4900 Rev 12.00
December 12, 2016
Page 21 of 22
For the most recent package outline drawing, see M28.3.
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
MAX
E
GAUGE
PLANE
SYMBOL
MIN
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
0.078
-
-
0.002
0.065
0.009
0.004
0.390
0.197
0.05
1.65
0.22
0.09
9.90
5.00
-
1
2
3
0.072
0.014
0.009
0.413
0.220
1.85
0.38
0.25
10.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
-
D
D
3
-C-
E
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
H
L
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
28
28
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm
(0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4900 Rev 12.00
December 12, 2016
Page 22 of 22
For the most recent package outline drawing, see M28.209.
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