HD74AC175T [RENESAS]
AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, TTP-16DA;
| 型号： | HD74AC175T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, TTP-16DA 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC175
Quad D-Type Flip-Flop
REJ03D0257–0200Z
(Previous ADE-205-377 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both
true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of
the Clock or D inputs, when Low.
Features
•
•
•
•
•
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Asynchronous Common Reset
True and Complement Output
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC175AFPEL SOP-16 pin (JEITA) FP-16DAV
HD74AC175ARPEL SOP-16 pin (JEDEC) FP-16DNV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL(2,000 pcs/reel)
HD74AC175TELL TSSOP-16 pin
TTP-16DAV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
7
8
16 VCC
MR
Q0
Q0
D0
D1
Q1
Q1
15 Q
3
14
13
Q
3
D
3
2
12 D
11 Q
2
10 Q
2
GND
9
CP
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC175
Logic Symbol
D
0
D
1
D
2
D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
Pin Names
D0 to D3
CP
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
MR
Q0 to Q3
Q0 to Q 3 Complement Outputs
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High
clock (CP) transition, causing individual Q and Q outputs to follow. A Low input on the Master Reset (MR) will force
all Q outputs Low and Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general
logic applications where a common Master Reset and Clock are acceptable.
Truth Table
Inputs
Outputs
@ tn+1
@ tn, MR = H
Dn
L
Qn
L
Qn
H
H
H
L
H : High Voltage Level
L
:
:
Low Voltage Level
tn
Bit Time before Clock Pulse
: Bit Time after Clock Pulse
tn + 1
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC175
Logic Diagram
MR CP D3
D2
D1
D0
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
CP
CP
CP
CD
CD
CD
CD
Q3Q3
Q2Q2
Q1Q1
Q0Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Absolute Maximum Ratings
Item
Symbol
VCC
Ratings
–0.5 to 7
Unit
Condition
VI = –0.5V
Supply voltage
V
DC input diode current
IIK
–20
mA
mA
V
20
VI = Vcc+0.5V
DC input voltage
VI
–0.5 to Vcc+0.5
DC output diode current
IOK
–50
mA
mA
V
VO = –0.5V
50
VO = Vcc+0.5V
DC output voltage
VO
–0.5 to Vcc+0.5
±50
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
IO
mA
mA
°C
ICC, IGND
Tstg
±50
–65 to +150
Recommended Operating Conditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
VIN 30% to 70% VCC
tr, tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC175
DC Characteristics
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
min.
2.1
3.15
3.85
—
max.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
VOUT = 0.1 V or VCC –0.1 V
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
—
Input leakage
current
IIN
—
—
µA
VIN = VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
—
—
86
—
—
80
mA
mA
µA
VOLD = 1.1 V
—
–75
—
VOHD = 3.85 V
Quiescent supply
current
8.0
VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics
Ta = +25°C
CL = 50 pF
Typ
Ta = –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
Symbol VCC (V)*1
Min
149
Max
Min
Max
Unit
fmax
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
—
—
139
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
MHz
ns
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
Propagation delay
CP to Qn or Qn
Propagation delay
CP to Qn or Qn
Propagation delay
MR to Qn
tPLH
tPHL
tPLH
tPHL
9.5
7.0
8.5
6.0
7.5
5.5
8.5
6.0
12.0
9.0
13.5
9.5
13.0
9.5
14.5
10.5
13.5
10.0
12.5
9.0
ns
12.5
9.0
ns
Propagation delay
11.0
8.5
ns
MR to Qn
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC175
AC Operating Requirements
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Set-up time, HIGH or LOW
Dn to CP
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
0
4.5
4.5
3.0
1.0
1.0
4.5
3.5
5.0
3.5
0.0
0.0
ns
ns
ns
ns
ns
3.0
1.0
1.0
4.5
3.5
4.5
3.5
0.0
0.0
Hold time, HIGH or LOW
Dn to CP
th
0
CP pulse width HIGH or LOW tw
2.5
2.0
2.5
2.0
–2.0
–1.0
MR pulse width, LOW
tw
Recovery time MR to CP
trec
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Unit
Condition
CIN
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
CPD
45.0
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC175
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DAV
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.3 Max
9
8
16
1
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC175
As of January, 2003
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*0.20 ± 0.05
6.40 ± 0.20
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-16DAV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.2.00, Jul.16.2004, page 7 of 7
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相关型号：
HD74AC175T-EL
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, TTP-16DA
HITACHI
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