HD74AC175T-ELL [RENESAS]
D FLIP-FLOP, PDSO16, TTP-16DA;
| 型号： | HD74AC175T-ELL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | D FLIP-FLOP, PDSO16, TTP-16DA 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC175
Quad D-Type Flip-Flop
ADE-205-377 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-
High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when Low.
Features
•
•
•
•
•
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Asynchronous Common Reset
True and Complement Output
Outputs Source/Sink 24 mA
HD74AC175
Pin Arrangement
1
2
3
4
5
16 VCC
15 Q3
MR
Q0
Q0
D0
D1
14
13
Q3
D3
12 D2
11 Q2
10 Q2
Q1 6
7
8
Q1
GND
9
CP
(Top view)
Logic Symbol
D0
D1
D2
D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
Pin Names
D0 to D3
CP
Data Inputs
Clock Pulse Input
MR
Q0 to Q3
Master Reset Input
True Outputs
Q0 to Q 3 Complement Outputs
2
HD74AC175
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs
Outputs
@ tn, MR = H
@ tn+1
Qn
L
Dn
L
Qn
H
H
H
L
H :
High Voltage Level
L
:
:
Low Voltage Level
tn
Bit Time before Clock Pulse
Bit Time after Clock Pulse
tn + 1
:
Logic Diagram
MR CP D3
D2
D1
D0
D
Q
Q
D
Q
Q
D
Q
D
Q
Q
CP
CD
CP
CD
CP
CP
Q
CD
CD
Q3Q3
Q2Q2
Q1Q1
Q0Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
3
HD74AC175
DC Characteristics (unless otherwise specified)
Item
Symbol Max
Unit
Condition
Maximum quiescent supply current
ICC
80
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current
ICC
8.0
µA
VIN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
AC Characteristics
Ta = +25°C
Ta = –40°C to +85°C
CL = 50 pF
CL = 50 pF
Item
Symbol VCC (V)*1
Min
149
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
Max
—
Min
139
187
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
Unit
Maximum clock
frequency
fmax
tPLH
tPHL
tPLH
tPHL
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
—
MHz
—
—
—
Propagation delay
CP to Qn or Qn
Propagation delay
CP to Qn or Qn
Propagation delay
MR to Qn
9.5
7.0
8.5
6.0
7.5
5.5
8.5
6.0
12.0
9.0
13.5
9.5
ns
ns
ns
ns
13.0
9.5
14.5
10.5
13.5
10.0
12.5
9.5
12.5
9.0
Propagation delay
MR to Qn
11.0
8.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
4
HD74AC175
AC Operating Requirements
Ta = –40°C
Ta = +25°C
to +85°C
CL = 50 pF
CL = 50 pF
Item
Symbol VCC (V)*1 Typ
Guaranteed Minimum
Unit
Set-up time, HIGH or LOW
Dn to CP
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
0
4.5
3.0
1.0
1.0
4.5
3.5
4.5
3.5
0.0
0.0
4.5
3.0
1.0
1.0
4.5
3.5
5.0
3.5
0.0
0.0
ns
Hold time, HIGH or LOW
Dn to CP
th
ns
ns
ns
ns
0
CP pulse width HIGH or LOW tw
2.5
2.0
2.5
2.0
–2.0
–1.0
MR pulse width, LOW
tw
Recovery time MR to CP
trec
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Symbol
CIN
Typ
4.5
Unit
pF
Condition
VCC = 5.5 V
VCC = 5.0 V
Input capacitance
Power dissipation capacitance
CPD
45.0
pF
5
HD74AC175
Package Dimensions
Unit: mm
19.20
20.00 Max
16
1
9
8
1.3
1.11 Max
7.62
+ 0.13
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
Hitachi Code
DP-16
JEDEC
EIAJ
Mass (reference value)
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
8
16
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0° – 8°
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Hitachi Code
JEDEC
FP-16DA
—
EIAJ
Conforms
0.24 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
6
HD74AC175
Unit: mm
9.9
10.3 Max
9
16
1
8
1.27
+ 0.10
6.10
– 0.30
1.08
0.635 Max
0° – 8°
+ 0.67
0.60
– 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.25
M
Hitachi Code
JEDEC
EIAJ
FP-16DN
Conforms
Conforms
0.15 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
+ 0.08
– 0.07
*0.22
0.20 ± 0.06
6.40 ± 0.20
0° – 8°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
TTP-16DA
—
EIAJ
—
0.05 g
*Dimension including the plating thickness
Base material dimension
Mass (reference value)
7
HD74AC175
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Colophon 2.0
8
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