HD74AC182 [RENESAS]
Carry Lookahead Generator; 超前进位发生器
| 型号： | HD74AC182 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Carry Lookahead Generator |
| 文件： | 总7页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC182
Carry Lookahead Generator
REJ03D0258–0200Z
(Previous ADE-205-378 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC182 is a high-speed carry lookahead generator. It is generally used with the HD74AC181 or HD74AC381
4-bit arithmetic logic unit to provide high-speed lookahead over word lengths of more than four bits.
Features
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
Package Type
Package Code Package AAbbreviation (Quantity)
HD74AC182FPEL SOP-16 pin (JEITA) FP-16DAV
HD74AC182RPEL SOP-16 pin (JEDEC) FP-16DNV
FP
RP
cs/reel)
s/reel)
Notes: 1. Please consult the sales office for the above package
2. The packages with lead-free pins are distinguishes by adding V at the end of
the package code.
Pin Arrangement
6
7
8
16 VCC
15 P
G
3
2
14
13
G
2
C
n
12 Cn+X
11 Cn+y
10 G
P
GND
9
C
n+z
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 6
HD74AC182
Logic Symbol
P0
G0
P1
G1
P2
G2
P
3
G3
G
P
C
n
C
n+x
C
n+y
Cn+z
Pin Names
Cn
Carry Input
G0, G2
Carry Generate Inputs (Active Low)
Carry Generate Input (Active Low)
Carry Generate Input (Active Low)
Carry Propagate Inputs (Active Low)
Carry Propagate Input (Active Low)
Carry Propagate Input (Active Low)
Carry Outputs
G
G1
P03, P1
P
P23
C
n + x to Cn + z
G
P
Carry Generate Output (Active Low)
Carry Propagate Output (Active Low
Logic Diagram
C
n
G
0
P0
G1
P1
G3 P3
C
n+x
C
n+y
Cn+z
G
P
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Functional Description
The HD74AC182/HD74ACT182 carry lookahead generator accepts up to four pairs of Active Low Carry Propagate (P0
to P3) and Carry Generate (G0 to G3) signals and an Active High Carry input (Cn) and provides anticipated Active High
carries (Cn + x, Cn + y , Cn + z) across four groups of binary adders. The HD74AC182/HD74ACT182 also has Active Low
Carry Propagate (P) and Carry Generate (G) outputs which may be used for further level of lookahead. The logic
equations provided at the outputs are:
Rev.2.00, Jul.16.2004, page 2 of 6
HD74AC182
Cn + x = G0 + P0Cn
Cn + y = G1 + P1G0 + P1P0Cn
Cn + z = G2 + P2G1 + P2P1G0 + P2P1P0Cn
G
P
= G3 + P3G2 + P3P2G1 + P3P2P1G0
= P3P2P1P0
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand
mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.
Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by
dropping the last HD74AC182/HD74ACT182.
Truth Table
Inputs
Outputs
Cn + z
Cn
G0
P0
G1
P1
G2
P2
G3
P3
Cn + x
Cn + y
G
P
X
L
H
H
L
H
X
X
L
L
L
X
H
X
X
L
H
H
X
X
H
H
X
L
X
H
X
X
X
L
H
H
H
L
H
X
X
X
L
X
X
H
X
X
X
L
X
X
X
H
H
H
X
L
X
X
X
H
H
X
X
L
L
X
X
H
X
X
X
X
L
X
H
X
X
X
X
L
H
H
H
H
H
X
L
L
L
L
X
X
X
H
H
H
H
H
X
X
X
X
X
L
X
X
X
X
H
X
X
X
L
X
L
X
X
X
L
H
H
H
L
H
X
X
X
X
L
H
H
H
H
L
X
X
X
L
X
X
L
L
X
L
L
L
H
X
X
X
L
X
H
X
X
L
X
X
H
X
L
X
X
X
H
L
H
H
H
H
L
H : High Voltage Level
L
:
:
Low Voltage Level
Immaterial
X
Rev.2.00, Jul.16.2004, page 3 of 6
HD74AC182
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VCC
Ratings
–0.5 to 7
Unit
Condition
VI = –0.5V
V
DC input diode current
IIK
–20
mA
mA
V
20
VI = Vcc+0.5V
DC input voltage
VI
–0.5 to Vcc+0.5
DC output diode current
IOK
–50
mA
mA
V
VO = –0.5V
50
VO = Vcc+0.5V
DC output voltage
VO
–0.5 to Vcc+0.5
±50
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
IO
mA
mA
°C
ICC, IGND
Tstg
±50
–65 to +150
Recommended Operating Conditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
Input rise and fall time
(except Schmitt inputs)
tr, tf
VCC = 3.0V
CC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
DC Characteristics
Item
Sym-
bol
Vcc
(V)
Ta = 2
nit
Condition
min.
2.1
5
—
x.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.
4
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
9
5.49
—
—
—
.65
—
0.9
1.35
1.65
—
—
—
Output voltage
.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
—
Input leakage
current
IIN
—
—
µA
VIN = VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
—
—
86
—
—
80
mA
mA
µA
VOLD = 1.1 V
—
–75
—
VOHD = 3.85 V
Quiescent supply
current
8.0
VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 4 of 6
HD74AC182
AC Characteristics
Ta = +25°C
CL = 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Item
Symbol VCC (V)*1
Min
1.0
Typ
Max
10.5
8.0
Min
Max
11.5
Unit
Propagation delay
Pn to P
tPLH
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
8.0
5.5
8.0
5.5
9.5
7.5
9.0
7.0
10.5
8.0
11.5
9.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.0
Propagation delay
Pn to P
tPHL
tPLH
tPHL
tPLH
tPHL
10.5
8.0
11.5
9.0
Propagation delay
Cn to Cn + x, y, z
12.0
10.0
12.0
10.0
13.0
10.5
14.0
11.5
13.0
11.0
13.0
11.0
14.0
11.5
15.5
12.5
Propagation delay
Cn to Cn + x, y, z
Propagation delay
Pn or Gn to Cn + x, y, z
Propagation delay
Pn or Gn to Cn + x, y, z
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Condition
CIN
4.5
50.0
0 V
Power dissipation capacitance
CPD
Rev.2.00, Jul.16.2004, page 5 of 6
HD74AC182
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
orms
24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
+ 0.10
6.10
– 0.30
1.08
Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 6 of 6
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