HA16114FP [RENESAS]
Switching Regulator for Chopper Type DC/DC Converter; 开关稳压器型DC / DC转换器
| 型号： | HA16114FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Switching Regulator for Chopper Type DC/DC Converter |
| 文件： | 总38页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Switching Regulator for Chopper Type DC/DC Converter
REJ03F0055-0200Z
(Previous: ADE-204-020A)
Rev.2.0
Sep.18.2003
Description
The HA16114P/FP/FPJ and HA16120FP/FPJ are single-channel PWM switching regulator controller ICs
suitable for chopper-type DC/DC converters. Integrated totem-pole output circuits enable these ICs to
drive the gate of a power MOSFET directly. The output logic of the HA16120 is designed to control a
DC/DC step-up (boost) converter using an N-channel power MOS FET. The output logic of the HA16114
is designed to control a DC/DC step-down (buck) converter or inverting converter using a P-channel power
MOS FET.
These ICs can operate synchronously with external pulse, a feature that makes them ideal for power
supplies that use a primary-control AC/DC converter to convert commercial AC power to DC, then use one
or more DC/DC converters on the secondary side to obtain multiple DC outputs. Synchronization is with
the falling edge of the ‘sync’ pulse, which can be the secondary output pulse from a flyback transformer.
Synchronization eliminates the beat interference that can arise from different operating frequencies of the
AC/DC and DC/DC converters, and reduces harmonic noise. Synchronization with an AC/DC converter
using a forward transformer is also possible, by inverting the ‘sync’ pulse.
Overcurrent protection features include a pulse-by-pulse current limiter that can reduce the width of
individual PWM pulses, and an intermittent operating mode controlled by an on-off timer. Unlike the
conventional latched shutdown function, the intermittent operating function turns the IC on and off at
controlled intervals when pulse-by-pulse current limiting continues for a programmable time. This results
in sharp vertical settling characteristics. Output recovers automatically when the overcurrent condition
subsides.
Using these ICs, a compact, highly efficient DC/DC converter can be designed easily, with a reduced
number of external components.
Functions
•
•
•
•
•
•
•
•
2.5 V voltage reference
Sawtooth oscillator (Triangle wave)
Overcurrent detection
External synchronous input
Totem-pole output
Undervoltage lockout (UVL)
Error amplifier
Vref overvoltage protection (OVP)
Rev.2.0, Sep.18.2003, page 1 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Features
•
•
•
Wide supply voltage range: 3.9 V to 40 V*
Maximum operating frequency: 600 kHz
Able to drive a power MOS FET (±1 A maximum peak current) by the built-in totem-pole gate pre-
driver circuit
•
•
•
•
Can operate in synchronization with an external pulse signal, or with another controller IC
Pulse-by-pulse overcurrent limiting (OCL)
Intermittent operation under continuous overcurrent
Low quiescent current drain when shut off by grounding the ON/OFF pin
HA16114: IOFF = 10 µA (max)
HA16120: IOFF = 150 µA (max)
•
•
•
•
Externally trimmable reference voltage (Vref): ±0.2 V
Externally adjustable undervoltage lockout points (with respect to VIN)
Stable oscillator frequency
Soft start and quick shut function
Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V.
Ordering Information
Hitachi Control ICs for Chopper-Type DC/DC Converters
Product
Channel Control Functions
Overcurrent
Protection
Channels Number
No.
Output Circuits
Step-Up
Step-Down Inverting
Dual
HA17451 Ch 1
Ch 2
❍
❍
—
❍
—
—
—
❍
❍
❍
❍
—
❍
❍
❍
—
❍
❍
❍
—
❍
—
❍
—
Open collector
SCP with timer (latch)
HA16114
HA16120
Single
Dual
—
—
Totem pole
Pulse-by-pulse
power MOS FET current limiter and
driver
intermittent operation
by on/off timer
HA16116 Ch 1
Ch 2
HA16121 Ch 1
Ch 2
Rev.2.0, Sep.18.2003, page 2 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Pin Arrangement
GND*1
1
2
3
4
5
6
7
8
16 Vref
15 ADJ
14 DB
13 ON/
12 TM
11 CL(−)
10 VIN
RT
CT
IN(−)
E/O
IN(+)
P.GND*1
9
OUT
(Top view)
Note: 1. Pin 1 (GND) and Pin 8 (P.GND) must be connected each other with external wire.
Pin Description
Pin No.
Symbol
GND
SYNC
RT
Function
1
Signal ground
2
External sync signal input (synchronized with falling edge)
Oscillator timing resistor connection (bias current control)
Oscillator timing capacitor connection (sawtooth voltage output)
Inverting input to error amplifier
Error amplifier output
3
4
CT
5
IN(–)
E/O
6
7
IN(+)
P.GND
OUT
VIN
Non-inverting input to error amplifier
Power ground
8
9
Output (pulse output to gate of power MOS FET)
Power supply input
10
11
12
CL(–)
TM
Inverting input to current limiter
Timer setting for intermittent shutdown when overcurrent is detected
(sinks timer transistor current)
13
14
15
16
ON/OFF
DB
IC on/off control (off below approximately 0.7 V)
Dead-band duty cycle control input
ADJ
Reference voltage (Vref) adjustment input
2.5 V reference voltage output
Vref
Rev.2.0, Sep.18.2003, page 3 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Block Diagram
Vref
16
ADJ
15
DB
14
ON/
13
TM
12
CL(−)
VIN
10
OUT
9
11
0.2 V
−
CL
+
1k
from
UVL
ON/
VIN
ADJ
Vref
0.3V
2.5V
bandgap
reference
voltage
UVL
H
UVL
output
Latch
L
VL VH
OVP
S
R
Q
generator
from
UVL
PWM COMP
*1
VIN
+
−
+
OUT
Triangle waveform
NAND (HA16114)
generator
1.6 V
1.0 V
0.3 V
1k
Latch reset pulses
from
UVL
+
EA
1.1 V
RT
−
Bias
current
1
2
3
4
5
6
7
8
GND
RT
CT
IN(−)
E/O
IN(+)
P.GND
Note: 1. The HA16120 has an AND gate.
Rev.2.0, Sep.18.2003, page 4 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Timing Waveforms
Generation of PWM pulse output from sawtooth wave (during steady-state operation)
1
fOSC
T =
Dead-band
voltage (at DB)
1.6 V typ
Sawtooth wave
(at CT)
1.0 V
typ
Error amplifier
output (at E/O)
VIN
HA16114 PWM
pulse output
Off
Off
Off
Off
Off
(drives gate of
P-channel
power MOS FET)
On
On
On
On
On
On
On
On
On
On
0 V
VIN
HA16120 PWM
pulse output
(drives gate of
N-channel
power MOS FET)
Off
Off
Off
Off
Off
Time t
0 V
tON
T
Note: On duty =
Rev.2.0, Sep.18.2003, page 5 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Guide to the Functional Description
The description covers the topics indicated below.
Vref adjustment,
undervoltage
lockout, and
overcurrent
Oscillator
frequency
(fOSC) control and
synchronization
GND*1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vref
ADJ
DB
1.
5.
protection
RT
CT
DC/DC output
voltage setting
and error
ON/
pin
6.
7.
2.
3.
4.
usage
ON/
TM
amplifier usage
IN(−)
Intermittent
mode timing
during
Dead-band and
soft-start settings
E/O
CL(−)
VIN
overcurrent
IN(+)
Setting of
current limit
P.GND*1
OUT
8.
Output stage and
power MOS FET
driving method
(Top view)
Note: 1. P.GND is a high-current (±1 A maximum peak) ground pin connected to the totem-pole output circuit.
GND is a low-current ground pin connected to the Vref voltage reference. Both pins must be grounded.
1. Sawtooth Oscillator (Triangle Wave)
1.1 Operation and Frequency Control
The sawtooth wave is a voltage waveform from which the PWM pulses are created (See figure 1). The
sawtooth oscillator operates as follows. A constant current IO determined by an external timing resistor RT
is fed continuously to an external timing capacitor CT. When the CT pin voltage exceeds a comparator
threshold voltage VTH, the comparator output opens a switching transistor, allowing a 3IO discharge current
to flow from CT. When the CT pin voltage drops below a threshold voltage VTL, the comparator output
closes the switching transistor, stopping the 3IO discharge. Repetition of these operations generates a
sawtooth wave.
The value of IO is 1.1 V/RT Ω. The IO current mirror has a limited current capacity, so RT should be at least
5 kΩ (IO ≤ 220 µA).
Internal resistances RA, RB, and RC set the peak and valley voltages VTH and VTL of the sawtooth waveform at
approximately 1.6 V and 1.0 V.
Rev.2.0, Sep.18.2003, page 6 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
The oscillator frequency fOSC can be calculated as follows.
1
fOSC
=
t1 + t2 + t3
CT × (VH − VL)
Here, t1 =
1.1 V/RT
CT × (VH − VL)
3 × 1.1 V/RT
t
t
=
2
3
≈ 0.8 µs (comparator delay time)
Since
V
H − VL = 0.6 V
1
fOSC
≈
(Hz)
0.73 × CT × RT + 0.8 (µs)
At high frequencies the comparator delay causes the sawtooth wave to overshoot the 1.6 V threshold and
undershoot the 1.0 V threshold, and changes the dead-band thresholds accordingly. Select constants by
testing under implementation conditions.
3.2 V
(Internal voltage)
Vref
2.5 V
Current
mirror
CT charging
IO
RA
RB
Oscillator
comparator
RC
1.1 V
Discharg
-ing 3IO
1 : 4
Sync
circuit
RT
IO
CT
External circuit
VH = 1.6 V typ
VL = 1.0 V typ
t1 : t2 = 3 : 1
t2
t1
Figure 1.1 Equivalent Circuit of Oscillator
Rev.2.0, Sep.18.2003, page 7 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
1.2 External Synchronization
These ICs have a sync input pin so that they can be synchronized to a primary-control AC/DC converter.
Pulses from the secondary winding of the switching transformer should be dropped through a resistor
voltage divider to the sync input pin. Synchronization takes place at the falling edge, which is optimal for
multiple-output power supplies that synchronize with a flyback AC/DC converter.
The sync input pin (SYNC) is connected internally through a synchronizing circuit to the sawtooth
oscillator to synchronize the sawtooth waveform (see figure 1.2).
•
•
•
•
Synchronization is with the falling edge of the external sync signal.
The frequency of the external sync signal must be in the range fOSC < fSYNC < fOSC × 2.
The duty cycle of the external sync signal must be in the range 5% < t1/t2 < 50% (t1 = 300 ns Min).
With external synchronization, VTH' can be calculated as follows.
fOSC
f
VTH' = (VTH − VTL) ×
+ VTL
Note: When not using external synchronization, connect the SYNC pin to the Vref pin.
VTH (1.6 V typ)
Sawtooth wave
VTH
'
(fOSC
)
VTL
(1.0 V typ)
pin
Vref
(f
)
1 V
t1
t2
Synchronized
at falling edge
Figure 1.2 External Synchronization
Rev.2.0, Sep.18.2003, page 8 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
2. DC/DC Output Voltage Setting and Error Amplifier Usage
2.1 DC/DC Output Voltage Setting
1. Positive Output Voltage (VO > Vref)
HA16114 with step-down topology
HA16120 with step-down (boost) topology
CL
CL
VIN
VIN
EA
EA
IN(−)
IN(−)
OUT
−
−
VO
IN(+)
IN(+)
VO
+
+
OUT
+
GND
GND
−
+
Vref
Vref
−
R2
R1
R2
R1
R1 + R2
VO = Vref ×
R2
Figure 2.1 Output Voltage Setting (1)
2. Negative Output Voltage (VO < 0 V)
HA16114 with inverting topology
CL
VIN
EA
OUT
−
IN(−)
+
IN(+)
Vref
−
+
R3
R4
R2
VO = −Vref ×
R1
R1 + R2
R2
R3
×
− 1
R3 + R4
Figure 2.2 Output Voltage Setting (2)
Rev.2.0, Sep.18.2003, page 9 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
2.2 Error Amplifier Usage
Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier in these ICs is a simple
NPN-transistor differential amplifier with a constant-current-driven output circuit.
The amplifier combines a wide bandwidth (fT = 4 MHz) with a low open-loop gain (50 dB Typ), allowing
stable feedback to be applied when the power supply is designed. Phase compensation is also easy.
IC internal VIN
IN(−)
E/O
IN(+)
To internal PWM
comparator
80 µA
40 µA
Figure 2.3 Error Amplifier Equivalent Circuit
3. Dead-Band Duty Cycle and Soft-Start Settings
3.1 Dead-Band Duty Cycle Setting
The dead-band duty cycle (the maximum duty cycle of the PWM pulse output) can be programmed by the
voltage VDB at the DB pin. A convenient way to obtain VDB is to divide the IC’s Vref output by two external
resistors. The dead-band duty cycle (DB) and VDB can be calculated as follows.
V
V
TH − VDB
DB =
× 100 (%)
This applies when VDB > VTL
If VDB < VTL, there is no PWM output.
.
TH − VTL
R2
R1 + R2
VDB = Vref ×
Note: VDB is the voltage at the DB pin.
VTH: 1.6 V (Typ)
VTL: 1.0 V (Typ)
Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V.
Sawtooth
wave
Sawtooth wave
Voltage at DB pin
To Vref
R1
PWM
COMP
VTH
VDB
−
+
+
E/O
DB
VDB
VTL
Dead band
from
UVL
R2
Note: VTH and VTL vary depending on the oscillator.
Select constants by testing under implementation
conditions.
Figure 3.1 Dead-Band Duty Cycle Setting
Rev.2.0, Sep.18.2003, page 10 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
3.2 Soft-Start Setting
Soft-start avoids overshoot at power-up by widening the PWM output pulses gradually, so that the
converted DC output rises slowly. Soft-start is programmed by connecting a capacitor between the DB pin
and ground. The soft-start time is determined by the time constant of this capacitor and the resistors that set
the voltage at the DB pin.
VX
VDB
tsoft = −C1 × R × ln (1 −
R1 × R2
)
R =
R1 + R2
R2
VDB = Vref ×
R1 + R2
Note: VX is the voltage at the DB pin after time t (VX < VDB).
Undervoltage
lockout released
Sawtooth wave
Sawtooth
wave
1.6 V
VTH
VDB
To Vref
R1
PWM
COMP
−
+
+
E/O
VTL
VX
C1
DB
1.0 V
VX
from
UVL
R2
UVL sink
transistor
t
Soft-start time
tsoft
Figure 3.2 Soft-Start Setting
3.3 Quick Shutdown
The quick shutdown function resets the voltages at all pins when the IC is turned off, to assure that PWM
pulse output stops quickly. Since the UVL pull-down resistor in the IC remains on even when the IC is
turned off, the sawtooth wave output, error amplifier output, and DB pin are all reset to low voltage.
This feature helps in particular to discharge capacitor C1 in figure 3.2, which has a comparatively large
capacitance. In intermittent mode (explained on a separate page), this feature enables the IC to soft-start in
each on-off cycle.
Rev.2.0, Sep.18.2003, page 11 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
4. PWM Output Circuit and Power MOSFET Driving Method
These ICs have built-in totem-pole push-pull drive circuits that can drive a power MOS FET as shown in
figure 4.1. The power MOS FET can be driven directly through a gate protection resistor.
If VIN exceeds the gate breakdown voltage of the power MOS FET additional protective measures should be
taken, e.g. by adding Zener diodes as shown in figure 4.2.
To drive a bipolar power transistor, the base should be protected by voltage and current dividing resistors as
shown in figure 4.3.
VIN
To CL
Example:
P-channel power MOSFET
RG
OUT
Bias
circuit
Gate protection
resistor
VO
Totem-pole output circuit
P.GND
Figure 4.1 Connection of Output Stage to Power MOS FET
VIN
VO
RG
OUT
GND
DZ
Example: N-channel power MOSFET
Figure 4.2 Gate Protection by Zener Diodes
VIN
Base current
limiting resistor
VO
OUT
GND
Base discharging resistor
Example: NPN power transistor
Figure 4.3 Driving a Bipolar Power Transistor
Rev.2.0, Sep.18.2003, page 12 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
5. Voltage Reference (Vref = 2.5 V)
5.1 Voltage Reference
A bandgap reference built into the IC (see figure 5.1) outputs 2.5 V ± 50 mV. The sawtooth oscillator,
PWM comparator, latch, and other internal circuits are powered by this 2.5 V and an internally-generated
voltage of approximately 3.2 V.
The voltage reference section shut downs when the IC is turned off at the ON/OFF pin as described later,
saving current when the IC is not used and when it operates in intermittent mode during overcurrent.
VIN
ON/
−
+
3.2 V
Vref
1.25 V
2.5 V
25 kΩ
25 kΩ
Sub bandgap circuit
1.25 V
ADJ
Main bandgap circuit
Figure 5.1 Vref Reference Circuit
5.2 Trimming the Reference Voltage (Vref and ADJ pins)
Figure 5.2 shows a simplified circuit equivalent to figure 5.1. The ADJ pin in this circuit is provided for
trimming the reference voltage (Vref). The output at the ADJ pin is a voltage VADJ of 1.25 V (Typ)
generated by the bandgap circuit. Vref is determined by VADJ and the ratio of internal resistors R1 and R2 as
follows:
R1 + R2
Vref = VADJ
×
R2
The design values of R1 and R2 are 25 kΩ with a tolerance of ±25%.
If trimming is not performed, the ADJ pin open can be left open.
VIN
Vref
25 kΩ
(typ)
R1
−
ADJ
+
25 kΩ
(typ)
R2
VBG (bandgap voltage)
1.25 V (typ)
Figure 5.2 Simplified Diagram of Voltage Reference Circuit
Rev.2.0, Sep.18.2003, page 13 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
The relation between Vref and the ADJ pin enables Vref to be trimmed by inserting one external resistor
(R3) between the Vref and ADJ pins and another (R4) between the ADJ pin and ground, to change the
resistance ratio. Vref is then determined by the combined resistance ratio of the internal R1 and R2 and
external R3 and R4.
RA + RB
Vref = VADJ
×
RB
Where, RA: parallel resistance of R1 and R3
RB: parallel resistance of R2 and R4
Although Vref can be trimmed by R3 or R4 alone, to decrease the temperature dependence of Vref it is
better to use two resistors having identical temperature coefficients. Vref can be trimmed in the range of
2.5 V ± 0.2 V. Outside this range, the bandgap circuit will not operate and the IC may shut down.
Vref
R1 R3
RA =
R3
R4
R1
R2
R1 + R3
ADJ
External
resistors
Internal
resistors
R2 R4
RB =
R2 + R4
Figure 5.3 Trimming of Reference Voltage
5.3 Vref Undervoltage Lockout and Overvoltage Protection
The undervoltage lockout (UVL) function turns off PWM pulse output when the input voltage (VIN) is low.
In these ICs, this is done by monitoring the Vref voltage, which normally stays constant at approximately
2.5 V. The UVL circuit operates with hysteresis: it shuts PWM output off when Vref falls below 1.7 V,
and turns PWM output back on when Vref rises above 2.0 V. Undervoltage lockout also provides
protection in the event that Vref is shorted to ground.
The overvoltage protection circuit shuts PWM output off when Vref goes above 6.8 V. This provides
protection in case the Vref pin is shorted to VIN or another high-voltage source.
PWM
output
PWM
output
off
PWM output on
PWM output off
Vref(V)
Figure 5.4 Vref Undervoltage Lockout and Overvoltage Protection
1.7 2.0 2.5
5.0
6.8
10
UVL Voltage Vref (V typ) VIN (V typ)
Description
VH
VL
2.0 V
1.7 V
3.6 V
3.3 V
VIN increasing: UVL releases; PWM output starts
VIN decreasing: undervoltage lockout; PWM output stops
Rev.2.0, Sep.18.2003, page 14 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
6. Usage of ON/OFF Pin
This pin is used for the following purposes:
•
•
•
To shut down the IC while its input power remains on (power management)
To externally alter the UVL release voltage
With the timer (TM) pin, to operate in intermittent mode during overcurrent (see next section)
6.1 Shutdown by ON/OFF Pin Control
The IC can be shut down safely by bringing the voltage at the ON/OFF pin below about 0.7 V (the internal
VBE value). This feature can be used in power supply systems to save power. When shut down, the
HA16114 draws a maximum current (IOFF) of 10 µA, while the HA16120 draws a maximum 150 µA. The
ON/OFF pin sinks 290 µA (Typ) at 5 V, so it can be driven by TTL and other logic ICs. If intermittent
mode will also be employed, use a logic IC with an open-collector or open-drain output.
IIN
VIN
RA
RB
VIN
External logic IC
To other circuitry
Off On
TM
ON/
To latch
10 kΩ
3VBE
Q1
Vref
Vref
output
reference
Switch
CON/
+
−
Q2
Q3
On/off hysteresis circuit
GND
HA16114,
HA16120
Figure 6.1 Shutdown by ON/OFF Pin Control
6.2 Adjustment of UVL Voltages (when not using intermittent mode)
These ICs permit external adjustment of the undervoltage lockout voltages. The adjustment is made by
changing the undervoltage lockout thresholds VTH and VTL relative to VIN, using the relationships shown in
the accompanying diagrams.
When the IC is powered up, transistor Q3 is off, so VON is 2VBE, or about 1.4 V. Connection of resistors RC
and RD in the diagram makes undervoltage lockout release at:
RC + RD
VIN = 1.4 V ×
RD
This VIN is the supply voltage at which undervoltage lockout is released. At the release point Vref is still
below 2.5 V. To obtain Vref = 2.5 V, VIN must be at least about 4.3 V.
Since V
operates in relation to the base-emitter voltage of internal transistors, V has a temperature
ON
ON/OFF
coefficient of approximately –4 mV/°C. Keep this in mind when designing the power supply unit.
When undervoltage lockout and intermittent mode are both used, the intermittent-mode time constant is
shortened, so the constants of external components may have to be altered.
Rev.2.0, Sep.18.2003, page 15 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
IIN
VIN
VIN
TM
(open)
To other circuitry
Vref output
RC
To latch
ON/
Q1
Vref
10 kΩ
3VBE
GND
generation
circuit
RD
Q3
Q2
On/off hysteresis circuit
3
2.5 V
VIN ≥ 4.5 V
2
1
0
Vref
VOFF
0.7 V
VON
1.4 V
0
1
2
3
4
5
VON/
Figure 6.2 Adjustment of UVL Voltages
7. Timing of Intermittent Mode during Overcurrent
7.1 Principle of Operation
These ICs provide pulse-by-pulse overcurrent protection by sensing the current during each pulse and
shutting off the pulse if overcurrent is detected. In addition, the TM and ON/OFF pins can be used to
operate the IC in intermittent mode if the overcurrent state continues. A power supply with sharp settling
characteristics can be designed in this way.
Intermittent mode operates by making use of the hysteresis of the ON/OFF pin threshold voltages VON and
VOFF (VON – VOFF = VBE). The timing can be programmed as explained below.
When not using intermittent mode, leave the TM pin open, and pull the ON/OFF pin up to VON or higher.
The VBE is base emitter voltage of internal transistors.
VIN
RA
Current
Latch limiter
390 kΩ
CL
S
R
TM
Q
2.2 kΩ
2.2 µF
RB
ON/OFF
Vref
reference
+
CON/
−
Figure 7.1 Connection Diagram (example)
Rev.2.0, Sep.18.2003, page 16 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
7.2 Intermittent Mode Timing Diagram (V
only)
ON/OFF
*1
3VBE
c
c
2VBE
VON/
On
On
Off
VBE
0 V
IC is on
a
IC is off
b
t
TON
2TON
a. Continuous overcurrent is detected
TOFF
b. Intermittent operation starts (IC is off)
c. Voltage if overcurrent ends (thick dotted line)
Note: 1. VBE is the base-emitter voltage of internal transistors, and is approximately 0.7 V.
(See the figure 6.1.)
For details, see the overall waveform timing diagram.
Figure 7.2 Intermittent Mode Timing Diagram (V
only)
ON/OFF
7.3 Calculation of Intermittent Mode Timing
Intermittent mode timing is calculated as follows.
(1) TON (time until the IC shuts off when continuous overcurrent occurs)
1
2VBE
VBE
T
ON = CON/
= CON/
≈ 0.69 × CON/
× RB × ln
×
1 − On duty*
1
× RB × ln2 ×
× RB
1 − On duty*
1
1 − On duty*
×
(2) TOFF (time from when the IC shuts off until it next turns on)
V
IN − VBE
TOFF = CON/
× (RA + RB) × ln
VIN − 2VBE
Where VBE ≈ 0.7 V
The greater the overload, the sooner the pulse-by-pulse current limiter operates, the smaller tON becomes,
and from the first equation (1) above, the smaller TON becomes. From the second equation (2), TOFF depends
on VIN. Note that with the connections shown in the diagram, when VIN is switched on the IC does not turn
on until TOFF has elapsed.
Dead-band voltage
Sawtooth wave
Point at which the current
limiter operates
PWM output
(In case of HA16114)
tON
On duty =
× 100 (%)
tON
T
Where T = t/fOSC
T
Note: On duty is the percent of time the IC output is on during one PWM cycle
when the pulse-by-pulse current limiter is operating.
Figure 7.3
Rev.2.0, Sep.18.2003, page 17 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
7.4 Examples of Intermittent Mode Timing (calculated values)
8
6
4
2
0
(1) TON
TON = T1 × CON/
× RB
Here, coefficient
1
T1 = 0.69 ×
1 − On duty
from section 7.3 (1) previously.
T1
Example: If CON/
= 2.2 µF,
RB = 2.2 kΩ, and the on duty
of the current limiter is 75%,
then TON = 13 ms.
0
20
40
60
80
100
(PWM) On duty (%)
Figure 7.4 Examples of Intermittent Mode Timing (1)
(2) TOFF
TOFF = T2 × CON/
× (RA + RB)
0.1
Here, coefficient
IN − VBE
IN − 2VBE
V
V
T2 = ln
T2
0.05
from section 7.3 (2) previously.
Example: If CON/
RA = 390 kΩ, VIN = 12 V,
then TOFF = 55 ms.
= 2.2 µF, RB = 2.2 kΩ,
0
0
10
20
VIN (V)
30
40
Figure 7.5 Examples of Intermittent Mode Timing (2)
Rev.2.0, Sep.18.2003, page 18 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Sawtooth wave VCT
Dead band VDB
Example of step-up circuit
VIN
CF
RF
RCS
Error output VE/O
PWM pulse output
(In case of HA16120)
CL
Inductor
L
IC
OUT
VOUT
Power MOS FET
drain current (ID)
(dotted line shows
inductor current)
ID
F.B.
VIN
Determined by L and VIN
Determined by RCS and RF
Current limiter
pin (CL)
V
TH (CL)
V
IN − 0.2 V
Figure 7.6
8. Setting the Overcurrent Detection Threshold
The voltage drop VTH at which overcurrent is detected in these ICs is typically 0.2 V. The bias current is
typically 200 µA. The power MOS FET peak current value before the current limiter goes into operation is
given as follows.
V
TH − (RF + RCS) × IBCL
ID
=
RCS
Where, VTH = VIN – VCL = 0.2 V, VCL is a voltage refered on GND.
Note that RF and CF form a low-pass filter with a cutoff frequency determined by their RC time constant.
This filter prevents incorrect operation due to current spikes when the power MOS FET is switched on or
off.
VIN
CF
1800 pF
IBCL
RCS
VIN
0.05 Ω
To other
circuitry
RF
CL
240 Ω
G
OUT
1 k
S
Detector
200 µA
D
VO
output
(internal)
+
−
−
+
IN(−)
Note: This circuit is an example for step-down use.
Figure 8.1 Example for Step-Down Use
With the values shown in the diagram, the peak current is:
0.2 V − (240 Ω + 0.05 Ω) × 200 µA
0.05 Ω
ID
=
= 3.04 A
The filter cutoff frequency is calculated as follows:
1
1
fC
=
=
= 370 kHz
2π CF RF 6.28 × 1800 pF × 240 Ω
Rev.2.0, Sep.18.2003, page 19 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Absolute Maximum Ratings
(Ta = 25°C)
Rating
HA16114P/FP,
HA16120FP
HA16114PJ/FPJ,
HA16120FPJ
Item
Symbol
Unit
Supply voltage
VIN
40
40
V
Output current (DC)
Output current (peak)
IO
±0.1
±0.1
A
IO peak
±1.0
±1.0
A
Current limiter input voltage VCL
Error amplifier input voltage VIEA
VIN
VIN
V
VIN
VIN
V
E/O input voltage
RT source current
TM sink current
VIE/O
IRT
Vref
Vref
V
500
500
µA
mA
V
ITM
3
3
SYNC voltage
VSYNC
ISYNC
PT
Vref
Vref
SYNC current
±250
680*1, *2
–40 to +85
125
±250
680*1, *2
–40 to +85
125
µA
mW
°C
°C
°C
Power dissipation
Operating temperature
Junction temperature
Storage temperature
Topr
TjMax
Tstg
–55 to +125
–55 to +125
Notes: 1. This value is for an SOP package (FP) and is based on actual measurements on a 40 × 40 × 1.6
mm glass epoxy circuit board. With a 10% wiring density, this value is permissible up to Ta =
45°C and should be derated by 8.3 mW/°C at higher temperatures. With a 30% wiring density,
this value is permissible up to Ta = 64°C and should be derated by 11.1 mW/°C at higher
temperatures.
2. For the DIP package. (P)
This value applies up to Ta = 45°C; at temperatures above this, 8.3 mW/°C derating should be
applied.
800
10% wiring density
680 mW
30% wiring density
600
447 mW
400
348 mW
200
45°C
64°C
85°C
125°C
0
−40
−20
0
20
40
60
80
100
120
140
Operating ambient temperature Ta (°C)
Rev.2.0, Sep.18.2003, page 20 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item
Symbol
Vref
Min
2.45
—
Typ
2.50
2
Max
2.55
60
Unit
V
Test Conditions
IO = 1 mA
Notes
Voltage
reference
section
Output voltage
Line regulation
Load regulation
Line
mV
mV
mA
4.5 V ≤ VIN ≤ 40V
0 ≤ IO ≤ 10 mA
Vref = 0 V
1
Load
IOS
—
30
60
Short-circuit output
current
10
24
—
Vref overvoltage
protection threshold
Vrovp
6.2
—
6.8
7.4
V
Temperature stability
of output voltage
∆Vref/∆Ta
VADJ
100
—
ppm/°C
V
Vref adjustment
voltage
1.225 1.25
1.275
Sawtooth
oscillator
section
Maximum frequency
Minimum frequency
fmax
fmin
∆f/f01
600
—
—
—
±1
—
1
kHz
Hz
%
Frequency stability
with input voltage
—
±3
4.5 V ≤ VIN ≤ 40 V
(f01 = (fmax + fmin)/2)
Frequency stability
with temperature
∆f/f02
fOSC
—
±5
—
%
–20°C ≤ Ta ≤ 85°C
(f02 = (fmax + fmin)/2)
Oscillator frequency
90
100
1.0
1.6
110
1.1
1.7
kHz
V
RT = 10 kΩ
CT = 1300 pF
Dead-band
adjustment
section
Low level threshold
voltage
VTL
0.9
1.5
Output duty cycle:
0% on
High level threshold
voltage
VTH
V
Output duty cycle:
100% on
Threshold difference
∆VTH
0.5
170
0.9
0.6
250
1.0
0.7
330
1.1
V
∆VTH = VTH – VTL
Output source current Isource
µA
V
DB pin: 0 V
PWM
Low level threshold
voltage
VTL
Output duty cycle:
0% on
comparator
section
High level threshold
voltage
VTH
1.5
0.5
1.6
0.6
1.7
0.7
V
V
Output duty cycle:
100% on
Threshold difference
∆VTH
∆VTH = VTH – VTL
Note: 1. Resistors connected to ON/OFF pin:
VIN pin
10
12
13
390 kΩ
2 kΩ
TM pin
ON/
pin
Rev.2.0, Sep.18.2003, page 21 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item
Symbol
VIO
Min
—
Typ
2
Max
10
Unit
mV
µA
Test Conditions
Notes
Error
Input offset voltage
Input bias current
Output sink current
amplifier
section
IB
—
0.5
40
40
2.0
52
IOsink
28
28
µA
VO = 2.5 V
VO = 1.0 V
Output source
current
IOsource
52
µA
Common-mode
VCM
1.1
—
3.7
V
input voltage range
Voltage gain
AV
40
—
50
4
—
—
dB
f = 10 kHz
Unity gain
bandwidth
BW
MHz
High level output
voltage
VOH
VOL
3.5
—
4.0
0.2
—
V
V
IO = 10 µA
IO = 10 µA
Low level output
voltage
0.5
Overcurrent
detection
section
Threshold voltage
CL(–) bias current
Turn-off time
VTH
VIN–0.22
140
—
VIN–0.2
200
VIN–0.18
260
V
IBCL(–)
tOFF
µA
ns
ns
V
CL(–) = VIN
200
300
1
2
—
500
600
UVL section
Vref high level
VTH
VTL
1.7
2.0
2.3
threshold voltage
Vref low level
threshold voltage
1.4
0.1
3.3
3.0
1.7
0.3
3.6
3.3
2.0
0.5
3.9
3.6
V
V
V
V
Threshold
difference
∆
∆VTH = VTH – VTL
VTH
VIN high level
VINH
VINL
threshold voltage
VIN low level
threshold voltage
Notes: 1. HA16114 only.
2. HA16120 only.
Rev.2.0, Sep.18.2003, page 22 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item
Symbol
VOL
Min
Typ
Max
1.5
—
Unit
V
Test Conditions
IOsink = 10 mA
Notes
Output
stage
Output low voltage
Output high voltage
High voltage when off
—
0.9
VOH1
VIN–2.2
VIN–2.2
VIN–1.6
VIN–1.6
V
IOsource = 10 mA
VOH2
—
V
IOsource = 1 mA
ON/OFF pin: 0 V
1
2
Low voltage when off
VOL2
—
0.9
1.5
V
IOsink = 1 mA
ON/OFF pin: 0 V
Rise time
tr
—
50
50
200
ns
CL = 1000 pF
CL = 1000 pF
SYNC pin: 0 V
Fall time
tf
—
200
ns
External
sync
SYNC source current
ISYNC
fSYNC
120
fOSC
180
—
240
µA
kHz
Sync input
fOSC × 2
section
frequency range
External sync
initiation voltage
VSYNC
PWmin
PW
Vref–1.0
—
—
—
Vref–0.5
V
Minimum pulse width
of sync input
300
5
—
ns
%
Input sync pulse
duty cycle
50
3
On/off
ON/OFF sink current 1
ON/OFF sink current 2
IC on threshold
I
60
90
120
380
1.7
1.0
0.9
µA
µA
V
ON/OFF pin: 3 V
ON/OFF pin: 5 V
ON/ OFF 1
section
I
220
1.1
0.4
0.5
290
1.4
0.7
0.7
ON/ OFF 2
VON
IC off threshold
VOFF
V
ON/OFF threshold
∆V
V
ON/OFF
difference
Total
device
Operating current
Quiescent current
IIN
6.0
0
8.5
—
11.0
10
mA
µA
µA
CL = 1000 pF
IOFF
ON/OFF pin: 0 V
ON/OFF pin: 0 V
1
2
—
120
150
Notes: 1. HA16114 only.
2. HA16120 only.
3. PW = t1 / t2 × 100
External
sync pulse
t1
t2
Rev.2.0, Sep.18.2003, page 23 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Characteristic Curves
Reference Voltage vs. Supply Voltage
Reference Voltage vs. Ambient Temperature
4.0
2.54
2.52
2.50
2.48
2.46
Ta = 25°C
VIN = 12 V
2.55 max
3.0
2.5V
2.0
1.0
0.0
SPEC
2.45 min
0
1
2
3
4
5
40
−20
0
20
40
60
80
4.3V
Supply voltage (V)
Ambient temperature (°C)
Low Level Threshold Voltage of Sawtooth Wave vs.
High Level Threshold Voltage of Sawtooth Wave vs.
Frequency
Frequency
2.5
2.5
Ta = 25°C
Ta = 25°C
V
IN = 12 V
V
IN = 12 V
RT = 10 kΩ
RT = 10 kΩ
2.0
1.5
1.0
0.5
0.0
2.0
1.5
1.0
0.5
0.0
100
200
300
400
500
600
100
200
300
400
500
600
Frequency (kHz)
Frequency (kHz)
Rev.2.0, Sep.18.2003, page 24 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Oscillator Frequency Change
with Ambient Temperature (1)
Oscillator Frequency Change
with Ambient Temperature (2)
10
10
5
VIN = 12 V
VIN = 12 V
fOSC = 350 kHz
f
OSC = 100 kHz
5
0
SPEC
0
−5
−5
−10
−10
−20
0
20
40
60
80
−20
0
20
40
60
80
Ambient temperature (°C)
Ambient temperature (°C)
Error Amplifier Gain, Error Amplifier Phase vs. Error Amplifier Input Frequency
60
AVO
40
20
0
0
φ
45
90
135
180
BW
3 M
1 k
3 k
10 k
30 k
100 k
300 k
1 M
10 M
Error amplifier input frequency fIN (Hz)
Rev.2.0, Sep.18.2003, page 25 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Current Limiter Turn-Off Time vs.
Current Limiter Threshold Voltage Note
Error Amplifier Voltage Gain vs. Ambient Temperature
60
500
400
300
200
100
VIN = 12 V
f = 10 kHz
• HA16114
Ta = 25°C
IN = 12 V
CL = 1000 pF
V
55
50 dB typ
50
300 ns max
45
40 dB min
40
40
−20
0
20
60
80
0.1
0.2
0.3
0.4
0.5
Ambient temperature (°C)
CL voltage VIN−VCL (V)
Note: Approximatery 300 ns greater than this
in the case of the HA16120.
Current Limiter Threshold Voltage vs.
Ambient Temperature
Current Limiter Turn-Off Time vs.
Ambient Temperature Note
0.22
300
0.22 max
300 ns max
VIN = 12 V
• HA16114
0.21
0.20
0.19
0.18
250
200
150
100
200 ns typ
VIN = 12 V
V
CL = 1000 pF
CL = VTH − 0.3 V
0.18 min
40
−20
0
20
60
80
−20
0
20
40
60
80
Ambient temperature (°C)
Ambient temperature (°C)
Note: Approximatery 300 ns greater than this
in the case of the HA16120.
Rev.2.0, Sep.18.2003, page 26 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Reference Voltage vs. IC On/Off Voltages
IC On/Off Voltages vs. Ambient Temperature
2.0
5.0
Ta = 25°C
VIN = 12 V
V
IN = 12 V
f
OSC = 100 kHz
4.0
3.0
2.0
1.0
0.0
SPEC
1.5
1.0
0.5
0.0
IC on voltage
IC off voltage IC on voltage
SPEC
SPEC
SPEC
IC off voltage
0
0.5
1.0
1.5
2.0
2.5
−20
0
20
40
60
80
IC on/off voltage (V)
Ambient temperature (°C)
Peak Output Current vs. Load Capacitance
Operating Current vs. Supply Voltage
600
500
400
300
200
100
0
20
15
10
5
Ta = 25°C
Ta = 25°C
fOSC = 100 kHz
On duty = 50%
CL = 1000 pF
V
IN = 12 V
f
OSC = 100 kHz
SPEC
0
0
1000 2000 3000 4000 5000
Load capacitance (pF)
0
10
20
30
40
Supply voltage (V)
Rev.2.0, Sep.18.2003, page 27 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Operating Current vs. Output Duty Cycle
20
Ta = 25°C
V
IN = 12 V
OSC = 100 kHz
CL = 1000 pF
f
15
10
5
SPEC
0
0
20
40
60
80
100
Output duty cycle (%)
PWM Comparator Input vs. Output Duty Cycle (1)
PWM Comparator Input vs. Output Duty Cycle (2)
100
100
• HA16114
• HA16120
80
60
80
60
fOSC
600 kHz
40
40
fOSC
600 kHz
50 kHz
50 kHz
300 kHz
20
0
20
0
300 kHz
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VDB or VE/O (V)
VDB or VE/O (V)
Note: The on-duty of the HA16114 is the proportion
of one cycle during which output is low.
Note: The on-duty of the HA16120 is the proportion
of one cycle during which output is high.
Rev.2.0, Sep.18.2003, page 28 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Output pin (Output Resistor) Characteristics
12
11
10
9
• HA16114
VGS
(P-channel
Power MOS FET)
Output high voltage
when on
Output high voltage
when off
• HA16120
3
2
1
0
Output low voltage
when on
Output low voltage
when off
VGS
(N-channel
Power MOS FET)
0
2
4
6
8
10
Io sink or Io source (mA)
Rev.2.0, Sep.18.2003, page 29 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Output Waveforms: Rise of Output Voltage VOUT
15
10
VOUT
(V)
5
Vref DB CL(−) VIN
OUT
0
CL
400
200
0
1000 pF
IN(+) RT CT
IO
10 kΩ
1300 pF
IO
(mA)
Test Circuit
−200
−400
200 ns/div
Output Waveforms: Fall of Output Voltage VOUT
15
10
VOUT
(V)
5
Vref DB CL(−) VIN
0
OUT
CL
1000 pF
400
200
0
IN(+) RT CT
IO
10 kΩ
1300 pF
IO
(mA)
Test Circuit
−200
−400
200 ns/div
Rev.2.0, Sep.18.2003, page 30 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Oscillator Frequency vs. Timing Capacitance
1000
100
10
RT = 3kΩ
RT = 10kΩ
RT = 30kΩ
RT = 100kΩ
RT = 300kΩ
RT = 1MΩ
1
0.1
101
102
103
104
105
106
Timing capacitance CT (pF)
Rev.2.0, Sep.18.2003, page 31 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (1)
Rev.2.0, Sep.18.2003, page 32 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (2)
• External Synchronization with Primary-Control AC/DC Converter
(1) Combination with a flyback AC/DC converter (simplified schematic)
HRA83
Transformer
HRP24
SBD
Commer-
cial AC
1S2076A
+
+
1S2076A
−
D
+
+
Main DC
output
R1
−
R2
−
VIN
Error amp.
−
+
OUT
2
CL(CS)
10
11
VIN
CL
HA16114,
HA16120
GND OUT P.GND
1
9
8
Primary AC/DC converter IC
(HA16107, HA17384, etc.)
To A of SBD
2SJ296
SBD
+
Step-down
output
(HA16114)
+
K
A
Sub DC
output
−
−
HRP24
This is one example of a circuit that uses the features of the HA16114/120 by operating in
synchronization with a flyback AC/DC converter. Note the following design points concerning the
circuit from the secondary side of the transformer to the
pin of the HA16114/120.
• Diode D prevents reverse current. Always insert a diode here. Use a general-purpose switching
diode.
• Resistors R1 and R2 form a voltage divider to ensure that the input voltage swing at the
does not exceed Vref (2.5 V). To maintain operating speed, R1 + R2 should not exceed 10 kΩ.
pin
Rev.2.0, Sep.18.2003, page 33 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (3)
• External Synchronization with Primary-Control AC/DC Converter (cont.)
(2) Combination with a forward AC/DC converter (simplified schematic)
DFG1C8
D
HRW26F
HA17431 and optocoupler
+
Input
Main DC
output
Feedback
section
C
SBD
module
A
B
−
HA16107,
HA16666 etc.
FB
VIN
2SC458
R3
390Ω
2
10
R1
R2
6.2kΩ
Q
Switching transformer
SYNC
VIN
HA16114,
HA16120
GND
1
9
OUT
Coil A Primary, for main
Coil B Secondary, for output
Coil C Tertiary, for IC
Coil D For reset
ZD
Other parts as
on previous page
510Ω
This circuit illustrates the combination of the HA16114/120 with a forward AC/DC converter. The
HA16114/120 synchronizes with the falling edge of the external sync signal, so with a forward
transformer, the sync pulses must be inverted. In the diagram, this is done by an external circuit
consisting of the following components:
• Q:
Transistor for inverting the pulses. Use a small-signal transistor.
• R1 and R2: These resistors form a voltage divider for driving the base of transistor Q. R2 also provides
a path for base discharge, so that the transistor can turn off quickly.
• R3:
• ZD:
Load resistor for transistor Q.
Zener diode for protecting the
pin.
Rev.2.0, Sep.18.2003, page 34 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Overall Waveform Timing Diagram (for Application Example (1))
12 V
VIN
0 V
VTM
,
2.1 V
1.4 V
VON/
VTM
VON/
,
1.4 V
0.7 V
0.0 V
On
On
(V)
3.0
On
On
On
VE/O
Off Off Off Off
Off
VCT
sawtooth wave
2.0
1.0
0.0
VE/O
VCT
VDB
,
,
VDB
12 V
VCL
11.8 V
0 V
Pulse-by-pulse
current limiting
*1 12 V
VOUT
PWM
pulse
0 V
DC/DC output
(example for
positive
voltage)
Soft start
Steady state
Overcurrent
detected;
intermittent
operation
Overcurrent Quick
subsides;
steady-state
operation
shutdown
IC operation
status
Power-up IC on
Power supply off,
IC off
Note: 1. This PWM pulse is on the step-down/inverting control channel (HA16114).
The booster control channel (HA16120) output consists of alternating L and H of the IC on cycle.
Rev.2.0, Sep.18.2003, page 35 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (4) (Some Pointers on Use)
1. Inductor, Power MOS FET, and Diode Connections
1. Step-up topology
VIN
2. Step-down topology
VIN
CF
CF
RCS Applicable only
to HA16120
RCS Applicable only
to HA16114
RF
VIN
VIN
RF
CL
CL
OUT
VO
VO
OUT
GND
GND
FB
FB
3. Inverting topology
CF
4. Step-down/step-up (buck-boost) topology
CF
RCS
RCS
Applicable only
to HA16114
Applicable only
to HA16114
RF
RF
VIN
CL
VIN
CL
OUT
GND
OUT
VO
GND
FB
FB
Vref
2. Turning Output On and Off while the IC is On
To turn only one channel off, ground the DB pin or the E/O pin.
In the case of E/O, however, there will be no soft start
when the output is turned back on.
DB
E/O
OFF
Rev.2.0, Sep.18.2003, page 36 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Package Dimensions
As of January, 2003
19.20
20.00 Max
Unit: mm
16
9
8
1
1.3
1.11 Max
7.62
+ 0.13
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0˚
– 15
˚
Package Code
JEDEC
JEITA
DP-16
Conforms
Conforms
1.07 g
Mass (reference value)
As of January, 2003
Unit: mm
10.06
10.5 Max
9
8
16
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-16DA
—
JEITA
Mass (reference value)
Conforms
0.24 g
*Dimension including the plating thickness
Base material dimension
Rev.2.0, Sep.18.2003, page 37 of 37
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circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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Colophon 1.0
相关型号：
HA16114FP-EL
Switching Regulator, 600kHz Switching Freq-Max, PDSO16, 0.300 INCH, 1.27 MM PITCH, EIAJ, SOP-16
HITACHI
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