HA16114FPJ-E [RENESAS]
1A SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PDSO16, SOP-16;
| 型号： | HA16114FPJ-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1A SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PDSO16, SOP-16 转换器 稳压器 开关 |
| 文件： | 总34页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA16116FP/FPJ, HA16121FP/FPJ
Switching Regulator for Chopper Type DC/DC Converter
REJ03F0056-0200Z
(Previous: ADE-204-019A)
Rev.2.0
Sep.18.2003
Description
HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in
chopper-type DC/DC converters.
This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The
output logic is preset for booster, step-down, or inverting control in a DC/DC converter. This logic
assumes use of an N-channel power MOS FET for booster control, and a P-channel power MOS FET for
step-down or inverting control.
HA16116 includes a built-in logic circuit for step-down control only, and one for use in both step-down and
inverting control. HA16121 has a logic circuit for booster control only and one for both step-down and
inverting control.
Both ICs have a pulse-by-pulse current limiter, which limits PWM pulse width per pulse as a means of
protecting against overcurrent, and which uses an on/off timer for intermittent operation. Unlike
conventional methods that use a latch timer for shutdown, when the pulse-by-pulse current limiter
continues operation beyond the time set in the timer, the IC is made to operate intermittently (flickering
operation), resulting in sharp vertical setting characteristics. When the overcurrent condition subsides, the
output is automatically restored to normal.
The dual control circuits in the IC output identical triangle waveforms, for completely synchronous
configuring a compact, high efficiency dual-channel DC/DC converter, with fewer external components
than were necessary previously.
Functions
•
•
•
•
•
•
•
•
2.5 V reference voltage (Vref) regulator
Triangle wave form oscillator
Dual overcurrent detector
Dual totem pole output driver
UVL (under voltage lock out) system
Dual error amplifier
Vref overvoltage detector
Dual PWM comparator
Rev.2.0, Sep.18.2003, page 1 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Features
•
•
•
•
Wide operating supply voltage range* (3.9 V to 40.0 V)
Wide operating frequency range (600 kHz maximum operation)
Direct power MOS FET driving (output current ±1 A peak in maximum rating)
Pulse-by-pulse overcurrent protection circuit with intermittent operation function (When overcurrent
state continues beyond time set in timer, the IC operates intermittently to prevent excessive output
current.)
•
Grounding the ON/OFF pin turns the IC off, saving power dissipation. (HA16116: IOFF = 10 µA max.;
HA16121: IOFF = 150 µA max.)
•
•
Built-in UVL circuit (UVL voltage can be varied with external resistance.)
Built-in soft start and quick shutoff functions
Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V.
Ordering Information
Hitachi Control ICs for Chopper-Type DC/DC Converters
Product
Channel Control Functions
Overcurrent
Protection
Channels Number
No.
Output Circuits
Step-Up
Step-Down Inverting
Dual
HA17451 Ch 1
Ch 2
❍
❍
—
❍
—
—
—
❍
❍
❍
❍
—
❍
❍
❍
—
❍
❍
❍
—
❍
—
❍
—
Open collector
SCP with timer (latch)
Single
Dual
HA16114
HA16120
HA16116
—
Totem pole
Pulse-by-pulse
power MOS FET current limiter and
driver
—
intermittent operation
by on/off timer
Ch 1
Ch 2
Ch 1
Ch 2
HA16121
Rev.2.0, Sep.18.2003, page 2 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Pin Arrangement
1
2
*
*
S.GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S.VIN
Vref
TIM
CT
RT
IN(+)1
IN(−)1
E/O1
DB1
ON/
IN(−)2
E/O2
DB2
Channel 1
Channel 2
CL1
CL2
OUT1
OUT2
1
*
2
*
P. V IN
P.GND
(Top view)
1. Pins S.GND (pin 1) and P.GND (pin 10) have no direct internal interconnection.
Both pins must be connected to ground.
Notes:
2. Pins S.VIN (pin 20) and P.V IN(pin 11) have no direct internal interconnection.
Both pins must be connected to VIN.
Rev.2.0, Sep.18.2003, page 3 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Pin Functions
Pin No.
Symbol
S.GND
CT
Function
Signal circuitry*1 ground
1
2
Timing capacitance (triangle wave oscillator output)
Timing resistance (for bias current synchronization)
Error amp. noninverting input (1)
Error amp. inverting input (1)
Error amp. output (1)
3
RT
4
IN(+)1
IN(–)1
E/O1
DB1
Channel 1
5
6
7
Dead band timer off period adjustment input (1)
Overcurrent detection input (1)
PWM pulse output (1)
Output stage*1 ground
Output stage*1 power supply input
8
CL1
9
OUT1
P.GND
P.VIN
10
11
12
13
14
15
16
17
18
OUT2
CL2
PWM pulse output (2)
Channel 2
Overcurrent detection input (2)
Dead band timer off period adjustment input (2)
Error amp. output (2)
DB2
E/O2
IN(–)2
ON/OFF
TIM
Error amp. inverting input (2)*2
IC on/off switch input (off when grounded)
Setting of intermittent operation timing when overcurrent is detected
(collector input of timer transistor)
19
20
Vref
2.5 V reference voltage output
Signal circuitry*1 power supply input
S.VIN
Notes: 1. Here “output stage” refers to the power MOS FET driver circuits, and “signal circuitry” refers to all
other circuits on the IC. Note that this IC is not protected against reverse insertion, which can
cause breakdown of the IC between VIN and GND. Be careful to insert the IC correctly.
2. Noninverting input of the channel 2 error amp is connected internally to Vref.
Rev.2.0, Sep.18.2003, page 4 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Block Diagram
Rev.2.0, Sep.18.2003, page 5 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Function and Timing Chart
Relation between triangle wave and PWM output (in steady-state operation)
CT triangle wave
1.6 V typ
1.0 V typ
Dead band
voltage
E/O Error amp output
V
IN (on)
This pulse
Booster
channel
output
(HA16121-
Ch 2) only
is for
N-channel
power MOS
FET gate
driving.
tON
tOFF
GND (off)
PWM
pulse
output
T
Step-down
or inverting
output
(HA16116-
Ch 1, Ch 2/
HA16121-Ch 1)
This pulse
is for
P-channel
power MOS
FET gate
driving.
V
IN (off)
GND (on)
Note: On duty = tON/T, where T = 1/fOSC
.
Rev.2.0, Sep.18.2003, page 6 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Determining External Component Constants (pin usage)
Constant settings are explained for the following items.
S.GND
CT
1
2
3
4
5
6
7
8
9
20 S.VIN
19 Vref
18 TIM
Vref UVL and
OVP
5.
6.
Oscillator
frequency
(fOSC) setting
1.
Setting of inter-
mittent operation
timing when
overcurrent is
detected
RT
IN(+)1
IN(−)1
E/O1
DB1
17 ON/
16 IN(−)2
15 E/O2
14 DB2
13 CL2
12 OUT2
11 P. V IN
DC/DC converter
output voltage
setting and
2.
3.
4.
error amp usage
ON/
pin
7.
8.
Channel 1
Channel 2
usage
Dead band duty
and soft start
setting
Overcurrent
detection value
setting
CL1
Output stage
circuit and
power MOS FET
driving method
OUT1
P.GND 10
1. Oscillator Frequency (fOSC) Setting
Figure 1.1 shows an equivalent circuit for the triangle wave oscillator.
VH
(3.3 V
IC internal circuits)
Vref (2.5 V)
1.6 V typ
VL
1.0 V typ
CT charging
IO
RA
t1
t2
Comparator
RC
IO
Discharging
RB
CT
(external)
CT
1 : 2
1.1 V
RT
RT
(external)
Inside the IC
Figure 1.1 Equivalent Circuit for the Triangle Wave Oscillator
Rev.2.0, Sep.18.2003, page 7 of 33
HA16116FP/FPJ, HA16121FP/FPJ
The triangle wave is a voltage waveform used as a reference in creating a PWM pulse. This block operates
according to the following principles. A constant current IO, determined by an external timing resistor RT, is
made to flow continuously to external timing capacitor CT. When the CT pin voltage exceeds the
comparator threshold voltage VH, the comparator output causes a switch to operate, discharging a current IO
from CT. Next, when the CT pin voltage drops below threshold voltage VL, the comparator output again
causes the switch to operate, stopping the IO discharge. The triangle wave is generated by this repeated
operation.
Note that IO = 1.1 V/RT. Since the IO current mirror circuit has a very limited current producing ability, RT
should be set to ≥ 5 kΩ (IO ≥ 220 µA).
With this IC series, VH and VL of the triangle wave are fixed internally at about 1.6 V and 1.0 V by the
internal resistors RA, RB, and RC. The oscillator frequency can be calculated as follows.
1
fOSC
Here,
=
t1 + t2 + t3
CT (VH − VL)
CT RT (VH − VL)
t1 =
=
1.1 V/RT
1.1 V
CT (VH − VL)
(2 − 1) × 1.1 V/RT
CT RT (VH − VL)
t2 =
=
= t1
1.1 V
VH − VL = 0.6 V
0.6
t1 = t2 =
1.1
CT RT
t3 ≈ 0.8 µs (comparator delay time in the oscillator)
Accordingly,
1
1
fOSC
≈
[Hz]
≈
2t1 + t3
1.1 CT RT + 0.8 µs
Note that the value of fOSC may differ slightly from the above calculation depending on the amount of delay
in the comparator circuit. Also, at high frequencies this comparator delay can cause triangle wave
overshoot or undershoot, skewing the dead band threshold. Confirm the actual value in implementation
and adjust the constants accordingly.
Rev.2.0, Sep.18.2003, page 8 of 33
HA16116FP/FPJ, HA16121FP/FPJ
2. DC/DC Converter Output Voltage Setting and Error Amp Usage
2.1 Positive Voltage Booster (VO > VIN) or Step-Down (VIN > VO > Vref)
R1 + R2
Use VO
=
Vref (V)
R2
Booster output is possible only at channel 2 of HA16121. For step-down output, both channels of
HA16116 or channel 1 of HA16121 are used.
VO
Error amp.
R1
IN(−)1
−
CH1
CH2
IN(+)1 +
R2
VO
R1
IN(−)2
−
R2
+
Vref
2.5 V
Vref pin
(internal connection)
Figure 2.1
2.2 Negative Voltage (VO < Vref) for Inverting Output
R1
R1 + R2
R3 + R4
R3
Use VO = −Vref
− 1 (V)
Channel 1 is used for inverting output on both ICs.
Vref pin
Vref 2.5 V
R1
IN(−)1
−
CH1
R3
R4
R2
+
IN(+)2
Error amp
VO
Figure 2.2 Inverting Output
Rev.2.0, Sep.18.2003, page 9 of 33
HA16116FP/FPJ, HA16121FP/FPJ
2.3 Error Amplifier
Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier on these ICs is configured
of a simple NPN transistor differential input amplifier and the output circuit of a constant-current driver.
This amplifier features wide bandwidth (fT = 4 MHz) with open loop gain kept to 50 dB, allowing stable
feedback to be applied when the power supply is designed. Phase compensation is also easy.
Both HA16116 and HA16121 have a noninverting input (IN(+)) pin, in order to allow use of the channel 1
error amplifier for inverting control. The channel 2 error amplifier, on the other hand, is used for step-
down control in HA16116 and booster control in HA16121; so the channel 2 noninverting input is
connected internally to Vref.
IC internal VIN
IN(−)
E/O
IN(+)
To internal PWM
comparator
80 µA
40 µA
Figure 2.3 Error Amplifier Equivalent Circuit
3. Dead Band (DB) Duty and Soft Start Setting (common to both channels)
3.1 Dead Band Duty Setting
Dead band duty is set by adjusting the DB pin input voltage (VDB). A convenient means of doing this is to
connect two external resistors to the Vref of this IC so as to divide VDB (see figure 3.1).
R2
R1 + R2
VDB = Vref ×
Duty (DB) =
Here, T =
(V)
V
V
TH − VDB
TH − VTL
× 100 (%)
This applies when VDB > VTL
.
If VDB < VTL, there is no PWM output.
1
fOSC
Note: VTH: 1.6 V (Typ)
VTL: 1.0 V (Typ)
Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V.
Rev.2.0, Sep.18.2003, page 10 of 33
HA16116FP/FPJ, HA16121FP/FPJ
VTH
VE/O
VDB
1.6 V typ
To Vref
PWM
CT
VTL
1.0 V typ
VIN
VIN
comparator
−
+
+
R1
E/O
On
tON
VDB
Booster
channel
tOFF
DB
Off
Off
5k
GND
VIN
PWM
pulse
output
From UVL
CST
0.8V
R2
Step-down/
inverting
channel
On
GND
T
Figure 3.1 Dead Band Duty Setting
3.2 Soft Start (SST) Setting (each channel)
When the power is turned on, the soft start function gradually raises VDB (refer to section 3.1), and the
PWM output pulse width gradually widens. This function is realized by adding a capacitor CST to the DB
pin. The function is realized as follows.
In the figure 3.2, the DB pin is clamped internally at approximately 0.8 V, which is 0.2 V lower than the
triangle wave VTL = 1.0 V typ.
tA: Standby time until PWM pulse starts widening.
tB: Time during which SST is in effect.
During soft start, the DB pin voltage in the figure below is as expressed in the following equation.
−t − t0.8
VSST = VDB
Here,
t0.8 = −T ln
tSST = tA + tB
T
1 − e
,
0.8
T = CST (R1 // R2)
1 −
,
VDB
How to select values: If the soft start time tSST is too short, the DC/DC converter output voltage will tend to
overshoot. To prevent this, set tSST to a few tens of ms or above.
Rev.2.0, Sep.18.2003, page 11 of 33
HA16116FP/FPJ, HA16121FP/FPJ
V
(voltage)
VSST
Triangle wave
1.6 V
1.0 V
VTH
VTL
Starts from clamp
voltage of 0.8 V
PWM output
pulse starts to
widen
Steady-state
operation
0 V
VIN
t0.8
tA
tB
Booster
channel
0 V
VIN
PWM pulse
output
Step-down/
inverting
channel
0 V
VO
DC/DC converter output
(positive in this example)
0 V
t = 0 (here IC is on)
t = tSST
Figure 3.2 Soft Start (SST) Setting
Rev.2.0, Sep.18.2003, page 12 of 33
HA16116FP/FPJ, HA16121FP/FPJ
4. Totem Pole Output Stage Circuit and Power MOS FET Driving Method
The output stage of this IC series is configured of totem pole circuits, allowing direct connection to a power
MOS FET as an external switching device, so long as VIN is below the gate breakdown voltage.
If there is a possibility that VIN will exceed the gate breakdown voltage of the power MOS FET, a Zener
diode circuit like that shown figure 4.1 or other protective measures should be used. The figure 4.1 shows
an example using a P-channel power MOS FET.
P. V IN
E.g.: VIN = 18 V
Zener diode for
gate protection
Bias
circuit
OUT
Gate
protection
resistor
VO
+
−
Drive circuit
Schottky
barrier diode
Figure 4.1 P-channel Power MOS FET (example)
5. Vref Undervoltage Error Prevention (UVL) and Overvoltage Protection (OVP) Functions
5.1 Operation Principles
The reference voltage circuit is equipped with UVL and OVP functions.
•
•
UVL
In normal operation the Vref output voltage is fixed at 2.5 V. If VIN is lower than normal, the UVL
circuit detects the Vref output voltage with a hysteresis of 1.7 V and 2.0 V, and shuts off the PWM
output if Vref falls below this level, in order to prevent malfunction.
OVP
The OVP circuit protects the IC from inadvertent application of a high voltage from outside, such as if
VIN is shorted. A Zener diode (5.6 V) and resistor are used between Vref and GND for overvoltage
detection. PWM output is shut off if Vref exceeds approximately 7.0 V.
Note that the PWM output pulse logic and the precision of the switching regulator output voltage are not
guaranteed at an applied voltage of 2.5 V to 7 V.
Rev.2.0, Sep.18.2003, page 13 of 33
HA16116FP/FPJ, HA16121FP/FPJ
5.2 Quick Shutoff
When the UVL circuit goes into operation, a sink transistor is switched on as in the figure below, drawing
off the excess current. This transistor also functions when the IC is turned off, drawing off current from the
CT, E/O, and DB pins and enabling quick shutoff.
PWM
output
PWM
output
off
PWM output on
PWM
output off
On
Off
Vref (V)
1.7 2.0 2.5
5.0
7.0
When VIN is
low
Abnormal voltage
applied to Vref
Relation of Vref to UVL and OVP
Vref
VIN
Vref
2.0 V and
1.7 V
detection
Vref
generation
circuit
Internal
pulse
signal
line
ZD
5.6 V
UVL
OUT
OUT
R
Sink
transistor
10 kΩ
OVP
To other circuitry
Figure 5.1 Quick Shutoff
Rev.2.0, Sep.18.2003, page 14 of 33
HA16116FP/FPJ, HA16121FP/FPJ
6. Setting of Intermittent Operation Timing when Overcurrent is Detected
6.1 Operation Principles
The current limiter on this IC detects overcurrent in each output pulse, providing pulse-by-pulse
overcurrent protection by limiting pulse output whenever an overcurrent is detected. If the overcurrent
state continues, the TIM pin and ON/OFF pin can be used to operate the IC intermittently. As a result, a
power supply with sharp vertical characteristics can be configured.
The ON/OFF timing for intermittent operation makes use of the hysteresis in the ON/OFF pin threshold
voltage VON and VOFF, such that VON – VOFF = VBE. Setting method is performed as described on the
following pages. VBE is based-emitter voltage of internal transistor.
Note: When an overcurrent is detected in one channel of this IC but not the other, the pulse-by-pulse
current limiter still goes into operation on both channels. Also, when the intermittent operation
feature is not used, the TIM pin should be set to open state and the ON/OFF pin pulled up to high
level (above VON).
VIN
RA
Current
Latch limiter
390 kΩ
CL
S
R
TM
Q
4.7 kΩ
2.2 µF
RB
Vref
generation
circuit
ON/
+
CON/
−
Figure 6.1 Connection Diagram (example)
6.2 Intermittent Operation Timing Chart (V
only)
ON/OFF
*1
4VBE
c
c
3VBE
2VBE
VBE
VON/
On
On
Off
IC is on
IC is off
a
b
0 V
t
TON
2TON
TOFF
a. Continuous overcurrent detected
b. Intermittent operation starts (IC is off)
c. Overcurrent cleared (dotted line)
1.VBE is the base-emitter voltage in transistors on the IC, and is approximately 0.7 V
(see the figure 7.1).
Note:
For details, see the overall waveform timing diagram.
Figure 6.2 Intermittent Operation Timing Chart
Rev.2.0, Sep.18.2003, page 15 of 33
HA16116FP/FPJ, HA16121FP/FPJ
6.3 Calculating Intermittent Operation Timing
Intermittent operation timing is calculated as follows.
(1) TON time (the time until the IC is shut off when continuous overcurrent occurs)
3VBE
2VBE
1
TON = CON/
× RB × ln
×
1 − On duty*
1
1
= CON/
× RB × ln1.5 ×
0.4
C
ON/
R
× ×
B
≈
×
1 − On duty*
1 − On duty*
(2) TOFF time (when the IC is off, the time until it next goes on)
V
IN − 2VBE
IN − 3VBE
TOFF = CON/
(R + R )
× ln
A B
×
V
Where, VBE ≈ 0.7 V
Note: 1. On duty is the percent of time the IC is on during one PWM cycle when the pulse-by-pulse
current limiter is operating.
From the first equation (1) above, it is seen that the shorter the time TON when the pulse-by-pulse current
limiter goes into effect (resulting in a larger overload), the smaller the value TON becomes.
As seen in the second equation (2), TOFF is a function of VIN. Further, according to this setting, when VIN is
switched on, the IC goes on only after TOFF has elapsed.
Dead band voltage
Triangle wave
Point at which current
limiter operate
PWM output
(step-down channel)
tON
T
tON
On duty =
Where T = 1/fOSC
T
On duty is the percent of time the IC is on during one PWM cycle when
the pulse-by-pulse current limiter is operating.
Note:
Figure 6.3
Rev.2.0, Sep.18.2003, page 16 of 33
HA16116FP/FPJ, HA16121FP/FPJ
6.4 Examples of Intermittent Operation Timing (calculated values)
4
3
2
1
0
(1) TON
TON = T1 × CON/
× RB
Here, coefficient
1
T1 = 0.4 ×
1 − On duty
from section 6.3 (1) previously.
T1
Example: If CON/
= 2.2 µF,
RB = 4.7 kΩ, and the on duty
of the current limiter is 75%,
then TON = 16 ms.
0
20
40
60
80
100
(PWM) ON Duty (%)
Figure 6.4 Examples of Intermittent Operation Timing (1)
(2) TOFF
TOFF = T2 × CON/
× (RA + RB)
0.1
Here, coefficient
V
V
IN − 2VBE
IN − 3VBE
T2 = ln
T2
0.05
from section 6.3 (2) previously.
Example: If CON/
RA = 390 kΩ, VIN = 12 V,
then TOFF = 60 ms.
= 2.2 µF, RB = 4.7 kΩ,
0
0
10
20
VIN (V)
30
40
Figure 6.5 Examples of Intermittent Operation Timing (2)
Rev.2.0, Sep.18.2003, page 17 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Triangle wave VCT
Dead band VDB
Example of step-up circuit
VIN
CF
RF
RCS
Error output VE/O
PWM pulse output
(In case of HA16120)
CL
Inductor
L
IC
OUT
VOUT
Power MOS FET
drain current (ID)
(dotted line shows
inductor current)
ID
F.B.
VIN
Determined by L and VIN
Determined by RCS and RF
Current limiter
pin (CL)
VTH (CL)
VIN − 0.2 V
Figure 6.6
7. ON/OFF Pin Usage
7.1 IC Shutoff by the ON/OFF Pin
As shown in the figure 7.1, these ICs can be turned off safely by lowering the voltage at the ON/OFF pin to
below 2VBE. This feature is used to conserve the power in the power supply system. In off state the IC
current consumption (IOFF) is 10 µA (Max) for HA16116 and 150 µA (Max) for HA16121.
The ON/OFF pin can also be used to drive logic ICs such as TTL or CMOS with a sink current of 50 µA
(Typ) at an applied voltage of 5 V. When it is desired to employ this feature along with intermittent
operation, an open collector or open drain logic IC should be used.
VIN
IIN
RA
S.VIN
P. V IN
TIM
ON/
External logic IC
To output
stage
To latch
To other circuitry
Vref
Off On
Switch
RB
Q1
Vref
generation
circuit
50 kΩ
4 VBE
GND
output
Q2
Q3
+
−
CON/
Q4
HA16116,
HA16121
On/off hysteresis circuit
Figure 7.1 IC Shutoff by the ON/OFF Pin
Rev.2.0, Sep.18.2003, page 18 of 33
HA16116FP/FPJ, HA16121FP/FPJ
7.2 Adjusting UVL Voltage (when intermittent operation is not used)
The UVL voltage setting in this IC series can be adjusted externally as shown below.
Using the relationships shown in the figure, the UVL voltage in relation to VIN can be adjusted by changing
the relative values of VTH and VTL.
When the IC is operating, transistor Q4 is off, so VON = 3VBE ≈ 2.1 V. Accordingly, by connecting resistors
RC and RD, the voltage at which UVL is cancelled is as follows.
RC + RD
VIN = 2.1 V
×
RD
This VIN is simply the supply voltage at which the UVL stops functioning, so in this state Vref is still below
2.5 V. In order to restore Vref to 2.5 V, a VIN of approximately 4.3 V should be applied.
With this IC series, V
makes use of the VBE of internal transistors, so when designing a power supply
ON/OFF
system it should be noted that VON has a temperature dependency of around –6 mV/°C.
VIN
P. V IN
S.VIN
To output
stage
To other circuitry
Vref output
TIM
(open)
RC
To latch
ON/
Q1
Vref
generation
circuit
50 kΩ
RD
Q2
Q3
Q4
On/off hysteresis circuit
GND
2.5 V
3
V
IN ≥ 4.5 V
2
1
0
Vref
VOFF
1.4 V
VON
2.1 V
0
1
2
3
4
5
VON/
Figure 7.2 Adjusting UVL Voltage
Rev.2.0, Sep.18.2003, page 19 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Overcurrent Detection Value Setting
The overcurrent detection value VTH for this IC series is 0.2 V (Typ) and the bias current is 200 µA (Typ)
The power MOS FET peak current value before the current limiter goes into operation is derived from the
following equation.
V
TCL − (RF + RCS) IBCL
ID
=
RCS
Here VTH = VIN – VCL = 0.2 V, VCL is a voltage referd on GND.
Note that CF and RCS form a low-pass filter, determined by their time constants, that prevents malfunctions
from current spikes when the power MOS FET is turned on or off.
CF 1800 PF
IBCL
S.VIN
RCS
0.05 Ω
VIN
VCL
To other
circuitry
CL
RF
240 Ω
This circuit is an example
for step-down output use.
1 k
G
OUT
S
D
200 µA
VO
Detection
output
(internal)
+
− +
−
IN(−)
Figure 8.1 Example for Step-Down Use
The sample values given in this figure are calculated from the following equation.
0.2 V − (240 Ω + 0.05 Ω) × 200 µA
ID =
= 3.04 [A]
0.05 Ω
The filter cutoff frequency is calculated as follows.
1
1
fC =
=
= 370 [kHz]
2π CF RF
6.28 × 1800 pF × 240 Ω
Rev.2.0, Sep.18.2003, page 20 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Absolute Maximum Ratings
(Ta = 25°C)
Rating
HA16116FP,
HA16121FP
HA16116FPJ,
HA16121FPJ
Item
Symbol
Unit
Supply voltage
VIN
40
40
V
Output current (DC)
Output current (peak)
Current limiter pin voltage
Error amp input voltage
E/O input voltage
IO
±0.1
±0.1
A
IO peak
VCL
±1.0
±1.0
A
VIN
VIN
V
VIEA
VIE/O
IRT
VIN
VIN
V
Vref
Vref
V
RT pin source current
TIM pin sink current
Power dissipation*1
500
500
µA
mA
mW
°C
°C
°C
ITM
20
20
PT
680*1
–40 to +85
125
680*1
–40 to +85
125
Operation temperature range
Junction temperature
Storage temperature range
Topr
TjMax
Tstg
–55 to +125
–55 to +125
Note: 1. This value is based on actual measurements on a 40 × 40 × 1.6 mm glass epoxy circuit board.
At a wiring density of 10%, it is the permissible value up to Ta = 45°C, but at higher temperatures
this value should be derated by 8.3 mW/°C. At a wiring density of 30% it is the permissible value
up to Ta = 64°C, but at higher temperatures it should be derated by 11.1 mW/°C.
800
10% wiring density
680 mW
30% wiring density
600
447 mW
400
348 mW
200
45°C
64°C
85°C
125°C
0
−40
−20
0
20
40
60
80
100
120
140
Operating ambient temperature Ta (°C)
Rev.2.0, Sep.18.2003, page 21 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
Symbol
Min
2.45
—
Typ
2.50
30
Max
2.55
60
Unit
V
Test Conditions
IO = 1 mA
Reference
voltage
block
Output voltage
Line regulation
Load regulation
Vref
Line
Load
IOS
mV
mV
mA
4.5 V ≤ VIN ≤ 40 V
0 ≤ IO ≤ 10 mA
Vref = 0 V
—
30
60
Output shorting
current
10
25
—
Vref OVP voltage
Vrovp
6.2
—
6.8
7.0
—
V
Output voltage
temperature
dependence
∆Vref/∆Ta
100
ppm/°C
Triangle
wave
Maximum oscillator
frequency
fOSCmax
600
—
—
—
±1
±5
—
1
kHz
Hz
%
oscillator
block
Minimum oscillator
frequency
fOSCmin
Oscillator frequency
input voltage stability
∆fOSC/∆VIN
∆fOSC/∆Ta
—
±3
—
4.5 V ≤ VIN ≤ 40 V
–20°C ≤ Ta ≤ 85°C
Oscillator frequency
temperature stability
—
%
Oscillator frequency
fOSC
270
300
330
kHz
V
CT = 220 pF, RT = 10 kΩ)
Dead band
Low-level threshold
VTLDB
0.87
0.97
1.07
Output on duty 0%
adjust block voltage
High-level threshold
voltage
VTHDB
1.48
0.55
1.65
0.65
1.82
0.75
V
V
Output on duty 100%
Threshold differential
voltage
∆VTDB
∆VTH = VTH – VTL
Output source current
IOsource (DB)
VTLCMP
100
150
200
µA
DB pin = 0 V
PWM
Low-level threshold
voltage
0.87
0.97
1.07
V
Output on duty = 0%
comparator
block
High-level threshold
oltage
VTHCMP
1.48
0.55
–5
1.65
0.65
0
1.82
0.75
+5
V
Output on duty = 100%
∆VTH = VTH – VTL
Threshold differential
voltage
∆VTCMP
DBdev
V
Dead band precision
%
Deviation when
V
EO = (VTL + VTH)/2,
duty = 50 %
Rev.2.0, Sep.18.2003, page 22 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
Symbol
VIOEA
IBEA
Min
—
Typ
2
Max
10
2
Unit
mV
µA
Test Conditions
Error amp
block
Input offset voltage
Input bias current
Output sink current
—
0.8
40
IOsink (EA)
28
52
µA
In open loop,
VI = 3 V, VO = 2 V
Output source current
IOsource (EA)
28
40
52
µA
In open loop,
VI = 2 V, VO = 1 V
Voltage gain
AV
40
50
4
—
—
dB
MHz
V
f = 10 kHz
Unity gain band-width
High-level output voltage
Low-level output voltage
BW
VOHEA
VOLEA
VTCL
IBCL
3
2.2
—
3.0
0.2
—
IO = 10 µA
IO = 10 µA
0.5
V
Overcurrent Threshold voltage
VIN–0.22
150
—
VIN–0.2 VIN–0.18
V
detection
block
CL bias current
200
200
500
250
300
600
µA
ns
ns
CL = VIN
Operating time
tOFFCL
CL = VIN –0.3 V
—
Applies only to ch 2
of HA16121
Output
stage
Output low voltage
VOL1
—
—
—
—
0.7
1.6
1.0
1.6
2.2
1.9
1.3
1.9
V
V
V
V
IOsink = 10 mA
Applies only to HA16116
IOsink = 10 mA
Applies only to HA16121
IOsink = 0 mA
Applies only to HA16121
Off state low voltage
VOL2
IOsink = 1 mA
ON/OFF pin = 0 V
Applies only to ch 2
of HA16121
—
1.0
1.3
V
IOsink = 0 mA
ON/OFF = 0 V
Applies only to ch 2
of HA16121
Output high voltage
Off state high voltage
VOH1
VIN–1.9
VIN–1.3
VIN–1.9
VIN–1.6
VIN–1.0
VIN–1.6
—
—
—
V
V
V
IOsource = 10 mA
IOsource = 0 A
VOH2
IOsource = 1 mA
ON/OFF pin = 0 V
VIN–1.3
VIN–1.0
—
V
IOsource = 0 A
ON/OFF pin = 0 V
Rise time
Fall time
tr
tf
—
—
70
70
130
130
ns
ns
CL = 1000 pF (to VIN) *1, *2
CL = 1000 pF (to VIN) *1, *2
Rev.2.0, Sep.18.2003, page 23 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 300 kHz)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
UVL block
VIN high-level threshold
voltage
VTUH1
VTUL1
∆VTU1
VTUH2
VTUL2
3.3
3.6
3.9
V
VIN low-level threshold
voltage
3.0
0.1
1.7
1.4
0.1
3.3
0.3
2.0
1.7
0.3
3.6
0.5
2.3
2.0
0.5
V
V
V
V
V
VIN threshold differential
voltage
∆VTU1 = VTUH1 – VTUL1
Vref high-level threshold
voltage
Vref low-level threshold
voltage
Vref threshold differential ∆VTU2
∆VTU2 = VTUH2 – VTUL2
ON/OFF pin = 5 V
voltage
ON/OFF
block
ON/OFF pin sink current
IC on-state voltage
IC off-state voltage
I
—
35
50
µA
V
ON/OFF
VON
VOFF
∆V
1.8
1.1
0.5
2.1
1.4
0.7
2.4
1.7
0.9
V
ON/OFF threshold
differential voltage
V
ON/OFF
TIM block
TIM pin sink current in
steady state
ITIM1
ITIM2
IIN
0
—
10
20
µA
CL pin = VIN, VTIM = 0.3 V
CL pin = VIN – 0.3 V
TIM pin sink current at
overcurrent detection
10
15
mA
V
TIM = 0.3 V
Common
block
Operating current
Off current
6.0
8.5
11.0
0
8.5
11.1
15.7
20.5
10
mA
mA
mA
µA
CL = 0 pF (to VIN) *1, *2
12.1
15.7
—
CL = 500 pF (to VIN) *1, *2
CL = 1000 pF (to VIN) *1, *2
HA16116FP ON/OFF
IOFF
pin = 0 V
0
120
150
µA
HA16121FP
Notes: 1. CL is load capacitor for Power MOS FET’s gate, and CL = 1000 pF to GND in the case of
HA16121 – ch 2.
2. CL in channel 2 of HA16121 is connected to GND.
Rev.2.0, Sep.18.2003, page 24 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Characteristic Curves
•
Reference Voltage Block (Vref)
Reference Voltage vs. Power Supply Input Voltage
Vref Temperature Characteristics
3
2.54
2.52
2.50
2.48
2.46
Ta = 25°C
VIN = 12 V
RA = 390 kΩ
2.5 V
IO (Vref) = 1 mA
(Between the VIN
and ON/
pins)
2
1
UVL release: 3.6 V
UVL operate: 3.3 V
3.3 3.6 4.3
85
−20
0
20
40
60
80
100
0
1
2
3
4
5
40
Ambient temperature Ta (°C)
Power supply input voltage VIN (V)
Vref Load Regulation
3.0
2.5
2.0
1.50
0
Short
circuit
current
10
20
30
Output current IO sink (mA)
•
UVL (Low Input Voltage Malfunction Prevention) Block
Hysteresis Voltage Temperature Characteristics
4.5
High threshold voltage
4.0
3.5
3.0
2.5
Hysteresis
Low threshold voltage
−20
0
20
40
60
80
100
Ambient temperature Ta (°C)
Rev.2.0, Sep.18.2003, page 25 of 33
HA16116FP/FPJ, HA16121FP/FPJ
•
Triangle Wave Oscillator Block
RT pin Output Current Characteristics
1.1
Sawtooth Wave Amplitude vs. Oscillator Frequency
2.0
VTH
1.5
1.0
0.9
Sawtooth wave
amplitude
VTL
1.0
Note: Due to these characteristics, the dead
band and PWM comparator threshold
voltages change at high frequencies.
Reccomended
usage range
0.5
10 (RT ≈ 100 kΩ)
330 (RT ≈ 3 kΩ)
300 400
0.8
0
100 200
500
0
100
200
300
400
500 600
I
RT (µA)
(DC)
fOSC (kHz) (linear scale)
CT, RT Values (VIN = 12V) vs. Oscillator Frequency
100
70
50
30
20
600 kHz
10
7
5
3
10
20
30
50 70 100
200 300
500 700 1 M
Oscillator frequency fOSC (kHz)
Oscillator Frequency Temperature Stability
+10
+5
0
VIN = 12 V
A: fOSC = 300 kHz
B: fOSC = 600 kHz
B
A
A
B
−5
85
−10
−20
0
20
40
60
80
100
Ambient temperature Ta (°C)
Rev.2.0, Sep.18.2003, page 26 of 33
HA16116FP/FPJ, HA16121FP/FPJ
•
Error Amplifier Block
Open Loop Gain Characteristics
AVO
60
40
20
0
φ
45
90
135
180
BW
3 M
0
1 k
3 k
10 k
30 k
100 k
300 k
1 M
10 M
Error amplifier input frequency fIN (Hz)
Common Mode Input Characteristics
+100
0
−+EA
V
−
O
−100
−200
−300
+
VI
Vref
0
1
2
3
4
Input voltage VI (V)
•
On Duty Characteristics
On Duty Characteristics
On Duty Characteristics
100
80
60
40
20
0
100
80
60
40
20
0
Boost PWM output
(HA16121-2 ch)
Step-down
PWM output
(HA16116-1, 2ch
HA16121-1ch)
0.8
1.0
1.2
1.4
1.6
1.8
0.8
1.0
1.2
1.4
1.6
1.8
VDB or VE/O (V)
VDB or VE/O (V)
Notes: 1. The percentage of a single timing cycle
during which the output is low.
2. The percentage of a single timing cycle
during which the output is high.
Rev.2.0, Sep.18.2003, page 27 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Other Characteristics
•
Current Limiter Level Temperature Characteristics IC On Voltage and Off Voltage Temperature Characteristics
4
3
2
1
0
220
210
200
190
180
VON on voltage (about −6mV/°C)
85°C
85°C
V
OFF off voltage
(about −4mV/°C)
−20
0
20
40
60
80
100
−20
0
20
40
60
80
100
Ambient temperature Ta (°C)
Ambient temperature Ta (°C)
IIN vs. VIN Characteristics
Output pin (Output Resistor) Characteristics
12
40
30
20
10
VGS
(P-channel
Power
fOSC = 300 kHz
On duty: 50%
Ta = 25°C
Output high voltage when on
11
10
9
MOS FET)
Maximum
rating at
Output high voltage
when off (channels 1
and 2 in the HA16116
and channel 1 in the
HA16121)
Ta = 25°C:
680 mW
Load capacitance:
1000 pF/ch
500 pF/ch
3
2
1
No load
Output low voltage when on
Output low voltage
when off (channels 1
and 2 in the HA16121)
VGS
(N-channel
Power
MOS FET)
10
20
30
40
2
4
6
8
10
0
0
Power supply voltage VIN (V)
IO sink or IO source (mA)
Output Drive Circuit Power MOS FET
Direct Drive ability Data
Gate Drive Waveforms for the 2SJ214
800
600
400
200
0
VIN = 12 V
fOSC = 130 kHz
2SJ216
2SJ176
2SJ214
Drive voltage:
5 V/div
*
Drive current:
200 mA/div
1000
2000
3000
4000
Ciss (pF)
650 nsec/div
Note: The solid line is data measured with discrete
capacitances (for each channel of HA16116).
Note: * Measured using a current probe.
(The boost channel (channel 2 in the HA16121)
load is with respect to ground, and has
almost identical characteristics.)
Rev.2.0, Sep.18.2003, page 28 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (1)
Rev.2.0, Sep.18.2003, page 29 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Overall Waveform Timing Diagram (for Application Examples (1))
12 V
VIN
0 V
VTIM
,
2.8 V
2.1 V
VON/
VTIM
VON/
,
2.1 V
1.4 V
0 V
On
On
(V)
3.0
On
On
On
VE/O
Off Off Off Off
Off
VCT
triangle wave
2.0
1.0
0.0
VE/O
VCT
VDB
,
,
VDB
12 V
VCL
11.8 V
0 V
Pulse-by-pulse
current limiter
operates
*1 12 V
VOUT
PWM
pulse
0 V
DC/DC output
(example for
positive
voltage)
Soft start
Steady-state
operation
Overcurrent
detected;
Overcurrent Quick
cleared;
shut-off
IC operation
states
intermittent
operation
steady-state
operation
Power
supply on
IC on
Power supply off,
IC off
Note: 1.This PWM pulse is on the step-down/inverting control channel.
The booster control channel output consists of alternating L and H of the IC ÒonÓ cycle.
Rev.2.0, Sep.18.2003, page 30 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (2) (Some Pointers on Use)
1. Inductor, Power MOS FET, and Diode Connections
1. Booster specification
2. Step-down specification
VIN
VIN
CF
CF
RCS Applicable to
HA16116FP and
to channel 1
RCS Applicable only
to channel 2
RF
VIN
RF
VIN
CL
CL
of HA16121FP
of HA16121FP
OUT
VO
VO
OUT
GND
GND
FB
FB
3. Inverting specification
CF
4. Negative booster specification (Flyback transformer)
CF
RCS
RCS
Applicable only
to channel 1
Applicable only
to channel 1
RF
RF
VIN
VIN
CL
CL
OUT
OUT
VO
GND
GND
FB
FB
Vref
2. Turning Output On and Off while the IC is On
1. To turn only one channel off, ground the DB pin
or the E/O pin. In the case of E/O, however,
there will be no soft start when the output is
turned back on.
2. When only one channel is to be used,
the channel not used should be connected
as follows.
VIN
DB
CL
Connect CL to VIN.
+
Ground IN(+) and IN(−).
Leave other pins open.
IN
E/O
−
IN
GND
OFF
Rev.2.0, Sep.18.2003, page 31 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Application Examples (3)
Rev.2.0, Sep.18.2003, page 32 of 33
HA16116FP/FPJ, HA16121FP/FPJ
Package Dimensions
As of January, 2003
Unit: mm
12.6
13 Max
11
10
20
1
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.12 M
Package Code
JEDEC
FP-20DA
—
JEITA
Mass (reference value)
Conforms
0.31 g
*Dimension including the plating thickness
Base material dimension
Rev.2.0, Sep.18.2003, page 33 of 33
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
相关型号：
©2020 ICPDF网 联系我们和版权申明