HA16116_技术文档

HA16116FP/FPJ, HA16121FP/FPJ

Switching Regulator for Chopper Type DC/DC Converter

Description

HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in

chopper-type DC/DC converters.

This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The

output logic is preset for booster, step-down, or inverting control in a DC/DC converter. This logic

assumes use of an N-channel power MOS FET for booster control, and a P-channel power MOS FET for

step-down or inverting control.

HA16116 includes a built-in logic circuit for step-down control only, and one for use in both step-down

and inverting control. HA16121 has a logic circuit for booster control only and one for both step-down and

inverting control.

Both ICs have a pulse-by-pulse current limiter, which limits PWM pulse width per pulse as a means of

protecting against overcurrent, and which uses an on/off timer for intermittent operation. Unlike

conventional methods that use a latch timer for shutdown, when the pulse-by-pulse current limiter

continues operation beyond the time set in the timer, the IC is made to operate intermittently (flickering

operation), resulting in sharp vertical setting characteristics. When the overcurrent condition subsides, the

output is automatically restored to normal.

The dual control circuits in the IC output identical triangle waveforms, for completely synchronous

configuring a compact, high efficiency dual-channel DC/DC converter, with fewer external components

than were necessary previously.

Functions

•

2.5 V reference voltage (Vref) regulator

Triangle wave form oscillator

Dual overcurrent detector

Dual totem pole output driver

UVL (under voltage lock out) system

Dual error amplifier

Vref overvoltage detector

Dual PWM comparator

HA16116FP/FPJ, HA16121FP/FPJ

Features

•

Wide operating supply voltage range* (3.9 V to 40.0 V)

Wide operating frequency range (600 kHz maximum operation)

Direct power MOS FET driving (output current ±1 A peak in maximum rating)

Pulse-by-pulse overcurrent protection circuit with intermittent operation function (When overcurrent

state continues beyond time set in timer, the IC operates intermittently to prevent excessive output

current.)

•

Grounding the ON/OFF pin turns the IC off, saving power dissipation. (HA16116: I_OFF= 10 µA max.;

HA16121: I_OFF= 150 µA max.)

•

Built-in UVL circuit (UVL voltage can be varied with external resistance.)

Built-in soft start and quick shutoff functions

Note: The reference voltage 2.5 V is under the condition of V_IN≥ 4.5 V.

Ordering Information

Hitachi Control ICs for Chopper-Type DC/DC Converters

Product

Channel Control Functions

Overcurrent

Channels Number

No.

Step-Up

Step-Down

Inverting

Output Circuits

Protection

Dual

HA17451

Ch 1

Ch 2

—

❍

—

❍

—

❍

—

❍

—

❍

—

❍

—

❍

—

Open collector

SCP with timer (latch)

Single

Dual

HA16114

HA16120

HA16116

Totem pole

Pulse-by-pulse

—

power MOS FET current limiter and

Ch 1

Ch 2

Ch 1

Ch 2

driver

intermittent operation

by on/off timer

HA16121

2

HA16116FP/FPJ, HA16121FP/FPJ

Pin Arrangement

*2

S.GND^*1

CT

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

S.V_IN

Vref

RT

TIM

IN(+)1

IN(−)1

E/O1

ON/OFF

IN(−)2

E/O2

Channel 1

Channel 2

DB1

CL1

DB2

CL2

OUT1

P.GND^*1

OUT2

*2

P.V _IN

(top view)

1. Pins S.GND (pin 1) and P.GND (pin 10) have no direct internal interconnection.

Both pins must be connected to ground.

Notes:

2. Pins S.V (pin 20) and P.V_IN(pin 11) have no direct internal interconnection.

IN

Both pins must be connected to V_IN.

3

HA16116FP/FPJ, HA16121FP/FPJ

Pin Functions

Pin No.

Symbol

S.GND

C_T

Function

Signal circuitry*¹ground

1

2

Timing capacitance (triangle wave oscillator output)

Timing resistance (for bias current synchronization)

Error amp. noninverting input (1)

Error amp. inverting input (1)

Error amp. output (1)

3

R_T

4

IN(+)1

IN(–)1

E/O1

DB1

Channel 1

5

6

7

Dead band timer off period adjustment input (1)

Overcurrent detection input (1)

PWM pulse output (1)

Output stage*¹ground

Output stage*¹power supply input

8

CL1

9

OUT1

P.GND

P.V_IN

OUT2

CL2

10

11

12

13

14

15

16

17

18

PWM pulse output (2)

Channel 2

Overcurrent detection input (2)

Dead band timer off period adjustment input (2)

Error amp. output (2)

DB2

E/O2

IN(–)2

ON/OFF

TIM

Error amp. inverting input (2)*²

IC on/off switch input (off when grounded)

Setting of intermittent operation timing when overcurrent is detected

(collector input of timer transistor)

19

20

Vref

2.5 V reference voltage output

Signal circuitry*¹power supply input

S.V_IN

Notes: 1. Here “output stage” refers to the power MOS FET driver circuits, and “signal circuitry” refers to all

other circuits on the IC. Note that this IC is not protected against reverse insertion, which can

cause breakdown of the IC between V_INand GND. Be careful to insert the IC correctly.

2. Noninverting input of the channel 2 error amp is connected internally to Vref.

4

HA16116FP/FPJ, HA16121FP/FPJ

Block Diagram

5

HA16116FP/FPJ, HA16121FP/FPJ

Function and Timing Chart

Relation between triangle wave and PWM output (in steady-state operation)

C_Ttriangle wave

1.6 V typ

1.0 V typ

Dead band

voltage

E/O Error amp output

V_IN(on)

This pulse

Booster

channel

output

(HA16121-

Ch 2) only

is for

N-channel

power MOS

FET gate

driving.

t_ON

t_OFF

GND (off)

PWM

pulse

output

T

Step-down

or inverting

output

(HA16116-

Ch 1, Ch 2/

HA16121-Ch 1)

This pulse

is for

P-channel

power MOS

FET gate

driving.

V_IN(off)

GND (on)

Note: On duty = t_ON/T, where T = 1/f _OSC

.

6

HA16116FP/FPJ, HA16121FP/FPJ

Determining External Component Constants (pin usage)

Constant settings are explained for the following items.

S.GND

CT

1

2

3

4

5

6

7

8

9

20 S.V_IN

19 Vref

Vref UVL and

OVP

5.

6.

Oscillator

frequency

(f_OSC) setting

1.

Setting of inter-

mittent operation

timing when

overcurrent is

detected

RT

18 TIM

IN(+)1

IN(−)1

E/O1

DB1

17 ON/OFF

16 IN(−)2

15 E/O2

14 DB2

DC/DC converter

output voltage

setting and

2.

3.

4.

error amp usage

ON/OFF pin

usage

7.

8.

Channel 1

Channel 2

Dead band duty

and soft start

setting

Overcurrent

detection value

setting

CL1

13 CL2

Output stage

circuit and

power MOS FET

driving method

OUT1

12 OUT2

11 P.V _IN

P.GND 10

1. Oscillator Frequency (f_OSC) Setting

Figure 1.1 shows an equivalent circuit for the triangle wave oscillator.

V_H

(3.3 V

IC internal circuits)

Vref (2.5 V)

1.6 V typ

V_L

1.0 V typ

C_Tcharging

I_O

R_A

t₁

t₂

Comparator

R_C

I_O

Discharging

R_B

C_T

(external)

C_T

1 : 2

1.1 V

R_T

(external)

Inside the IC

Figure 1.1 Equivalent Circuit for the Triangle Wave Oscillator

7

HA16116FP/FPJ, HA16121FP/FPJ

The triangle wave is a voltage waveform used as a reference in creating a PWM pulse. This block operates

according to the following principles. A constant current I_O, determined by an external timing resistor R_T,

is made to flow continuously to external timing capacitor C_T. When the C_Tpin voltage exceeds the

comparator threshold voltage V_H, the comparator output causes a switch to operate, discharging a current I_O

from C_T. Next, when the C_Tpin voltage drops below threshold voltage V_L, the comparator output again

causes the switch to operate, stopping the I_Odischarge. The triangle wave is generated by this repeated

operation.

Note that I_O= 1.1 V/R_T. Since the I_Ocurrent mirror circuit has a very limited current producing ability, R_T

should be set to ≥ 5 kΩ (I_O≥ 220 µA).

With this IC series, V_Hand V_Lof the triangle wave are fixed internally at about 1.6 V and 1.0 V by the

internal resistors R_A, R_B, and R_C. The oscillator frequency can be calculated as follows.

1

f_OSC

Here,

=

t₁+ t₂+ t₃

C_T(V_H− V_L)

C_TR_T(V_H− V_L)

t₁=

=

1.1 V/R_T

1.1 V

C_T(V_H− V_L)

(2 − 1) × 1.1 V/R_T

C_TR_T(V_H− V_L)

t₂=

=

= t₁

1.1 V

V

_H− V_L= 0.6 V

0.6

t₁= t₂=

1.1

C_TR_T

t₃≈ 0.8 µs (comparator delay time in the oscillator)

Accordingly,

1

f_OSC

≈

[Hz]

≈

2t₁+ t₃

1.1 C_TR_T+ 0.8 µs

Note that the value of f_OSCmay differ slightly from the above calculation depending on the amount of delay

in the comparator circuit. Also, at high frequencies this comparator delay can cause triangle wave

overshoot or undershoot, skewing the dead band threshold. Confirm the actual value in implementation

and adjust the constants accordingly.

8

HA16116FP/FPJ, HA16121FP/FPJ

2. DC/DC Converter Output Voltage Setting and Error Amp Usage

2.1 Positive Voltage Booster (V_O> V_IN) or Step-Down (V_IN> V_O> Vref)

R₁+ R₂

Use V_O

=

Vref (V)

R₂

Booster output is possible only at channel 2 of HA16121. For step-down output, both channels of

HA16116 or channel 1 of HA16121 are used.

V_O

Error amp.

R₁

IN(−)1

−

CH1

IN(+)1 +

R₂

V_O

R₁

IN(−)2

−

CH2

R₂

+

Vref

2.5 V

Vref pin

(internal connection)

Figure 2.1

2.2 Negative Voltage (V_O< Vref) for Inverting Output

R₁

R₁+ R₂

R₃+ R₄

R₃

Use V_O= −Vref

− 1 (V)

Channel 1 is used for inverting output on both ICs.

Vref pin

Vref 2.5 V

R₁

IN(−)1

−

CH1

R

R₂

3

+

IN(+)2

R₄

Error amp

V_O

Figure 2.1 Inverting Output

9

HA16116FP/FPJ, HA16121FP/FPJ

2.3 Error Amplifier

Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier on these ICs is configured

of a simple NPN transistor differential input amplifier and the output circuit of a constant-current driver.

This amplifier features wide bandwidth (f_T= 4 MHz) with open loop gain kept to 50 dB, allowing stable

feedback to be applied when the power supply is designed. Phase compensation is also easy.

Both HA16116 and HA16121 have a noninverting input (IN(+)) pin, in order to allow use of the channel 1

error amplifier for inverting control. The channel 2 error amplifier, on the other hand, is used for step-

down control in HA16116 and booster control in HA16121; so the channel 2 noninverting input is

connected internally to Vref.

IC internal V_IN

IN(−)

E/O

IN(+)

To internal PWM

comparator

80 µA

40 µA

Figure 2.3 Error Amplifier Equivalent Circuit

3. Dead Band (DB) Duty and Soft Start Setting (common to both channels)

3.1 Dead Band Duty Setting

Dead band duty is set by adjusting the DB pin input voltage (V_DB). A convenient means of doing this is to

connect two external resistors to the Vref of this IC so as to divide V_DB(see figure 3.1).

R₂

R₁+ R₂

V_DB= Vref

Duty (DB) =

Here, T =

×

(V)

V

_TH− V_DB

_TH− V_TL

× 100 (%)

This applies when V_DB> V_TL

.

If V_DB< V_TL, there is no PWM output.

1

f_OSC

Note: V_TH: 1.6 V (Typ)

V_TL: 1.0 V (Typ)

Vref is typically 2.5 V. Select R₁and R₂so that 1.0 V ≤ V_DB≤ 1.6 V.

10

HA16116FP/FPJ, HA16121FP/FPJ

V_TH

V_E/O

V_DB

1.6 V typ

To Vref

R₁

PWM

C_T

V_TL

1.0 V typ

V_IN

comparator

−

+

E/O

On

t_ON

V_DB

Booster

channel

t_OFF

DB

Off

5k

GND

V_IN

PWM

pulse

output

From UVL

C_ST

0.8V

R₂

Step-down/

inverting

channel

On

GND

T

Figure 3.1 Dead Band Duty Setting

3.2 Soft Start (SST) Setting (each channel)

When the power is turned on, the soft start function gradually raises V_DB(refer to section 3.1), and the

PWM output pulse width gradually widens. This function is realized by adding a capacitor C_STto the DB

pin. The function is realized as follows.

In the figure 3.2, the DB pin is clamped internally at approximately 0.8 V, which is 0.2 V lower than the

triangle wave V_TL= 1.0 V typ.

t_A: Standby time until PWM pulse starts widening.

t_B: Time during which SST is in effect.

During soft start, the DB pin voltage in the figure below is as expressed in the following equation.

−t − t_0.8

V_SST= V_DB

Here,

t_0.8= −T ln

t_SST= t_A+ t_B

T

1 − e

,

0.8

T = C_ST(R₁// R₂)

1 −

,

V_DB

How to select values: If the soft start time t_SSTis too short, the DC/DC converter output voltage will tend to

overshoot. To prevent this, set t_SSTto a few tens of ms or above.

11

HA16116FP/FPJ, HA16121FP/FPJ

V

(voltage)

V_SST

Triangle wave

V_TH

1.6 V

1.0 V

V_TL

Starts from clamp

voltage of 0.8 V

PWM output

pulse starts to

widen

Steady-state

operation

0 V

V_IN

t_0.8

t_A

t_B

Booster

channel

0 V

V_IN

PWM pulse

output

Step-down/

inverting

channel

0 V

V_O

DC/DC converter output

(positive in this example)

0 V

t = 0 (here IC is on)

t = t_SST

Figure 3.2 Soft Start (SST) Setting

12

HA16116FP/FPJ, HA16121FP/FPJ

4. Totem Pole Output Stage Circuit and Power MOS FET Driving Method

The output stage of this IC series is configured of totem pole circuits, allowing direct connection to a power

MOS FET as an external switching device, so long as V_INis below the gate breakdown voltage.

If there is a possibility that V_INwill exceed the gate breakdown voltage of the power MOS FET, a Zener

diode circuit like that shown figure 4.1 or other protective measures should be used. The figure 4.1 shows

an example using a P-channel power MOS FET.

P.V _IN

E.g.: V_IN= 18 V

Zener diode for

gate protection

Bias

circuit

OUT

Gate

protection

resistor

V_O

+

−

Drive circuit

Schottky

barrier diode

Figure 4.1 P-channel Power MOS FET (example)

5. Vref Undervoltage Error Prevention (UVL) and Overvoltage Protection (OVP) Functions

5.1 Operation Principles

The reference voltage circuit is equipped with UVL and OVP functions.

•

UVL

In normal operation the Vref output voltage is fixed at 2.5 V. If V_INis lower than normal, the UVL

circuit detects the Vref output voltage with a hysteresis of 1.7 V and 2.0 V, and shuts off the PWM

output if Vref falls below this level, in order to prevent malfunction.

•

OVP

The OVP circuit protects the IC from inadvertent application of a high voltage from outside, such as if

V_INis shorted. A Zener diode (5.6 V) and resistor are used between Vref and GND for overvoltage

detection. PWM output is shut off if Vref exceeds approximately 7.0 V.

Note that the PWM output pulse logic and the precision of the switching regulator output voltage are not

guaranteed at an applied voltage of 2.5 V to 7 V.

13

HA16116FP/FPJ, HA16121FP/FPJ

5.2 Quick Shutoff

When the UVL circuit goes into operation, a sink transistor is switched on as in the figure below, drawing

off the excess current. This transistor also functions when the IC is turned off, drawing off current from the

C_T, E/O, and DB pins and enabling quick shutoff.

PWM

output

PWM

output

off

PWM output on

PWM

output off

On

Off

Vref (V)

1.7 2.0 2.5

5.0

7.0

When V_INis

low

Abnormal voltage

applied to Vref

Relation of Vref to UVL and OVP

Vref

V_IN

Vref

2.0 V and

1.7 V

detection

Vref

generation

circuit

Internal

pulse

signal

line

ZD

5.6 V

UVL

OUT

R

Sink

transistor

10 kΩ

OVP

To other circuitry

Figure 5.1 Quick Shutoff

14

HA16116FP/FPJ, HA16121FP/FPJ

6. Setting of Intermittent Operation Timing when Overcurrent is Detected

6.1 Operation Principles

The current limiter on this IC detects overcurrent in each output pulse, providing pulse-by-pulse

overcurrent protection by limiting pulse output whenever an overcurrent is detected. If the overcurrent

state continues, the TIM pin and ON/OFF pin can be used to operate the IC intermittently. As a result, a

power supply with sharp vertical characteristics can be configured.

The ON/OFF timing for intermittent operation makes use of the hysteresis in the ON/OFF pin threshold

voltage V_ONand V_OFF, such that V_ON– V_OFF= V_BE. Setting method is performed as described on the

following pages. V_BEis based-emitter voltage of internal transistor.

Note: When an overcurrent is detected in one channel of this IC but not the other, the pulse-by-pulse

current limiter still goes into operation on both channels. Also, when the intermittent operation

feature is not used, the TIM pin should be set to open state and the ON/OFF pin pulled up to high

level (above V_ON).

V_IN

R_A

Current

Latch limiter

390 kΩ

CL

S

R

TM

Q

4.7 kΩ

2.2 µF

R_B

Vref

generation

circuit

ON/OFF

+

C_ON/OFF

−

Figure 6.1 Connection Diagram (example)

6.2 Intermittent Operation Timing Chart (V_ON/OFFonly)

*1

4V_BE

c

3V_BE

2V_BE

V_BE

V_ON/OFF

On

Off

IC is on

IC is off

a

b

0 V

t

T_ON

2T_ON

a. Continuous overcurrent detected

T_OFF

b. Intermittent operation starts (IC is off)

c. Overcurrent cleared (dotted line)

1.V_BEis the base-emitter voltage in transistors on the IC, and is approximately 0.7 V

(see the figure 7.1).

Note:

For details, see the overall waveform timing diagram.

Figure 6.2 Intermittent Operation Timing Chart

15

HA16116FP/FPJ, HA16121FP/FPJ

6.3 Calculating Intermittent Operation Timing

Intermittent operation timing is calculated as follows.

(1) T_ONtime (the time until the IC is shut off when continuous overcurrent occurs)

3V_BE

2V_BE

1

T_ON= C_ON/OFF× R_B× ln

×

1 − On duty*

1

= C_ON/OFF× R_B× ln1.5 ×

0.4

C

R

× ×

B

≈

×

ON/OFF

1 − On duty*

(2) T_OFFtime (when the IC is off, the time until it next goes on)

V

_IN− 2V_BE

_IN− 3V_BE

T_OFF= C_ON/OFF(R + R )

×

× ln

A

B

Where, V_BE≈ 0.7 V

Note: 1. On duty is the percent of time the IC is on during one PWM cycle when the pulse-by-pulse

current limiter is operating.

From the first equation (1) above, it is seen that the shorter the time T_ONwhen the pulse-by-pulse current

limiter goes into effect (resulting in a larger overload), the smaller the value T_ONbecomes.

As seen in the second equation (2), T_OFFis a function of V_IN. Further, according to this setting, when V is

IN

switched on, the IC goes on only after T_OFFhas elapsed.

Dead band voltage

Triangle wave

Point at which current

limiter operate

PWM output

(step-down channel)

t_ON

On duty =

T

Where T = 1/f_OSC

T

On duty is the percent of time the IC is on during one PWM cycle when

the pulse-by-pulse current limiter is operating.

Note:

Figure 6.3

16

HA16116FP/FPJ, HA16121FP/FPJ

6.4 Examples of Intermittent Operation Timing (calculated values)

4

3

2

1

0

(1) T_ON

T_ON= T₁× C_ON/OFF× R_B

Here, coefficient

1

T₁= 0.4 ×

1 − On duty

from section 6.3 (1) previously.

T₁

Example: If C_ON/OFF= 2.2 µF,

R = 4.7 k , and the on duty

Ω

B

of the current limiter is 75%,

then T_ON= 16 ms.

0

20

40

60

80

100

(PWM) ON Duty (%)

Figure 6.4 Examples of Intermittent Operation Timing (1)

(2) T_OFF

T_OFF= T₂× C_ON/OFF× (R_A+ R_B)

0.1

Here, coefficient

V

_IN− 2V_BE

_IN− 3V_BE

T₂= ln

T₂

0.05

from section 6.3 (2) previously.

Example: If C_ON/OFF= 2.2 µF, R_B= 4.7 kΩ,

R_A= 390 kΩ, V = 12 V,

IN

0

then T_OFF= 60 ms.

0

10

20

V_IN(V)

30

40

Figure 6.5 Examples of Intermittent Operation Timing (2)

17

HA16116FP/FPJ, HA16121FP/FPJ

Triangle wave V_CT

Dead band V_DB

Example of step-up circuit

V_IN

C_F

R_F

R_CS

Error output V_E/O

PWM pulse output

(In case of HA16120)

C_L

Inductor

L

IC

OUT

V_OUT

Power MOS FET

drain current (I_D)

(dotted line shows

inductor current)

I_D

F.B.

V_IN

Determined by L and V_IN

Determined by R_CSand R_F

Current limiter

pin (CL)

V

_TH(CL)

V

_IN− 0.2 V

Figure 6.6

7. ON/OFF Pin Usage

7.1 IC Shutoff by the ON/OFF Pin

As shown in the figure 7.1, these ICs can be turned off safely by lowering the voltage at the ON/OFF pin to

below 2V_BE. This feature is used to conserve the power in the power supply system. In off state the IC

current consumption (I_OFF) is 10 µA (Max) for HA16116 and 150 µA (Max) for HA16121.

The ON/OFF pin can also be used to drive logic ICs such as TTL or CMOS with a sink current of 50 µA

(Typ) at an applied voltage of 5 V. When it is desired to employ this feature along with intermittent

operation, an open collector or open drain logic IC should be used.

V_IN

I_IN

R_A

S.V_IN

P.V _IN

TIM

External logic IC

To output

stage

To latch

To other circuitry

Vref

Off On

Switch

R_B

Q₁

Vref

generation

circuit

50 kΩ

output

ON/OFF

Q₂

Q₃

+

4 V_BE

−

C_ON/OFF

Q₄

GND

HA16116,

HA16121

On/off hysteresis circuit

Figure 7.1 IC Shutoff by the ON/OFF Pin

18

HA16116FP/FPJ, HA16121FP/FPJ

7.2 Adjusting UVL Voltage (when intermittent operation is not used)

The UVL voltage setting in this IC series can be adjusted externally as shown below.

Using the relationships shown in the figure, the UVL voltage in relation to V_INcan be adjusted by changing

the relative values of V_THand V_TL.

When the IC is operating, transistor Q₄is off, so V_ON= 3V_BE≈ 2.1 V. Accordingly, by connecting resistors

R_Cand R_D, the voltage at which UVL is cancelled is as follows.

R_C+ R_D

V_IN= 2.1 V ×

R_D

This V_INis simply the supply voltage at which the UVL stops functioning, so in this state Vref is still below

2.5 V. In order to restore Vref to 2.5 V, a V_INof approximately 4.3 V should be applied.

With this IC series, V_ON/OFFmakes use of the V_BEof internal transistors, so when designing a power supply

system it should be noted that V_ONhas a temperature dependency of around –6 mV/°C.

V_IN

P.V_IN

S.V_IN

To output

stage

To other circuitry

Vref output

TIM

(open)

R_C

To latch

ON/OFF

Q₁

Vref

generation

circuit

50 kΩ

R_D

Q₂

Q₃

Q₄

On/off hysteresis circuit

GND

2.5 V

3

V_IN≥ 4.5 V

2

1

0

Vref

V_OFF

1.4 V

V_ON

2.1 V

0

1

2

3

4

5

V_ON/OFF

Figure 7.2 Adjusting UVL Voltage

19

HA16116FP/FPJ, HA16121FP/FPJ

Overcurrent Detection Value Setting

The overcurrent detection value V_THfor this IC series is 0.2 V (Typ) and the bias current is 200 µA (Typ)

The power MOS FET peak current value before the current limiter goes into operation is derived from the

following equation.

V

_TCL− (R_F+ R_CS) I_BCL

I_D=

R_CS

Here V_TH= V_IN– V_CL= 0.2 V, V_CLis a voltage referd on GND.

Note that C_Fand R_CSform a low-pass filter, determined by their time constants, that prevents malfunctions

from current spikes when the power MOS FET is turned on or off.

C_F1800 PF

I_BCL

S.V_IN

R_CS

0.05 Ω

V_IN

V_CL

To other

circuitry

CL

R_F

240 Ω

This circuit is an example

for step-down output use.

1 k

G

OUT

S

D

200 A

V_O

Detection

output

(internal)

+

− +

−

IN(—)

Figure 8.1 Example for Step-Down Use

The sample values given in this figure are calculated from the following equation.

0.2 V − (240 Ω + 0.05 Ω) × 200 µA

I_D=

0.05 Ω

= 3.04 [A]

The filter cutoff frequency is calculated as follows.

1

f_C=

=

= 370 [kHz]

2π C_FR_F

6.28 × 1800 pF × 240 Ω

20

HA16116FP/FPJ, HA16121FP/FPJ

Absolute Maximum Ratings (Ta = 25°C)

Rating

HA16116FP,

HA16116FPJ,

HA16121FPJ

Item

Symbol

V_IN

HA16121FP

Unit

V

Supply voltage

40

Output current (DC)

Output current (peak)

Current limiter pin voltage

Error amp input voltage

E/O input voltage

I_O

±0.1

A

I_Opeak

V_CL

±1.0

A

V_IN

V

V_IEA

V_IN

V

V_IE/O

I_RT

Vref

V

RT pin source current

TIM pin sink current

Power dissipation*¹

Operation temperature range

Junction temperature

Storage temperature range

500

µA

mA

mW

°C

I_TM

20

P_T

680*^1,*²

–20 to +85

125

680*^1,*²

–40 to +85

125

Topr

TjMax

Tstg

–55 to +125

Note: 1. This value is based on actual measurements on a 40 × 40 × 1.6 mm glass epoxy circuit board.

At a wiring density of 10%, it is the permissible value up to Ta = 45°C, but at higher temperatures

this value should be derated by 8.3 mW/°C. At a wiring density of 30% it is the permissible value

up to Ta = 64°C, but at higher temperatures it should be derated by 11.1 mW/°C.

2. For the DILP package.

This value applies up to Ta = 45°C; at temperatures above this, 8.3 mW/°C derating should be

applied.

800

10% wiring density

680 mW

30% wiring density

600

447 mW

400

348 mW

200

45°C

64°C

85°C

125°C

0

−20

0

20

40

60

80

100

120

140

Operating ambient temperature Ta (°C)

21

HA16116FP/FPJ, HA16121FP/FPJ

Electrical Characteristics (Ta = 25°C, V_IN= 12 V, f_OSC= 300 kHz)

Item

Symbol

Vref

Min

Typ Max Unit

Test Conditions

I_O= 1 mA

Reference

voltage

block

Output voltage

Line regulation

Load regulation

2.45 2.50 2.55

V

Line

—

10

30

25

60

—

mV

mA

4.5 V ≤ V_IN≤ 40 V

0 ≤ I_O≤ 10 mA

Vref = 0 V

Load

I_OS

Output shorting

current

Vref OVP voltage

Vrovp

6.2

6.8

7.0

—

V

Output voltage

temperature

dependence

∆Vref/∆Ta —

100

ppm/°C

Triangle

wave

Maximum oscillator

frequency

f_OSCmax

600

—

±1

±5

—

1

kHz

Hz

%

oscillator

block

Minimum oscillator

frequency

f_OSCmin

—

Oscillator frequency

input voltage stability

∆f_OSC/∆V_IN

∆f_OSC/∆Ta

—

±3

—

4.5 V ≤ V_IN≤ 40 V

–20°C ≤ Ta ≤ 85°C

Oscillator frequency

temperature stability

—

%

Oscillator frequency

f_OSC

270

300 330 kHz

C_T= 220 pF, R_T= 10 kΩ)

Dead band Low-level threshold

adjust block voltage

V_TLDB

0.87 0.97 1.07

1.48 1.65 1.82

0.55 0.65 0.75

V

Output on duty 0%

High-level threshold

voltage

V_THDB

Output on duty 100%

Threshold differential ∆V_TDB

voltage

∆V_TH= V_TH– V_TL

Output source current I_{Osource (DB)}

Low-level threshold V_TLCMP

comparator voltage

block High-level threshold

oltage

100

150 200 µA

DB pin = 0 V

PWM

0.87 0.97 1.07

1.48 1.65 1.82

0.55 0.65 0.75

V

%

Output on duty = 0%

V_THCMP

Output on duty = 100%

∆V_TH= V_TH– V_TL

Threshold differential ∆V_TCMP

voltage

Dead band precision DBdev

–5

0

+5

Deviation when

V

_EO= (V_TL+ V_TH)/2,

duty = 50 %

22

HA16116FP/FPJ, HA16121FP/FPJ

Electrical Characteristics (Ta = 25°C, V_IN= 12 V, f_OSC= 300 kHz) (cont)

Item

Error amp Input offset voltage V_IOEA

block Input bias current I_BEA

Symbol Min

Typ

2

Max

10

2

Unit Test Conditions

—

mV

0.8

40

µA

Output sink current I_{Osink (EA)}28

52

µA

In open loop,

V_I= 3 V, V_O= 2 V

Output source

current

I_{Osource (EA)}28

40

52

µA

In open loop,

V_I= 2 V, V_O= 1 V

Voltage gain

A_V

40

3

50

4

—

dB

f = 10 kHz

Unity gain band-

width

BW

MHz

High-level output V_OHEA

voltage

2.2

—

3.0

0.2

—

V

I_O= 10 µA

Low-level output

voltage

V_OLEA

0.5

Overcurrent Threshold voltage V_TCL

V_IN–0.22 V_IN–0.2 V_IN–0.18

V

detection

block

CL bias current

Operating time

I_BCL

150

—

200

500

250

300

600

µA

ns

C_L= V_IN

t_OFFCL

C_L= V_IN–0.3 V

—

Applies only to ch 2

of HA16121

Output

stage

Output low voltage V_OL1

—

0.7

1.6

1.0

1.6

2.2

1.9

1.3

1.9

V

I_Osink= 10 mA

Applies only to HA16116

I_Osink= 10 mA

Applies only to HA16121

I_Osink= 0 mA

Applies only to HA16121

Off state low

voltage

V_OL2

I_Osink= 1 mA

ON/OFF pin = 0 V

Applies only to ch 2

of HA16121

—

1.0

1.3

V

I_Osink= 0 mA

ON/OFF = 0 V

Applies only to ch 2

of HA16121

Output high

voltage

V_OH1

V_IN–1.9 V_IN–1.6 —

V_IN–1.3 V_IN–1.0 —

V_IN–1.9 V_IN–1.6 —

V

I_Osource= 10 mA

I_Osource= 0 A

Off state high

voltage

V_OH2

I_Osource= 1 mA

ON/OFF pin = 0 V

V_IN–1.3 V_IN–1.0 —

V

I_Osource= 0 A

ON/OFF pin = 0 V

23

HA16116FP/FPJ, HA16121FP/FPJ

Electrical Characteristics (Ta = 25°C, V_IN= 12 V, f_OSC= 300 kHz) (cont)

Item

Symbol

Min Typ Max Unit Test Conditions

Output

stage

Rise time

Fall time

t_r

—

70

3.6

130 ns

C_L= 1000 pF (to V_IN) *^1,*²

t_f

—

UVL

block

V_INhigh-level threshold

voltage

V_TUH1

3.3

3.9

3.6

0.5

2.3

2.0

0.5

V

V_INlow-level threshold

voltage

V_TUL1

∆V_TU1

V_TUH2

V_TUL2

∆V_TU2

3.0

0.1

1.7

1.4

0.1

3.3

0.3

2.0

1.7

0.3

V_INthreshold differential

voltage

∆V_TU1= V_TUH1– V_TUL1

Vref high-level threshold

voltage

Vref low-level threshold

voltage

Vref threshold differential

voltage

∆V_TU2= V_TUH2– V_TUL2

ON/OFF pin = 5 V

ON/OFF

block

ON/OFF pin sink current

IC on-state voltage

IC off-state voltage

I_ON/OFF

V_ON

—

35

50

µA

V

1.8

1.1

0.5

2.1

1.4

0.7

2.4

1.7

0.9

V_OFF

V

ON/OFF threshold

differential voltage

∆V_ON/OFF

V

TIM

block

TIM pin sink current in

steady state

I_TIM1

I_TIM2

I_IN

0

—

10

20

µA

CL pin = V_IN

V_TIM= 0.3 V

TIM pin sink current at

overcurrent detection

10

15

8.5

mA

CL pin = V_IN– 0.3 V

V_TIM= 0.3 V

Common Operating current

block

6.0

8.5

11.1 mA

C_L= 0 pF (to V_IN) *^1,*²

C_L= 500 pF (to V_IN) *^1,*²

C_L= 1000 pF (to V_IN) *^1,*²

HA16116FP ON/OFF

HA16121FP pin = 0 V

12.1 15.7 mA

11.0 15.7 20.5 mA

Off current

I_OFF

0

—

10

µA

120

150 µA

Notes: 1. C_Lis load capacitor for Power MOS FET’s gate, and C_L= 1000 pF to GND in the case of

HA16121 – ch 2.

2. C_Lin channel 2 of HA16121 is connected to GND.

24

HA16116FP/FPJ, HA16121FP/FPJ

Characteristic Curves

•

Reference Voltage Block (Vref)

Reference Voltage vs. Power Supply Input Voltage

Vref Temperature Characteristics

2.54

3

Ta = 25°C

V_IN= 12 V

R

_A= 390 kΩ

2.5 V

I

_O(Vref) = 1 mA

(Between the V_IN

and ON/OFF pins)

2.52

2.50

2.48

2.46

2

1

UVL release: 3.6 V

UVL operate: 3.3 V

3.3 3.6 4.3

85

−20

0

20

40

60

80

100

0

1

2

3

4

5

40

Ambient temperature Ta (°C)

Power supply input voltage V_IN(V)

Vref Load Regulation

3.0

2.5

2.0

1.50

0

Short

circuit

current

10

20

30

Output current I_{O sink}(mA)

•

UVL (Low Input Voltage Malfunction Prevention) Block

Hysteresis Voltage Temperature Characteristics

4.5

High threshold voltage

Hysteresis

4.0

3.5

3.0

2.5

Low threshold voltage

−20

0

20

40

60

80

100

Ambient temperature Ta (°C)

25

HA16116FP/FPJ, HA16121FP/FPJ

•

Triangle Wave Oscillator Block

R_Tpin Output Current Characteristics

1.1

Sawtooth Wave Amplitude vs. Oscillator Frequency

2.0

V_TH

1.5

1.0

0.9

Sawtooth wave

amplitude

V_TL

1.0

Note: Due to these characteristics, the dead

band and PWM comparator threshold

voltages change at high frequencies.

Reccomended

usage range

0.5

10 (R_T≈ 100 kΩ)

330 (R_T≈ 3 kΩ)

300 400 500

0.8

0

100

200

I_RT(µA)

0

100

200

300

400

500

600

(DC)

f_OSC(kHz) (linear scale)

C_T, R_TValues (V_IN= 12V) vs. Oscillator Frequency

100

70

50

30

20

600 kHz

10

7

5

3

10

20

30

50

70 100

200 300

500 700 1 M

Oscillator frequency f_OSC(kHz)

Oscillator Frequency Temperature Stability

+10

+5

0

V_IN= 12 V

A: f_OSC= 300 kHz

B: f_OSC= 600 kHz

B

A

B

−5

85

−10

−20

0

20

40

60

80

100

Ambient temperature Ta (°C)

26

HA16116FP/FPJ, HA16121FP/FPJ

•

Error Amplifier Block

Open Loop Gain Characteristics

60

A_VO

40

20

0

φ

45

90

135

180

BW

3 M

0

1 k

3 k

10 k

30 k

100 k

300 k

1 M

10 M

Error amplifier input frequency f_IN(Hz)

Common Mode Input Characteristics

+100

0

⁻₊EA

V

−

O

−100

−200

−300

+

V_I

Vref

0

1

2

3

4

Input voltage V_I(V)

•

On Duty Characteristics

100

80

60

40

20

0

100

80

60

40

20

0

Boost PWM output

(HA16121-2 ch)

Step-down

PWM output

(HA16116-1, 2ch

HA16121-1ch)

0.8

1.0

1.2

1.4

1.6

1.8

0.8

1.0

1.2

1.4

1.6

1.8

V_DBor V_E/O(V)

Notes: 1. The percentage of a single timing cycle

during which the output is low.

2. The percentage of a single timing cycle

during which the output is high.

27

HA16116FP/FPJ, HA16121FP/FPJ

•

Other Characteristics

Current Limiter Level Temperature Characteristics IC On Voltage and Off Voltage Temperature Characteristics

4

3

2

1

0

220

210

200

190

180

V_ONon voltage (about −6mV/°C)

85°C

V_OFFoff voltage

(about −4mV/°C)

−20

0

20

40

60

80

100

−20

0

20

40

60

80

100

Ambient temperature Ta (°C)

I_INvs. V_INCharacteristics

Output pin (Output Resistor) Characteristics

12

40

30

20

10

V_GS

(P-channel

Power

f_OSC= 300 kHz

On duty: 50%

Ta = 25°C

Output high voltage when on

11

10

9

MOS FET)

Maximum

rating at

Output high voltage

when off (channels 1

and 2 in the HA16116

and channel 1 in the

HA16121)

Ta = 25°C:

680 mW

Load capacitance:

1000 pF/ch

500 pF/ch

3

2

1

No load

Output low voltage when on

Output low voltage

when off (channels 1

and 2 in the HA16121)

V_GS

(N-channel

Power

MOS FET)

10

20

30

40

2

4

6

8

10

0

Power supply voltage V_IN(V)

I_{O sink}or I_{O source}(mA)

Output Drive Circuit Power MOS FET

Direct Drive ability Data

Gate Drive Waveforms for the 2SJ214

800

600

400

200

0

V_IN= 12 V

f_OSC= 130 kHz

2SJ216

2SJ176

2SJ214

Drive voltage:

5 V/div

*

Drive current:

200 mA/div

1000

2000

3000

4000

Ciss (pF)

650 nsec/div

Note: The solid line is data measured with discrete

capacitances (for each channel of HA16116).

Note: * Measured using a current probe.

(The boost channel (channel 2 in the HA16121)

load is with respect to ground, and has

almost identical characteristics.)

28

HA16116FP/FPJ, HA16121FP/FPJ

Application Examples (1)

29

HA16116FP/FPJ, HA16121FP/FPJ

Overall Waveform Timing Diagram (for Application Examples (1))

12 V

V

IN

0 V

V_TIM

,

2.8 V

2.1 V

V_ON/OFF

V_TIM

V_ON/OFF

,

2.1 V

1.4 V

0 V

On

(V)

3.0

On

V_E/O

Off Off Off Off

Off

V_CT

triangle wave

2.0

1.0

0.0

V_E/O

V_CT

V_DB

,

V_DB

12 V

V_CL

11.8 V

0 V

Pulse-by-pulse

current limiter

operates

12 V

0 V

V_OUT*1

PWM

pulse

DC/DC output

(example for

positive

voltage)

Soft start

Steady-state

operation

Overcurrent

detected;

Overcurrent Quick

cleared;

shut-off

IC operation

states

intermittent

operation

steady-state

operation

Power

supply on

IC on

Power supply off,

IC off

Note: 1.This PWM pulse is on the step-down/inverting control channel.

The booster control channel output consists of alternating L and H of the IC on cycle.

30

HA16116FP/FPJ, HA16121FP/FPJ

Application Examples (2) (Some Pointers on Use)

1. Inductor, Power MOS FET, and Diode Connections

1. Booster specification

V_IN

2. Step-down specification

V_IN

C_F

R_CSApplicable to

HA16116FP and

to channel 1

R_CSApplicable only

R_F

V_IN

R_F

V_IN

to channel 2

of HA16121FP

C_L

of HA16121FP

OUT

V_O

OUT

GND

FB

3. Inverting specification

C_F

4. Negative booster specification (Flyback transformer)

C_F

R_CS

Applicable only

to channel 1

Applicable only

to channel 1

R_F

V_IN

C_L

OUT

V_O

GND

FB

Vref

2. Turning Output On and Off while the IC is On

1. To turn only one channel off, ground the DB pin

or the E/O pin. In the case of E/O, however,

there will be no soft start when the output is

turned back on.

2. When only one channel is to be used,

the channel not used should be connected

as follows.

V_IN

DB

C_L

Connect C_Lto V_IN.

+

Ground IN(+) and IN(−).

Leave other pins open.

IN

E/O

−

IN

GND

OFF

31

HA16116FP/FPJ, HA16121FP/FPJ

Application Examples (3)

32

HA16116FP/FPJ, HA16121FP/FPJ

Package Dimensions

Unit: mm

12.6

13 Max

11

10

20

1

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0° – 8°

1.27

0.70 ± 0.20

*0.42 ± 0.08

0.40 ± 0.06

0.15

0.12 M

Hitachi Code

JEDEC

FP-20DA

—

EIAJ

Conforms

0.31 g

*Dimension including the plating thickness

Base material dimension

Mass (reference value)

33

HA16116FP/FPJ, HA16121FP/FPJ

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower, World Finance Centre,

Harbour City, Canton Road, Tsim Sha Tsui,

Kowloon, Hong Kong

Tel: <852> (2) 735 9218

Fax: <852> (2) 730 0281

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Electronic components Group

Dornacher Straβe 3

D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

179 East Tasman Drive,

San Jose,CA 95134

Tel: <1> (408) 433-1990

Fax: <1>(408) 433-0223

Fax: 535-1533

Hitachi Asia Ltd.

Taipei Branch Office

3F, Hung Kuo Building. No.167,

Tun-Hwa North Road, Taipei (105)

Tel: <886> (2) 2718-3666

Fax: <886> (2) 2718-8180

Telex: 40815 HITEC HX

Hitachi Europe Ltd.

Electronic Components Group.

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Fax: <44> (1628) 778322

34


型号：	HA16116
厂家：	HITACHI SEMICONDUCTOR
描述：	Switching Regulator for Chopper Type DC/DC Converter 开关稳压器型DC / DC转换器转换器稳压器开关
文件：	总34页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HA16116 [HITACHI]

相关型号：

HA16116FP

HA16116FP

HA16116FP-EL

HA16116FP-EL

HA16116FP-EL-E

HA16116FP-EL-E

HA16116FP/FPJ/

HA16116FP/FPJ|HA16121FP/FPJ

HA16116FPJ

HA16116FPJ

HA16116FPJ-E

HA16116FPJ-EL