2SK3993-ZK-E2 [RENESAS]
2SK3993-ZK-E2;
| 型号： | 2SK3993-ZK-E2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2SK3993-ZK-E2 |
| 文件： | 总4页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT INFORMATION
MOS FIELD EFFECT TRANSISTOR
2SK3993
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
ORDERING INFORMATION
The 2SK3993 is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for low voltage high current
applications such as DC/DC converter with synchronous
rectifier.
PART NUMBER
2SK3993
PACKAGE
TO-251 (MP-3)
TO-252 (MP-3ZK)
2SK3993-ZK
(TO-251)
FEATURES
• Low on-state resistance
RDS(on)1 = 3.8 mΩ MAX. (VGS = 10 V, ID = 32 A)
• Low Ciss: Ciss = 4520 pF TYP.
• 5 V drive available
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
(TO-252)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
25
±20
V
V
±64
A
±256
40
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation
W
W
°C
°C
A
PT2
1.0
Channel Temperature
Tch
150
−55 to +150
70
Storage Temperature
Tstg
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
EAS
490
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 12.5 V, RG = 25 Ω, VGS = 20 → 0 V
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D17322EJ2V0PM00 (2nd edition)
Date Published November 2004 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
2004
2SK3993
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
TEST CONDITIONS
MIN.
TYP.
2.5
MAX.
UNIT
µA
nA
V
IDSS
VDS = 25 V, VGS = 0 V
10
±100
3.0
IGSS
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 32 A
VGS = 10 V, ID = 32 A
VGS = 5.0 V, ID = 32 A
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
2.0
15
Note
Forward Transfer Admittance
S
Note
mΩ
mΩ
pF
pF
pF
ns
Drain to Source On-state Resistance
3.3
4.7
4520
1080
770
21
3.8
7.8
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
VDS = 10 V
VGS = 0 V
f = 1 MHz
Coss
Crss
td(on)
tr
VDD = 12.5 V, ID = 32 A
VGS = 10 V
23
ns
RG = 10 Ω
Turn-off Delay Time
Fall Time
td(off)
tf
140
50
ns
ns
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
QG
VDD = 20 V
VGS = 10 V
ID = 64 A
100
17
nC
nC
nC
V
QGS
QGD
VF(S-D)
trr
35
Note
Body Diode Forward Voltage
IF = 64 A, VGS = 0 V
IF = 64 A, VGS = 0 V
di/dt = 100 A/µs
0.9
23
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
ns
Qrr
11
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
GS
R
L
RG
= 25 Ω
90%
V
GS
Wave Form
VGS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
V
DD
V
V
DS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
τ = 1 µs
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
PG.
50 Ω
V
DD
2
Preliminary Product Information D17322EJ2V0PM
2SK3993
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (MP-3)
2) TO-252 (MP-3ZK)
6.6 ±0.2
5.3 TYP.
4.3 MIN.
Mold Area
2.3 ±0.1
0.5 ±0.1
2.3±0.1
6.5±0.2
5.1 TYP.
4.3 MIN.
4
0.5±0.1
No Plating
4
1
2
3
No Plating
1
2
3
1.14 MAX.
No Plating
0.75±0.12
1.14 MAX.
0 to 0.25
2.3 2.3
0.5±0.1
0.5 ±0.1
0.76 ±0.1
1.0
2.3 TYP.
2.3 TYP.
1. Gate
2. Drain
3. Source
4. Fin (Drain)
1. Gate
2. Drain
3. Source
4. Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.
3
Preliminary Product Information D17322EJ2V0PM
2SK3993
•
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
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rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
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customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
•
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"Specific":
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(1)
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defined above).
M5 02. 11-1
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