HYS64T32900HU-3.7-A_技术文档

May 2007

HYS64T32x00HU–[3/3S/3.7/5]–A

HYS[64/72]T64x00HU–[3/3S/3.7/5]–A

HYS[64/72]T128x20HU–[3/3S/3.7/5]–A

240-Pin Unbuffered DDR2 SDRAM Modules

DDR2 SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.41

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

HYS64T32x00HU–[3/3S/3.7/5]–A, HYS[64/72]T64x00HU–[3/3S/3.7/5]–A, HYS[64/72]T128x20HU–[3/3S/3.7/5]–A

Revision History: 2007-01, Rev. 1.41

Page

Subjects (major changes since last revision)

All

Adapted internet edition

42, 43

Table 30 Footnote 4 updated.

Previous Revision: 2007-01, Rev. 1.40

All

Added Products HYS64T[32/64/128]9x0HU–[3S/3.7]–A

Previous Revision: 2006-09, Rev. 1.32

All

Qimonda update

Previous Revision: 2006-03, Rev. 1.31

43, 44, 45, 46

29, 34, 37

48

Editorial changes

Updated AC Timing Parameter table DQS DQ skew value is the max. value

Added 50 ohm data

Previous Revision: 2005-08, Rev. 1.3

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-08-07

03292006-EZUJ-JY4S

2

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

1

Overview

This chapter gives an overview of the 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes its main

characteristics.

1.1

Features

•

240-Pin PC2-5300, PC2-4200 and PC2-3200 DDR2

SDRAM memory modules for use as main memory when

installed in systems such as mobile personal computers.

32M × 64, 64M × 64, 64M × 72, 128M × 64, 128M × 72

module organization, and 32M × 16, 64M × 8 chip

organization

256 MByte, 512 MByte and 1 GByte modules built with

512-Mbit DDR2 SDRAMs in P-TFBGA-60 and P-TFBGA-

84 chipsize packages

All Speed grades faster than DDR2-400 comply with

DDR2-400 timing specifications.

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply

•

Programmable CAS Latencies (3, 4 and 5), Burst Length

(8 & 4) and Burst Type

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_1.8 compatible

Off-Chip Driver Impedance Adjustment (OCD) and On-Die

Termination (ODT)

•

Serial Presence Detect with E²PROM

Dimensions (nominal): 30 mm high, 133.35 mm wide

Based on standard reference layouts Raw Card “A”,

“B”“C“,”D”,”E”,”F” and “G“

•

RoHS compliant products¹⁾

TABLE 1

Performance table for –3(S)

Product Type Speed Code

Speed Grade

–3

–3S

Unit

PC2–5300 4–4–4

PC2–5300 5–5–5

—

Max. Clock Frequency

@CL5 f_CK5333

@CL4 f_CK4333

333

266

200

15

MHz

ns

@CL3 f_CK3200

t_RCD12

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

t_RP12

15

ns

t_RAS45

45

ns

t_RC57

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.41, 2007-05

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03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 2

Performance table for –3.7

Product Type Speed Code

–3.7

Unit

Speed Grade

PC2–4200 4–4–4

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

266

200

15

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

45

ns

60

ns

TABLE 3

Performance table for –5

Product Type Speed Code

–5

Unit

Speed Grade

PC2-3200 3–3–3

—

max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

200

15

MHz

ns

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

15

ns

t_RAS

t_RC

40

ns

55

ns

Rev. 1.41, 2007-05

4

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

1.2

Description

The Qimonda HYS[64/72]T[32/64/128]0x0HU–[3/…/5]–A

module family are unbuffered DIMM modules “UDIMMs” with

30,0 mm height based on DDR2 technology. DIMMs are

available as non-ECC modules in 32M × 64 (256MB),

64M × 64 (512MB), 128M × 64 (1GB) and as ECC modules in

64M × 72 (512MB), 128M × 72 (1GB) organization and

density, intended for mounting into 240-pin connector

sockets.

The memory array is designed with 512-Mbit Double-Data-

Rate-Two (DDR2) Synchronous DRAMs. Decoupling

capacitors are mounted on the PCB board. The DIMMs

feature serial presence detect based on a serial E²PROM

device using the 2-pin I²C protocol. The first 128 bytes are

programmed with configuration data and are write protected;

the second 128 bytes are available to the customer.

TABLE 4

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

PC2-5300

HYS64T32000HU–3–A

HYS64T64000HU–3–A

HYS72T64000HU–3–A

HYS64T128020HU–3–A

HYS72T128020HU–3–A

HYS64T32000HU–3S–A

HYS64T32900HU–3S–A

HYS64T64000HU–3S–A

HYS64T64900HU–3S–A

HYS72T64000HU–3S–A

HYS64T128020HU–3S–A

HYS64T128920HU–3S–A

HYS72T128020HU–3S–A

PC2-4200

256MB 1R×16 PC2–5300U–444–12–C1

512MB 1R×8 PC2–5300U–444–12–D0

512MB 1R×8 PC2–5300E–444–12–F0

1GB 2R×8 PC2–5300U–444–12–E0

1GB 2R×8 PC2–5300E–444–12–G0

256MB 1R×16 PC2–5300U–555–12–C1

512MB 1R×8 PC2–5300U–555–12–D0

512MB 1R×8 PC2–5300E–555–12–F0

1GB 2R×8 PC2–5300U–555–12–E0

1GB 2R×8 PC2–5300E–555–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

1 Rank, Non-ECC

1 Rank, ECC

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–3.7–A

HYS64T32900HU–3.7–A

HYS64T64000HU–3.7–A

HYS64T64900HU–3.7–A

HYS72T64000HU–3.7–A

HYS64T128020HU–3.7–A

HYS64T128920HU–3.7–A

HYS72T128020HU–3.7–A

PC2-3200

256MB 1R×16 PC2–4200U–444–11–C1

512MB 1R×8 PC2–4200U–444–11–A1

512MB 1R×8 PC2–4200U–444–11–D0

512MB 1R×8 PC2–4200E–444–11–A1

1GB 2R×8 PC2–4200U–444–11–B1

1GB 2R×8 PC2–4200U–444–11–E0

1GB 2R×8 PC2–4200E–444–11–B1

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–5–A

HYS64T64000HU–5–A

HYS72T64000HU–5–A

256MB 1R×16 PC2–3200U–333–11–C1

512MB 1R×8 PC2–3200U–333–11–A1

512MB 1R×8 PC2–3200E–333–11–A1

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

Rev. 1.41, 2007-05

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03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

HYS64T128020HU–5–A

HYS72T128020HU–5–A

1GB 2R×8 PC2–3200U–333–11–B1

1GB 2R×8 PC2–3200E–333–12–B1

2 Ranks, Non-ECC

2 Ranks, ECC

512 Mbit (×8)

1) All product types end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3–A, indicating Rev. “A” dies are

used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–5300U–444–12–C1”, where

4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)

latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and

produced on the Raw Card “C”.

TABLE 5

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of SDRAMs # of row/bank/column

bits

Raw

Card

256 MByte

512 MByte

1 GByte

32M ×64

64M ×64

64M ×72

128M ×64

128M ×72

1

2

Non-ECC

ECC

4

13/2/10

14/2/10

C

8

A,D

A,F

B,E

B,G

9

Non-ECC

ECC

16

18

1 GByte

TABLE 6

Components on Modules

Product Type¹⁾

DRAM Components¹⁾

DRAM Density

DRAM Organisation

Notes²⁾

HYS64T32000HU

HYS64T32900HU

HYS64T64000HU

HYS64T64900HU

HYS72T64000HU

HYS64T128020HU

HYS64T128920HU

HYB18T512160AF

HYB18T512800AF

512 Mbit

32M × 16

64M × 8

HYS72T128020HU

1) Green Product

2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

2

Pin Configurations

This chapter contains information to the pin configuration of the modules as well as the block diagrams to the various module

organization

The pin configuration of the Unbuffered DDR2 SDRAM DIMM

is listed by function in Table 7 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 8

and Table 9 respectively. The pin numbering is depicted in

Figure 1 for non-ECC modules (×64) and Figure 2 for ECC

modules (×72).

TABLE 7

Pin Configuration of UDIMM

Ball No.

Name Pin

Buffer Function

Type Type

Clock Signals

185

137

220

186

138

221

52

CK0

CK1

CK2

CK0

CK1

CK2

CKE0

CKE1

NC

I

SSTL

—

Clock Signals 2:0, Complement Clock Signals 2:0

I

Clock Enable Rank 1:0

171

I

NC

Not Connected

Note: 1 Rank module

Control Signals

193

76

S0#

S1#

NC

I

SSTL

—

Chip Select Rank 1:0

I

NC

Not Connected

Note: 1 Rank module

Row Address Strobe

Column Address Strobe

Write Enable

192

RAS

CAS

WE

I

SSTL

74

73

Address Signals

71

BA0

BA1

BA2

NC

I

SSTL

—

Bank Address Bus 1:0

Bank Address Bus 2

190

54

I

NC

Not Connected

Less than 1Gb DDR2 SDRAMS

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Ball No.

Name Pin

Buffer Function

Type Type

188

183

63

A0

I

SSTL

Address Bus 12:0

A1

A2

182

61

A3

A4

60

A5

180

58

A6

A7

179

177

70

A8

A9

A10

AP

A11

A12

A13

57

176

196

Address Signal 13

Note: 1 Gbit based module and 512M ×4/×8

Not Connected

NC

A14

NC

I

—

Note: Module based on 1 Gbit ×16 Module based on 512 Mbit ×16 or smaller

Address Signal 14

174

SSTL

—

Note: Modules based on 2 Gbit

NC

Not Connected

Note: Modules based on 1 Gbit or smaller

Data Signals

3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

4

9

10

122

123

128

129

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Ball No.

Name Pin

Buffer Function

Type Type

12

DQ8

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

206

89

90

95

96

208

209

214

215

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Ball No.

Name Pin

Buffer Function

Type Type

98

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bit Signals

42

CB0

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

SSTL

—

Check Bit 0

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 1

43

CB1

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 2

48

CB2

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 3

49

CB3

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 4

161

162

CB4

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 5

CB5

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Ball No.

Name Pin

Buffer Function

Type Type

167

CB6

NC

I/O SSTL

Check Bit 6

Note: ECC type module only

Not Connected

NC

—

Note: ECC type module only

Check Bit 7

168

CB7

NC

I/O

NC

SSTL

—

Note: ECC type module only

Not Connected

Note: Non-ECC module

Data Strobe Bus

7

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL

Data Strobe Bus 8:0

16

28

37

84

93

105

114

46

6

Complement Data Strobe Bus 8:0

15

27

36

83

92

104

113

45

Data Mask Signals

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Mask Bus 8:0

134

146

155

202

211

223

232

164

EEPROM

120

SCL

SDA

I

CMOS Serial Bus Clock

119

I/O

OD

Serial Bus Data

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Ball No.

Name Pin

Buffer Function

Type Type

239

SA0

SA1

SA2

I

CMOS Serial Address Select Bus 2:0

240

CMOS

101

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

EEPROM Power Supply

I/O Driver Power Supply

238

V_DDSPDPWR

51,56,62,72,75,,

78,170,175,181,,

191,194

V_DDQ

V_DD

V_SS

PWR

GND

53,59,64,67,69,,

172,178,184,187,

189,197

—

Power Supply

Ground Plane

2,5,8,11,14,17,,

20,23,26,29,32,

35,38,41,44,47,,

50,65,66,79,82,

85,88,91,94,97,,

100,103,106,

109,112,115,118,

121,124,127,,

130,133,136,139,

142,145,148,,

151,154,157,160,

163,166,169,

198,201,204,207,

210,213,216,,

219,222,225,228,

231,234,237

Other Pins

195

77

ODT0

ODT1

I

SSTL

On-Die Termination Control 0

On-Die Termination Control 1

Note: 2 Rank modules

NC

—

Not Connected

Note: 1 Rank modules

18,19,55,68,102,1 NC

26,135,147,

Not connected

Note: Pins not connected on Qimonda UDIMMs

156,165,173,203,

212, 224,233

Rev. 1.41, 2007-05

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 8

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NC

Ground

Not Connected

TABLE 9

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

LV-CMOS

CMOS

OD

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tri-state,

and allows multiple devices to share as a wire-OR.

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 1

Pin Configuration UDIMM ×64 (240 Pin)

62%& ꢆ 0IN ꢀꢀꢁ

$1ꢀ ꢆ 0IN ꢀꢀꢃ

6₃₃ꢆ 0IN ꢀꢀꢂ

$13ꢀ ꢆ 0IN ꢀꢀꢄ

$1ꢇ ꢆ 0IN ꢀꢀꢅ

6₃₃ꢆ 0IN ꢀꢁꢁ

$1ꢅ ꢆ 0IN ꢀꢁꢃ

$13ꢁ ꢆ 0IN ꢀꢁꢂ

6₃₃ꢆ 0IN ꢀꢁꢄ

0IN ꢁꢇꢁ ꢆ 6₃₃

0IN ꢁꢇꢇ ꢆ $1ꢈ

0IN ꢁꢇꢃ ꢆ $1ꢂ

0IN ꢁꢇꢈ ꢆ 6₃₃

6₃₃

ꢆ 0IN ꢀꢀꢇ

ꢆ 0IN ꢀꢀꢈ

$1ꢁ

$13ꢀ ꢆ 0IN ꢀꢀꢉ

0IN ꢁꢇꢂ ꢆ $-ꢀ

0IN ꢁꢇꢉ ꢆ .#

0IN ꢁꢇꢄ ꢆ 6₃₃

6₃₃

ꢆ 0IN ꢀꢀꢊ

ꢆ 0IN ꢀꢁꢀ

ꢆ 0IN ꢀꢁꢇ

ꢆ 0IN ꢀꢁꢈ

0IN ꢁꢇꢊ ꢆ $1ꢉ

0IN ꢁꢇꢅ ꢆ $1ꢄ

0IN ꢁꢃꢀ ꢆ 6₃₃

$1ꢃ

$1ꢊ

6₃₃

0IN ꢁꢃꢁ ꢆ $1ꢁꢇ

0IN ꢁꢃꢇ ꢆ $1ꢁꢃ

0IN ꢁꢃꢃ ꢆ 6₃₃

0IN ꢁꢃꢈ ꢆ $-ꢁ

0IN ꢁꢃꢂ ꢆ .#

$13ꢁ ꢆ 0IN ꢀꢁꢉ

0IN ꢁꢃꢉ ꢆ 6₃₃

0IN ꢁꢃꢄ ꢆ #+ꢁ

0IN ꢁꢃꢊ ꢆ #+ꢁ

0IN ꢁꢃꢅ ꢆ 6₃₃

.#

ꢆ 0IN ꢀꢁꢊ

.#

ꢆ 0IN ꢀꢁꢅ

6₃₃

ꢆ 0IN ꢀꢇꢀ

0IN ꢁꢈꢀ ꢆ $1ꢁꢈ

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-004ꢀꢁꢂꢀ

Rev. 1.41, 2007-05

03292006-EZUJ-JY4S

14

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 2

Pin Configuration UDIMM ×72 (240 Pin)

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3

Electrical Characteristics

This chapter contains the electrical characteristics.

3.1

Absolute Maximum Ratings

Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 10 at any time.

TABLE 10

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Notes

Max.

1)

V_DD

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0

–0.5

–55

+2.3

+100

V

1)2)

1)

V_DDQ

V_DDL

V

V_IN, V_OUT

T_STG

V

1)2)

°C

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 11

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Notes

Min.

Max.

1)2)3)4)

T_OPER

Operating Temperature

0

95

°C

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 95 °C under all other specification parameters.

3) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%

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3.2

DC Operating Conditions

This chapter contains the DC operating conditions tables.

TABLE 12

Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Notes

Max.

Operating temperature (ambient)

DRAM Case Temperature

T_OPR

T_CASE

T_STG

0

+65

+95

+100

+105

90

×C

kPa

%

1)2)3)4)

5)

0

Storage Temperature

– 50

+69

10

Barometric Pressure (operating & storage)

Operating Humidity (relative)

PBar

H_OPR

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported

3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C Case

Temperature before initiating Self-Refresh operation.

5) Up to 3000 m.

TABLE 13

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Notes

Nom.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

1.9

V

1)

2)

V_DDQ

V_REF

V_DDSPD

V_IH(DC)

V_IL(DC)

I_L

1.7

1.8

1.9

V

0.49 x V_DDQ

0.5 x V_DDQ

0.51 x V_DDQ

V

1.7

—

3.6

V

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

– 0.30

– 5

_REF– 0.125

V

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_{REF (DC)}.V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

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3.3

AC Characteristics

This chapter contains the AC operating conditions tables.

3.3.1

Speed Grade Definitions

List of speed grade definition tables.

•

Table 14 “Speed Grade Definition Speed Bins for DDR2–667” on Page 18

Table 15 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 19

Table 16 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 19

TABLE 14

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667C

DDR2–667D

Unit

Notes

QAG Sort Name

CAS-RCD-RP latencies

–3

–3S

4–4–4

5–5–5

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

8

5

8

ns

t_CK

3

8

3.75

3

8

t_CK

3

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

45

57

12

70000

—

45

60

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

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TABLE 15

Speed Grade Definition Speed Bins for DDR2–533C

Speed Grade

DDR2–533C

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3.7

4–4–4

t_CK

Parameter

Symbol

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

t_RAS

t_RC

t_RCD

t_RP

5

8

ns

3.75

45

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

TABLE 16

Speed Grade Definition Speed Bins for DDR2–400B

Speed Grade

DDR2–400B

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–5

3–3–3

t_CK

Parameter

Symbol

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

t_RAS

t_RC

t_RCD

t_RP

5

8

ns

5

8

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

40

55

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

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3.3.2

AC Timing Parameters

List of AC Timing parameters.

•

Table 17 “Timing Parameter by Speed Grade - DDR2–667” on Page 20

Table 18 “Timing Parameter by Speed Grade - DDR2–533” on Page 25

Table 19 “Timing Parameter by Speed Grade - DDR2-400” on Page 28

TABLE 17

Timing Parameter by Speed Grade - DDR2–667

Parameter

Symbol

DDR2–667

Unit

Notes^1)2)3)4)5)6)

7)8)

Min.

Max.

9)

DQ output access time from CK / CK

DQS output access time from CK / CK

Average clock high pulse width

Average clock low pulse width

Average clock period

t_AC

–450

–400

0.48

3000

100

+450

+400

0.52

8000

––

ps

9)

t_DQSCK

t_CH.AVG

t_CL.AVG

t_CK.AVG

t_DS.BASE

t_DH.BASE

ps

10)11)

t_CK.AVG

ps

12)13)14)

13)14)15)

DQ and DM input setup time

DQ and DM input hold time

ps

175

––

ps

Control & address input pulse width for each input t_IPW

0.6

—

t_CK.AVG

ps

DQ and DM input pulse width for each input

Data-out high-impedance time from CK / CK

DQS/DQS low-impedance time from CK / CK

DQ low impedance time from CK/CK

t_DIPW

t_HZ

t_LZ.DQS

t_LZ.DQ

0.35

—

9)16)

17)

t_AC.MAX

240

t_AC.MIN

2 x t_AC.MIN

—

ps

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

ps

18)

CK half pulse width

t_HP

Min(t_CH.ABS

,

__

ps

t_CL.ABS

)

19)

20)

DQ hold skew factor

t_QHS

t_QH

—

340

—

ps

DQ/DQS output hold time from DQS

t

_HP– t_QHS

ps

Write command to DQS associated clock edges WL

RL–1

nCK

t_CK.AVG

21)

DQS latching rising transition to associated clock t_DQSS

– 0.25

+ 0.25

edges

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Write postamble

t_DQSH

t_DQSL

t_DSS

0.35

0.2

—

t_CK.AVG

ps

—

21)

—

t_DSH

0.2

—

t_WPST

t_WPRE

t_LS.BASE

t_LH.BASE

t_RPRE

t_RPST

t_RAS

0.4

0.6

—

Write preamble

0.35

200

275

0.9

22)23)

23)24)

25)26)

25)27)

28)

Address and control input setup time

Address and control input hold time

Read preamble

—

ps

1.1

0.6

70000

t_CK.AVG

ns

Read postamble

0.4

Active to precharge command

45

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Parameter

Symbol

DDR2–667

Unit

Notes^1)2)3)4)5)6)

7)8)

Min.

Max.

28)

Active to active command period for 1KB page

size products

t_RRD

7.5

—

ns

Active to active command period for 2KB page

size products

10

—

28)

Four Activate Window for 1KB page size products t_FAW

Four Activate Window for 2KB page size products t_FAW

37.5

—

ns

50

ns

CAS to CAS command delay

Write recovery time

t_CCD

t_WR

2

nCK

ns

28)

15

29)30)

28)31)

28)

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

7.5

nCK

ns

Internal write to read command delay

Internal Read to Precharge command delay

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_WTR

t_RTP

t_XSNR

t_XSRD

t_XP

7.5

ns

28)

t

_RFC+10

ns

200

2

nCK

Exit precharge power-down to any valid

command (other than NOP or Deselect)

Exit power down to read command

t_XARD

2

—

nCK

Exit active power-down mode to read command t_XARDS

7 – AL

(slow exit, lower power)

32)

CKE minimum pulse width ( high and low pulse t_CKE

width)

3

—

2

nCK

ODT turn-on delay

t_AOND

t_AON

2

nCK

ns

9)33)

ODT turn-on

t_AC.MIN

t

_AC.MAX+ 0.7

2 x t_CK.AVG

_AC.MAX+ 1

2.5

_AC.MAX+ 0.6

2.5 x t_CK.AVG

_AC.MAX+ 1

ODT turn-on (Power down mode)

t_AONPD

t

_AC.MIN+ 2

+

ns

t

ODT turn-off delay

t_AOFD

t_AOF

2.5

nCK

ns

34)35)

ODT turn-off

t_AC.MIN

t

ODT turn-off (Power down mode)

t_AOFPD

t

_AC.MIN+ 2

+

ns

t

ODT to power down entry latency

ODT to power down exit latency

Mode register set command cycle time

MRS command to ODT update delay

OCD drive mode output delay

t_ANPD

t_AXPD

t_MRD

t_MOD

t_OIT

3

8

2

0

––

nCK

ns

—

12

––

1)

ns

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t

_LS+ t_{CK .AVG}

+

ns

t_LH

1) For details and notes see the relevant Qimonda component data sheet

2)

_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V. See notes ^5)6)7)8)

V

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

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6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

.

8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

.

9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

t_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to

DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.

11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and

the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).

12) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 4.

13) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

15) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

V_IH.DC.MIN. See Figure 4.

16) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

17) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

18) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

19) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

20) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under

the max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

22) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 5.

23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

,

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

24) Input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 5.

25) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

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26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

28) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

t_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

29) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

30) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

31) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

32) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measured from t_AOND

34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD

.

35) When the device is operated with input clock jitter, this parameter needs to be derated by {–t_JIT.DUTY.MAX– t_{ERR(6-10PER).MAX}} and {–t_JIT.DUTY.MIN

– t_{ERR(6-10PER).MIN}} of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter

into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272 ps, t_{ERR(6- 10PER).MAX}= + 293 ps, t_JIT.DUTY.MIN= – 106 ps and t_JIT.DUTY.MAX= + 94 ps,

then t_{AOF.MIN(DERATED)}= t_AOF.MIN+ {– t_JIT.DUTY.MAX– t_{ERR(6-10PER).MAX}} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and t_{AOF.MAX(DERATED)}= t_AOF.MAX

+ {– t_JIT.DUTY.MIN– t_{ERR(6-10PER).MIN}} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)

FIGURE 3

Method for calculating transitions and endpoint

VOH - x mV

VTT + 2x mV

VTT + x mV

VOH - 2x mV

tLZ

tHZ

tRPRE begin point

tRPST end point

VOL + 2x mV

VOL + x mV

VTT - x mV

VTT - 2x mV

T1 T2

tLZ,tRPRE begin point = 2*T1-T2

T1 T2

tHZ,tRPST end point = 2*T1-T2

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FIGURE 4

Differential input waveform timing - t_DSand t_DS

DQS

tDH

tDS

V_DDQ

V_IH(ac)min

V_IH(dc)min

V_REF(dc)

V_IL(dc)max

V_IL(ac)max

V_SS

FIGURE 5

Differential input waveform timing - t_lSand t_lH

CK

tIH

tIS

V_DDQ

V_IH(ac)min

V_IH(dc)min

V_REF(dc)

V_IL(dc)max

V_IL(ac)max

V_SS

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TABLE 18

Timing Parameter by Speed Grade - DDR2–533

Parameter

Symbol

DDR2–533

Unit

Notes^1)2)3)4)5)

6)7)

Min.

Max.

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

–500

2

+500

—

ps

t_CCD

t_CH

t_CKE

t_CL

t_CK

0.45

3

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

0.45

WR + t_RP

0.55

—

8)18)

9)

Auto-Precharge write recovery + precharge

time

t_DAL

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_CK+ t_IH

225

––

—

ns

ps

10)

11)

DQ and DM input hold time (differential data

strobe)

t

_DH(base)

DQ and DM input hold time (single ended data

strobe)

_DH1(base)

–25

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

t_DIPW

0.35

–450

0.35

—

t_CK

ps

t_CK

ps

t_DQSCK

+450

—

DQS input low (high) pulse width (write cycle) t_DQSL,H

11)

DQS-DQ skew (for DQS & associated DQ

signals)

t_DQSQ

300

Write command to 1st DQS latching transition t_DQSS

– 0.25

100

+ 0.25

—

t_CK

11)

DQ and DM input setup time (differential data

strobe)

t

_DS(base)

ps

DQ and DM input setup time (single ended data t_DS1(base)

strobe)

–25

0.2

—

ps

DQS falling edge hold time from CK (write

cycle)

t_DSH

t_CK

DQS falling edge to CK setup time (write cycle) t_DSS

0.2

—

t_CK

ns

Four Activate Window period

t_FAW

37.5

13)

12)

13)

11)

50

Clock half period

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

—

ps

t_CK

t_IH(base)

t_IPW

375

0.6

Address and control input pulse width

(each input)

—

11)

14)

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

250

—

ps

t_CK

ns

2 × t_AC.MIN

t_AC.MAX

—

t_AC.MIN

2

0

t_OIT

12

Data output hold time from DQS

t_QH

t

_HP–t_QHS

—

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Unbuffered DDR2 SDRAM Modules

Parameter

Symbol

DDR2–533

Min.

Unit

Notes^1)2)3)4)5)

6)7)

Max.

Data hold skew factor

t_QHS

t_REFI

—

400

7.8

3.9

—

ps

µs

ns

14)15)

16)18)

17)

Average periodic refresh Interval

—

Auto-Refresh to Active/Auto-Refresh

command period

t_RFC

105

Precharge-All (4 banks) command period

Precharge-All (8 banks) command period

Read preamble

t_RP

t

_RP+ 1t_CK

—

ns

t_CK

ns

t_CK

ns

t_RP

15 + 1tCK

0.9

—

14)

t_RPRE

t_RPST

t_RRD

1.1

0.60

—

14)

Read postamble

0.40

7.5

14)18)

16)20)

Active bank A to Active bank B command

period

10

—

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

—

t_WPRE

t_WPST

t_WR

0.25 x t_CK

0.40

15

—

19)

20)

Write postamble

0.60

—

Write recovery time for write without Auto-

Precharge

Write recovery time for write with Auto-

Precharge

WR

t

_WR/t_CK

t_CK

21)

22)

Internal Write to Read command delay

t_WTR

7.5

2

—

ns

Exit power down to any valid command

(other than NOP or Deselect)

t_XARD

t_CK

22)

Exit active power-down mode to Read

command (slow exit, lower power)

t_XARDS

t_XP

6 – AL

2

—

t_CK

Exit precharge power-down to any valid

command (other than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant Qimonda component data sheet

2)

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ±0.1 V. See notes ^5)6)7)8)

V

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,

input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

.

8) For each of the terms, if not already an integer, round to the next highest integer. t_CKrefers to the application clock period. WR refers to

the WR parameter stored in the MR.

9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.

10) For timing definition, refer to the Component data sheet.

11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate

mis-match between DQS / DQS and associated DQ in any given cycle.

12) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can

be greater than the minimum specification limits for t_CLand t_CH).

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13) The t_HZ, t_RPSTand t_LZ, t_RPREparameters are referenced to a specific voltage level, which specify when the device output is no longer driving

(t_HZ,t_RPST), or begins driving (t_LZ,t_RPRE). t_HZand t_LZtransitions occur in the same access time windows as valid data transitions.These

parameters are verified by design and characterization, but not subject to production test.

14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

15) 0 °C≤ T_CASE≤ 85 °C

16) 85 °C < T_CASE≤ 95 °C

17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.

18) The t_RRDtiming parameter depends on the page size of the DRAM organization. See Table 4 “Ordering Information for RoHS

Compliant Products” on Page 5.

19) The maximum limit for the t_WPSTparameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

20) WR must be programmed to fulfill the minimum requirement for the t_WRtiming parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded

up to the next integer value. t_DAL= WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK

refers to the application clock period. WR refers to the WR parameter stored in the MRS.

21) Minimum t_WTRis two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.

22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-

down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARDcan be used. In “low active power-down mode” (MR, A12 =”1”) a slow

power-down exit timing t_XARDShas to be satisfied.

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TABLE 19

Timing Parameter by Speed Grade - DDR2-400

Parameter

Symbol

DDR2–400

Unit

Notes^1)2)3)4)5)

6)7)

Min.

Max.

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

–600

2

+600

—

ps

t_CCD

t_CH

t_CKE

t_CL

t_CK

0.45

3

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

0.45

WR + t_RP

0.55

—

8)22)

9)

Auto-Precharge write recovery + precharge

time

t_DAL

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_CK+ t_IH

275

––

—

ns

ps

10)

11)

DQ and DM input hold time (differential data

strobe)

t

_DH(base)

DQ and DM input hold time (single ended data

strobe)

_DH1(base)

–25

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

t_DIPW

0.35

–500

0.35

—

t_CK

ps

t_CK

ps

t_DQSCK

+500

—

DQS input low (high) pulse width (write cycle) t_DQSL,H

11)

DQS-DQ skew (for DQS & associated DQ

signals)

t_DQSQ

350

Write command to 1st DQS latching transition t_DQSS

– 0.25

150

+ 0.25

—

t_CK

11)

DQ and DM input setup time (differential data

strobe)

t

_DS(base)

ps

DQ and DM input setup time (single ended

data strobe)

t

_DS1(base)

–25

0.2

—

ps

DQS falling edge hold time from CK (write

cycle)

t_DSH

t_CK

DQS falling edge to CK setup time (write cycle) t_DSS

0.2

—

t_CK

ns

Four Activate Window period

t_FAW

37.5

13)

12)

13)

11)

50

Clock half period

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

—

ps

t_CK

t_IH(base)

t_IPW

475

0.6

Address and control input pulse width

(each input)

—

11)

14)

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

350

—

ps

t_CK

ns

2 × t_AC.MIN

t_AC.MAX

—

t_AC.MIN

2

0

t_OIT

12

Data output hold time from DQS

t_QH

t

_HP–t_QHS

—

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Unbuffered DDR2 SDRAM Modules

Parameter

Symbol

DDR2–400

Min.

Unit

Notes^1)2)3)4)5)

6)7)

Max.

Data hold skew factor

t_QHS

t_REFI

—

450

7.8

3.9

—

ps

µs

ns

14)15)

16)18)

17)

Average periodic refresh Interval

—

Auto-Refresh to Active/Auto-Refresh

command period

105

Precharge-All (4 banks) command period

Precharge-All (8 banks) command period

Read preamble

t_RP

t

_RP+ 1t_CK

—

ns

t_CK

ns

t_CK

ns

t_RP

15 + 1t_CK

0.9

—

14)

t_RPRE

t_RPST

t_RRD

1.1

0.60

—

14)

Read postamble

0.40

7.5

14)18)

16)20)

Active bank A to Active bank B command

period

10

—

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

—

t_WPRE

t_WPST

t_WR

0.25 x t_CK

0.40

15

—

19)

20)

Write postamble

0.60

—

Write recovery time for write without Auto-

Precharge

Write recovery time for write with Auto-

Precharge

WR

t

_WR/t_CK

t_CK

21)

22)

Internal Write to Read command delay

t_WTR

10

2

—

ns

Exit power down to any valid command

(other than NOP or Deselect)

t_XARD

t_CK

22)

Exit active power-down mode to Read

command (slow exit, lower power)

t_XARDS

t_XP

6 – AL

2

—

t_CK

Exit precharge power-down to any valid

command (other than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant Qimonda component data sheet

2)

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ±0.1 V. See notes ^5)6)7)8)

V

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,

input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

.

8) For each of the terms, if not already an integer, round to the next highest integer. t_CKrefers to the application clock period. WR refers to

the WR parameter stored in the MR.

9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.

10) For timing definition, refer to the Component data sheet.

11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate

mis-match between DQS / DQS and associated DQ in any given cycle.

12) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can

be greater than the minimum specification limits for t_CLand t_CH).

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

13) The t_HZ, t_RPSTand t_LZ, t_RPREparameters are referenced to a specific voltage level, which specify when the device output is no longer driving

(t_HZ,t_RPST), or begins driving (t_LZ,t_RPRE). t_HZand t_LZtransitions occur in the same access time windows as valid data transitions.These

parameters are verified by design and characterization, but not subject to production test.

14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

15) 0 °C≤ T_CASE≤ 85 °C

16) 85 °C < T_CASE≤ 95 °C

17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.

18) The t_RRDtiming parameter depends on the page size of the DRAM organization. See Table 4 “Ordering Information for RoHS

Compliant Products” on Page 5.

19) The maximum limit for the t_WPSTparameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

20) WR must be programmed to fulfill the minimum requirement for the t_WRtiming parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded

up to the next integer value. t_DAL= WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK

refers to the application clock period. WR refers to the WR parameter stored in the MRS.

21) Minimum t_WTRis two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.

22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-

down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARDcan be used. In “low active power-down mode” (MR, A12 =”1”) a slow

power-down exit timing t_XARDShas to be satisfied.

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Unbuffered DDR2 SDRAM Modules

3.3.3

ODT AC Electrical Characteristics

This chapter contains the ODT AC electrical characteristics tables.

TABLE 20

ODT AC Characteristics and Operating Conditions for DDR2-667

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

t_AOND

t_AON

ODT turn-on delay

2

t_CK

ns

t_CK

ns

t_CK

1)

2)

ODT turn-on

t_AC.MIN

t_AC.MAX+ 0.7 ns

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

t

_AC.MIN+ 2 ns

2 t_{CK +}t_AC.MAX+ 1 ns

2.5

ODT turn-off

t_AC.MIN

t_AC.MAX+ 0.6 ns

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

t

_AC.MIN+ 2 ns

2.5 t_{CK +}t_AC.MAX+ 1 ns

3

8

—

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measure from t_AOND

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD

.

TABLE 21

ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

t_AOND

t_AON

ODT turn-on delay

2

t_CK

ns

t_CK

ns

t_CK

1)

2)

ODT turn-on

t_AC.MIN

t_AC.MAX+ 1 ns

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

t

_AC.MIN+ 2 ns

2 t_{CK +}t_AC.MAX+ 1 ns

2.5

ODT turn-off

t_AC.MIN

t_AC.MAX+ 0.6 ns

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

t

_AC.MIN+ 2 ns

2.5 t_{CK +}t_AC.MAX+ 1 ns

3

8

—

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measure from t_AOND

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

.

Both are measured from t_AOFD

.

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

3.4

Currents Specifications and Conditions

Chapter contains current tables for each of the product types and the definitions of the various currents.

•

Table 22 “IDD Measurement Conditions” on Page 32

Table 23 “Definitions for IDD” on Page 33

Table 24 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A” on Page 34

Table 25 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A” on Page 35

Table 26 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A” on Page 36

TABLE 22

_DDMeasurement Conditions

I

Parameter

Symbol Note

1)2)3)4)5)

Operating Current 0

I_DD0

One bank Active - Precharge; t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN, CKE is HIGH, CS is HIGH between

valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.

6)

Operating Current 1

I_DD1

One bank Active - Read - Precharge; I_OUT= 0 mA, BL = 4, t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN

,

t

_RCD= t_RCD.MIN, AL = 0, CL = CL_MIN; CKE is HIGH, CS is HIGH between valid commands. Address and

control inputs are SWITCHING, Databus inputs are SWITCHING.

Precharge Standby Current

I_DD2N

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are SWITCHING,

Databus inputs are SWITCHING.

Precharge Power-Down Current

Other control and address inputs are STABLE, Data bus inputs are FLOATING.

I_DD2P

I_DD2Q

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are STABLE,

Data bus inputs are FLOATING.

Active Standby Current

I_DD3N

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX, t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

I_DD3P(0)

I_DD3P(1)

I_DD4R

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

6)

Operating Current - Burst Read

All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CKMIN; t_RAS= t_RASMAX

;

t

_RP= t_RPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

bus inputs are SWITCHING; I_OUT= 0mA.

Operating Current - Burst Write

I_DD4W

All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX., t_RP= t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

Burst Refresh Current

I_DD5B

t

_CK= t_CK.MIN., Refresh command every t_RFC= t_RFC.MINinterval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

Parameter

Symbol Note

1)2)3)4)5)

Distributed Refresh Current

I_DD5D

t

_CK= t_CK.MIN., Refresh command every t_RFC= t_REFIinterval, CKE is LOW and CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data

bus inputs are FLOATING. I_DD6current values are guaranteed up to T_CASEof 85 °C max.

6)

All Bank Interleave Read Current

I_DD7

All banks are being interleaved at minimum t_RCwithout violating t_RRDusing a burst length of 4. Control

and address bus inputs are STABLE during DESELECTS. I_out= 0 mA.

1)

2)

V

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

I_DDspecifications are tested after the device is properly initialized and I_DDparameter are specified with ODT disabled.

3) Definitions for I_DDsee Table 23

4) For two rank modules: All active current measurements in the same I_DDcurrent mode. The other rank is in I_DD2PPrecharge Power-Down

Mode

5) For details and notes see the relevant Qimonda component data sheet

6)

I_DD1, I_DD4Rand I_DD7current measurements are defined with the outputs disabled (I_OUT= 0 mA). To achieve this on module level the output

buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.

TABLE 23

Definitions for I_DD

Parameter

LOW

Description

V_IN≤ V_IL(ac).MAX, HIGH is defined as V_IN≥ V_IH(ac).MIN

Inputs are stable at a HIGH or LOW level

Inputs are V_REF= V_DDQ/2

STABLE

FLOATING

SWITCHING

Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control

signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ

signals not including mask or strobes

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Unbuffered DDR2 SDRAM Modules

TABLE 24

_DDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A

I

Product Type

Unit Note¹⁾

Organization

256MB

1 Rank

×64

512MB

1 Rank

×64

512MB

1 Rank

×72

1GB

2 Ranks

×64

1GB

2 Ranks

×72

–3

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

380

440

200

20

600

720

400

40

680

810

450

50

640

760

800

80

720

860

900

90

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

160

200

80

320

400

150

50

360

450

170

50

640

800

300

100

1080

1160

100

80

720

900

340

110

1220

1310

110

90

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

20

600

680

560

20

1040

1120

50

1170

1260

50

I_DD4W

I_DD5B

I_DD5D

I_DD6

20

40

45

I_DD7

960

1240

1400

1280

1440

1) Calculated values from component data. ODT disabled. I_DD1,

2) The other rank is in I_DD2PPrecharge Power-Down mode

3) Both ranks are in the same I_DDcurrent mode

I

_DD4R,and I_DD7,are defined with the outputs disabled.

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

TABLE 25

_DDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A

I

Product Type

Unit Note¹⁾

Organization

256MB

1 Rank

×64

512MB

1 Rank

×64

512MB

1 Rank

×72

1GB

2 Ranks

×64

2 Ranks

×72

–3S

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

360

420

200

20

570

680

400

40

640

770

450

50

610

720

800

80

680

810

900

90

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

160

200

80

320

400

150

50

360

450

170

50

640

800

300

100

1080

1160

100

80

720

900

340

110

1220

1310

110

90

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

20

600

680

560

20

1040

1120

50

1170

1260

50

I_DD4W

I_DD5B

I_DD5D

I_DD6

20

40

45

I_DD7

910

1180

1320

1220

1370

1) Calculated values from component data. ODT disabled. I_DD1,

2) The other rank is in I_DD2PPrecharge Power-Down mode

3) Both ranks are in the same I_DDcurrent mode

I

_DD4R,and I_DD7,are defined with the outputs disabled.

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

TABLE 26

_DDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A

I

Product Type

Unit Note¹⁾

Organization

256MB

1 Rank

×64

512MB

1 Rank

×64

512MB

1 Rank

×72

1GB

2 Ranks

×64

2 Ranks

×72

–3.7

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

320

360

160

20

520

600

320

30

590

680

360

40

550

630

640

60

620

710

720

70

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

120

160

60

240

320

130

40

270

360

140

50

480

640

260

80

540

720

290

90

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

20

400

440

520

20

720

760

1040

50

810

860

1170

50

750

790

1070

100

64

850

890

1210

110

72

I_DD4W

I_DD5B

I_DD5D

I_DD6

16

32

36

I_DD7

880

1120

1260

1160

1300

1) Calculated values from component data. ODT disabled. I_DD1,

2) The other rank is in I_DD2PPrecharge Power-Down mode

3) Both ranks are in the same I_DDcurrent mode

I

_DD4R,and I_DD7,are defined with the outputs disabled.

Rev. 1.41, 2007-05

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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 27

_DDSpecification for HYS[64/72]T[32/64/128]xxxHU–5–A

I

Product Type

Unit Note¹⁾

Organization

256MB

1 Rank

×64

512MB

1 Rank

×64

512MB

1 Rank

×72

1GB

2 Ranks

×64

1GB

2 Ranks

×72

–5

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

280

300

130

20

440

480

260

30

500

540

290

40

470

510

60

530

580

70

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

100

140

50

200

280

100

40

230

320

120

50

400

560

210

80

450

630

230

90

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

20

340

360

480

20

560

600

960

50

630

680

1080

50

590

630

990

100

64

670

710

1120

110

72

I_DD4W

I_DD5B

I_DD5D

I_DD6

16

32

36

I_DD7

840

1040

1170

1070

1210

1) Calculated values from component data. ODT disabled. I_DD1,

2) The other rank is in I_DD2PPrecharge Power-Down mode

3) Both ranks are in the same I_DDcurrent mode

I

_DD4R,and I_DD7,are defined with the outputs disabled.

Rev. 1.41, 2007-05

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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

4

SPD Codes

This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands

for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.

List of SPD Code Tables

•

Table 28 “HYS[64/72]T[32/64/128]0x0HU-3-A” on Page 38

Table 29 “HYS[64/72]T[32/64]x00HU-3S-A” on Page 43

Table 30 “HYS[64/72]T128x20HU-3S-A” on Page 48

Table 31 “HYS[64/72]T[32/64]x00HU-3.7-A” on Page 52

Table 32 “HYS[64/72]T128x20HU-3.7-A” on Page 57

Table 33 “HYS[64/72]T[32/64/128]0x0HU-5-A” on Page 61

TABLE 28

HYS[64/72]T[32/64/128]0x0HU-3-A

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

5300U–

444

PC2–

5300U–

444

PC2–

5300E–

444

PC2–

5300U–

444

PC2–

5300E–

444

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

0

1

2

3

4

5

6

7

8

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0D

0A

60

40

00

05

80

08

0E

0A

60

40

00

05

80

08

0E

0A

60

48

00

05

80

08

0E

0A

61

40

00

05

80

08

0E

0A

61

48

00

05

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

Not used

Interface Voltage Level

Rev. 1.41, 2007-05

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Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

5300U–

444

PC2–

5300U–

444

PC2–

5300E–

444

PC2–

5300U–

444

PC2–

5300E–

444

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

9

t

_CK@ CL_MAX(Byte 18) [ns]

30

45

00

82

10

00

0C

04

38

01

02

00

03

30

45

50

60

30

28

30

2D

40

20

30

45

00

82

08

00

0C

04

38

01

02

00

03

30

45

50

60

30

1E

30

2D

80

20

30

45

02

82

08

00

0C

04

38

01

02

00

03

30

45

50

60

30

1E

30

2D

80

20

30

45

00

82

08

00

0C

04

38

01

02

00

03

30

45

50

60

30

1E

30

2D

80

20

30

45

02

82

08

00

0C

04

38

01

02

00

03

30

45

50

60

30

1E

30

2D

80

20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

_AS.MINand t_CS.MIN[ns]

t

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Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

5300U–

444

PC2–

5300U–

444

PC2–

5300E–

444

PC2–

5300U–

444

PC2–

5300E–

444

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

t

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

27

10

17

3C

1E

00

39

69

80

18

22

00

55

72

67

36

24

29

1A

52

1E

27

10

17

3C

1E

00

39

69

80

18

22

00

53

78

4F

39

26

2B

1B

4A

20

27

10

17

3C

1E

00

39

69

80

18

22

00

53

78

4F

39

26

2B

1B

4A

20

27

10

17

3C

1E

00

39

69

80

18

22

00

53

78

4F

39

26

2B

1B

4A

20

27

10

17

3C

1E

00

39

69

80

18

22

00

53

78

4F

39

26

2B

1B

4A

20

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ∆T_4R4WDelta

T

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

Rev. 1.41, 2007-05

40

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

5300U–

444

PC2–

5300U–

444

PC2–

5300E–

444

PC2–

5300U–

444

PC2–

5300E–

444

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

∆T₇(DT7)

34

00

12

A2

7F

51

00

xx

23

00

12

B0

7F

51

00

xx

23

00

12

C2

7F

51

00

xx

23

00

12

B1

7F

51

00

xx

23

00

12

C3

7F

51

00

xx

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

36

34

54

33

32

30

36

34

54

36

34

30

37

32

54

36

34

30

36

34

54

31

32

38

30

32

37

32

54

31

32

38

30

32

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Rev. 1.41, 2007-05

41

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

5300U–

444

PC2–

5300U–

444

PC2–

5300E–

444

PC2–

5300U–

444

PC2–

5300E–

444

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Product Type, Char 9

48

55

33

41

20

7x

xx

00

FF

48

55

33

41

20

9x

xx

00

FF

48

55

33

41

20

9x

xx

00

FF

30

48

55

33

41

20

9x

xx

00

FF

30

48

55

33

41

20

9x

xx

00

FF

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

42

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 29

HYS[64/72]T[32/64]x00HU-3S-A

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300E–

555

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0D

0A

60

40

00

05

30

45

00

82

10

00

0C

04

38

01

02

00

80

08

0D

0A

60

40

00

05

30

45

00

82

10

00

0C

04

38

01

02

00

80

08

0E

0A

60

40

00

05

30

45

00

82

08

00

0C

04

38

01

02

00

80

08

0E

0A

60

40

00

05

30

45

00

82

08

00

0C

04

38

01

02

00

80

08

0E

0A

60

48

00

05

30

45

02

82

08

00

0C

04

38

01

02

00

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Rev. 1.41, 2007-05

43

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300E–

555

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

Component Attributes

03

3D

50

60

3C

28

3C

2D

40

20

27

10

17

3C

1E

00

3C

69

80

18

22

03

3D

50

60

3C

28

3C

2D

40

20

27

10

17

3C

1E

00

3C

69

80

18

22

03

3D

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

03

3D

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

03

3D

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

Rev. 1.41, 2007-05

44

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300E–

555

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

PLL Relock Time

00

55

72

5F

36

24

29

1A

52

1E

31

00

12

CA

7F

51

00

55

72

5F

36

24

29

1A

52

1E

31

00

12

CA

7F

51

00

53

78

4B

39

26

2B

1B

4A

20

22

00

12

DE

7F

51

00

53

78

4B

39

26

2B

1B

4A

20

22

00

12

DE

7F

51

00

53

78

4B

39

26

2B

1B

4A

20

22

00

12

F0

7F

51

T_CASE.MAXDelta / ∆T_4R4WDelta

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Rev. 1.41, 2007-05

45

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300E–

555

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

00

xx

36

34

54

33

32

30

48

55

33

53

41

20

4x

xx

00

xx

36

34

54

33

32

39

30

48

55

33

53

41

20

2x

xx

00

xx

36

34

54

36

34

30

48

55

33

53

41

20

4x

xx

00

xx

36

34

54

36

34

39

30

48

55

33

53

41

20

2x

xx

00

xx

37

32

54

36

34

30

48

55

33

53

41

20

4x

xx

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Rev. 1.41, 2007-05

46

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300U–

555

PC2–

5300E–

555

JEDEC SPD Revision

Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2

Byte#

Description

HEX

94

Module Manufacturing Date Week

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

47

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 30

HYS[64/72]T128x20HU-3S-A

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–5300U–555 PC2–5300U–555 PC2–5300E–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0E

0A

61

40

00

05

30

45

00

82

08

00

0C

04

38

01

02

00

03

3D

80

08

0E

0A

61

40

00

05

30

45

00

82

08

00

0C

04

38

01

02

00

03

3D

80

08

0E

0A

61

48

00

05

30

45

02

82

08

00

0C

04

38

01

02

00

03

3D

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_MAX-1 (Byte 18) [ns]

Rev. 1.41, 2007-05

48

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–5300U–555 PC2–5300U–555 PC2–5300E–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

t

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

00

53

78

4B

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

00

53

78

4B

50

60

3C

1E

3C

2D

80

20

27

10

17

3C

1E

00

3C

69

80

18

22

00

53

78

4B

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ∆T_4R4WDelta

T

Psi(T-A) DRAM

∆T₀(DT0)

Rev. 1.41, 2007-05

49

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–5300U–555 PC2–5300U–555 PC2–5300E–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

39

26

2B

1B

4A

20

22

00

12

DF

7F

51

00

xx

39

26

2B

1B

4A

20

22

00

12

DF

7F

51

00

xx

39

26

2B

1B

4A

20

22

00

12

F1

7F

51

00

xx

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

36

34

54

36

34

54

37

32

54

Product Type, Char 2

Product Type, Char 3

Rev. 1.41, 2007-05

50

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–5300U–555 PC2–5300U–555 PC2–5300E–555

JEDEC SPD Revision

Rev. 1.2

HEX

Rev. 1.2

HEX

Rev. 1.2

HEX

Byte#

Description

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Product Type, Char 4

31

32

38

30

32

30

48

55

33

53

41

20

4x

xx

00

FF

31

32

38

39

32

30

48

55

33

53

41

20

2x

xx

00

FF

31

32

38

30

32

30

48

55

33

53

41

20

4x

xx

00

FF

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

51

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 31

HYS[64/72]T[32/64]x00HU-3.7-A

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200E–

444

JEDEC SPD Revision

Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1

Byte#

Description

HEX

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0D

0A

60

40

00

05

3D

50

00

82

10

00

0C

04

38

00

02

00

80

08

0D

0A

60

40

00

05

3D

50

00

82

10

00

0C

04

38

00

02

00

80

08

0E

0A

60

40

00

05

3D

50

00

82

08

00

0C

04

38

00

02

00

80

08

0E

0A

60

40

00

05

3D

50

00

82

08

00

0C

04

38

00

02

00

80

08

0E

0A

60

48

00

05

3D

50

02

82

08

00

0C

04

38

00

02

00

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Rev. 1.41, 2007-05

52

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200E–

444

JEDEC SPD Revision

Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1

Byte#

Description

HEX

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

Component Attributes

01

3D

50

60

3C

28

3C

2D

40

25

37

10

22

3C

1E

00

3C

69

80

1E

28

03

3D

50

60

3C

28

3C

2D

40

25

37

10

22

3C

1E

00

3C

69

80

1E

28

01

3D

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

03

3D

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

01

3D

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

Rev. 1.41, 2007-05

53

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200E–

444

JEDEC SPD Revision

Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1

Byte#

Description

HEX

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

PLL Relock Time

00

53

72

53

2B

1D

23

16

36

1C

30

00

11

BA

7F

51

00

53

72

53

2B

1D

23

16

36

1C

30

00

12

BD

7F

51

00

51

78

3F

2E

1E

24

17

34

1E

20

00

11

D0

7F

51

00

51

78

3F

2E

1E

24

17

34

1E

20

00

12

D3

7F

51

00

51

78

3F

2E

1E

24

17

34

1E

20

00

11

E2

7F

51

T_CASE.MAXDelta / ∆T_4R4WDelta

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Rev. 1.41, 2007-05

54

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200E–

444

JEDEC SPD Revision

Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1

Byte#

Description

HEX

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

00

xx

36

34

54

33

32

30

48

55

33

2E

37

41

20

5x

xx

00

xx

36

34

54

33

32

39

30

48

55

33

2E

37

41

20

2x

xx

00

xx

36

34

54

36

34

30

48

55

33

2E

37

41

20

5x

xx

00

xx

36

34

54

36

34

39

30

48

55

33

2E

37

41

20

2x

xx

00

xx

37

32

54

36

34

30

48

55

33

2E

37

41

20

5x

xx

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Rev. 1.41, 2007-05

55

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

×64

×72

1 Rank

(×16)

(×8)

Label Code

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200U–

444

PC2–

4200E–

444

JEDEC SPD Revision

Rev. 1.1 Rev. 1.2 Rev. 1.1 Rev. 1.2 Rev. 1.1

Byte#

Description

HEX

94

Module Manufacturing Date Week

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

56

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 32

HYS[64/72]T128x20HU-3.7-A

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

Rev. 1.2

HEX

Rev. 1.1

HEX

Byte#

Description

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0E

0A

61

40

00

05

3D

50

00

82

08

00

0C

04

38

00

02

00

01

3D

80

08

0E

0A

61

40

00

05

3D

50

00

82

08

00

0C

04

38

00

02

00

03

3D

80

08

0E

0A

61

48

00

05

3D

50

02

82

08

00

0C

04

38

00

02

00

01

3D

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_MAX-1 (Byte 18) [ns]

Rev. 1.41, 2007-05

57

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

Rev. 1.2

HEX

Rev. 1.1

HEX

Byte#

Description

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

t

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

00

51

78

3F

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

00

51

78

3F

50

60

3C

1E

3C

2D

80

25

37

10

22

3C

1E

00

3C

69

80

1E

28

00

51

78

3F

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ∆T_4R4WDelta

T

Psi(T-A) DRAM

∆T₀(DT0)

Rev. 1.41, 2007-05

58

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

Rev. 1.2

HEX

Rev. 1.1

HEX

Byte#

Description

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

2E

1E

24

17

34

1E

20

00

11

D1

7F

51

00

xx

2E

1E

24

17

34

1E

20

00

12

D4

7F

51

00

xx

2E

1E

24

17

34

1E

20

00

11

E3

7F

51

00

xx

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

36

34

54

36

34

54

37

32

54

Product Type, Char 2

Product Type, Char 3

Rev. 1.41, 2007-05

59

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

1 GByte

×64

1 GByte

×64

1 GByte

×72

2 Ranks (×8)

Label Code

PC2–4200U–444 PC2–4200U–444 PC2–4200E–444

JEDEC SPD Revision

Rev. 1.1

HEX

Rev. 1.2

HEX

Rev. 1.1

HEX

Byte#

Description

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Product Type, Char 4

31

32

38

30

32

30

48

55

33

2E

37

41

20

5x

xx

00

FF

31

32

38

39

32

30

48

55

33

2E

37

41

20

2x

xx

00

FF

31

32

38

30

32

30

48

55

33

2E

37

41

20

5x

xx

00

FF

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

60

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

TABLE 33

HYS[64/72]T[32/64/128]0x0HU-5-A

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

3200U–

333

PC2–

3200U–

333

PC2–

3200E–

333

PC2–

3200U–

333

PC2–

3200E–

333

JEDEC SPD Revision

Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1

Byte#

Description

HEX

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0D

0A

60

40

00

05

50

60

00

82

10

00

0C

04

38

00

02

00

80

08

0E

0A

60

40

00

05

50

60

00

82

08

00

0C

04

38

00

02

00

80

08

0E

0A

60

48

00

05

50

60

02

82

08

00

0C

04

38

00

02

00

80

08

0E

0A

61

40

00

05

50

60

00

82

08

00

0C

04

38

00

02

00

80

08

0E

0A

61

48

00

05

50

60

02

82

08

00

0C

04

38

00

02

00

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Rev. 1.41, 2007-05

61

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

3200U–

333

PC2–

3200U–

333

PC2–

3200E–

333

PC2–

3200U–

333

PC2–

3200E–

333

JEDEC SPD Revision

Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1

Byte#

Description

HEX

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

Component Attributes

01

50

60

50

60

3C

28

3C

28

40

35

47

15

27

3C

28

1E

00

37

69

80

23

2D

01

50

60

50

60

3C

1E

3C

28

80

35

47

15

27

3C

28

1E

00

37

69

80

23

2D

01

50

60

50

60

3C

1E

3C

28

80

35

47

15

27

3C

28

1E

00

37

69

80

23

2D

01

50

60

50

60

3C

1E

3C

28

80

35

47

15

27

3C

28

1E

00

37

69

80

23

2D

01

50

60

50

60

3C

1E

3C

28

80

35

47

15

27

3C

28

1E

00

37

69

80

23

2D

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

Rev. 1.41, 2007-05

62

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

3200U–

333

PC2–

3200U–

333

PC2–

3200E–

333

PC2–

3200U–

333

PC2–

3200E–

333

JEDEC SPD Revision

Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1

Byte#

Description

HEX

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

PLL Relock Time

00

51

72

43

23

1D

19

1C

16

2E

1A

2D

00

11

02

7F

51

00

51

78

33

24

1E

1B

1E

17

28

1B

1E

00

11

1A

7F

51

00

51

78

33

24

1E

1B

1E

17

28

1B

1E

00

11

2C

7F

51

00

51

78

33

24

1E

1B

1E

17

28

1B

1E

00

11

1B

7F

51

00

51

78

33

24

1E

1B

1E

17

28

1B

1E

00

11

2D

7F

51

T_CASE.MAXDelta / ∆T_4R4WDelta

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Rev. 1.41, 2007-05

63

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

3200U–

333

PC2–

3200U–

333

PC2–

3200E–

333

PC2–

3200U–

333

PC2–

3200E–

333

JEDEC SPD Revision

Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1

Byte#

Description

HEX

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

00

xx

36

34

54

33

32

30

48

55

35

41

20

5x

xx

00

xx

36

34

54

36

34

30

48

55

35

41

20

5x

xx

00

xx

37

32

54

36

34

30

48

55

35

41

20

5x

xx

00

xx

36

34

54

31

32

38

30

32

30

48

55

35

41

20

5x

xx

00

xx

37

32

54

31

32

38

30

32

30

48

55

35

41

20

5x

xx

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Rev. 1.41, 2007-05

64

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Product Type

Organization

256MB

512MB

1 GByte 1 GByte

×64

×72

×64

×72

1 Rank

2 Ranks 2 Ranks

(×16)

(×8)

Label Code

PC2–

3200U–

333

PC2–

3200U–

333

PC2–

3200E–

333

PC2–

3200U–

333

PC2–

3200E–

333

JEDEC SPD Revision

Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1 Rev. 1.1

Byte#

Description

HEX

94

Module Manufacturing Date Week

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

xx

00

FF

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.41, 2007-05

65

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

5

Package Outlines

This chapter contains the package outlines of the products.

FIGURE 6

Package Outline Raw Card A L-DIM-240-1

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"URR MAXꢌ ꢀꢌꢈ ALLOWED

',$ꢀꢅꢉꢂꢇ

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

66

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 7

Package Outline Raw Card B L-DIM-240-2

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Notes

1. The chip is only found on ECC modules.

2. Drawing according to ISO 8015

3. Dimensions in mm

4. General tolerances +/- 0.15

Rev. 1.41, 2007-05

67

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 8

Package Outline Raw Card C L-DIM-240-3

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ꢁ

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" #

"URR MAXꢌ ꢀꢌꢈ ALLOWED

',$ꢀꢅꢉꢂꢈ

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

68

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 9

Package Outline L-DIM-240-8

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"URR MAXꢌ ꢀꢌꢈ ALLOWED

',$ꢀꢁꢀꢃꢊ

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

69

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 10

Package Outline L-DIM-240-9

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"URR MAXꢌ ꢀꢌꢈ ALLOWED

',$ꢀꢁꢀꢃꢅ

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

70

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 11

Package Outline Raw Card F L-DIM-240-6

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"URR MAXꢌ ꢀꢌꢈ ALLOWED

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Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

71

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

FIGURE 12

Package Outline Raw Card G L-DIM-240-7

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Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

Rev. 1.41, 2007-05

72

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

6

Product Type Nomenclature

Qimonda´s nomenclature uses simple coding combined with some propriatory coding. Table 34 provides examples for module

and component product type number as well as the field number. The detailed field description together with possible values

and coding explanation is listed for modules in Table 35 and for components in Table 36.

TABLE 34

Nomenclature Fields and Examples

Example for

Field Number

1

2

3

4

5

6

7

8

9

10

11

Micro-DIMM

DDR2 DRAM

HYS

HYB

64

18

T

64/128

0

2

0

K

A

M

C

–5

–A

512/1G 16

TABLE 35

DDR2 DIMM Nomenclature

Field

Description

Values

Coding

1

2

Qimonda Module Prefix

Module Data Width [bit]

HYS

64

Constant

Non-ECC

ECC

72

3

4

DRAM Technology

T

DDR2

Memory Density per I/O [Mbit];

Module Density¹⁾

32

256 MByte

512 MByte

1 GByte

2 GByte

4 GByte

64

128

256

512

0 .. 9

0, 2, 4

0 .. 9

A .. Z

D

5

6

7

8

9

Raw Card Generation

Number of Module Ranks

Product Variations

Look up table

1, 2, 4

Look up table

SO-DIMM

Package, Lead-Free Status

Module Type

M

Micro-DIMM

Registered

Unbuffered

Fully Buffered

R

U

F

Rev. 1.41, 2007-05

73

03292006-EZUJ-JY4S

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Field

Description

Values

Coding

10

Speed Grade

–2.5F

–2.5

–3

PC2–6400 5–5–5

PC2–6400 6–6–6

PC2–5300 4–4–4

PC2–5300 5–5–5

PC2–4200 4–4–4

PC2–3200 3–3–3

First

–3S

–3.7

–5

11

Die Revision

–A

–B

Second

1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall

module memory density in MBytes as listed in column “Coding”.

TABLE 36

DDR2 DRAM Nomenclature

Field

Description

Values

Coding

1

2

3

4

Qimonda Component Prefix

Interface Voltage [V]

HYB

18

Constant

SSTL_18

DRAM Technology

T

DDR2

Component Density [Mbit]

256

512

1G

2G

40

256 Mbit

512 Mbit

1 Gbit

2 Gbit

5+6

Number of I/Os

×4

80

×8

16

×16

7

8

Product Variations

Die Revision

0 .. 9

A

Look up table

First

B

Second

9

Package, Lead-Free Status

Speed Grade

C

FBGA, lead-containing

FBGA, lead-free

DDR2-800 5-5-5

DDR2-800 6-6-6

DDR2-667 4-4-4

DDR2-667 5-5-5

DDR2-533 4-4-4

DDR2-400 3-3-3

F

10

–25F

–2.5

–3

–3S

–3.7

–5

Rev. 1.41, 2007-05

74

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A

Unbuffered DDR2 SDRAM Modules

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4

5

6

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Rev. 1.41, 2007-05

75

03292006-EZUJ-JY4S

Internet Data Sheet

Edition 2007-05

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics

(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,

including without limitation warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com


型号：	HYS64T32900HU-3.7-A
厂家：	QIMONDA AG
描述：	240-Pin Unbuffered DDR2 SDRAM Modules 240针无缓冲DDR2 SDRAM模组动态存储器双倍数据速率
文件：	总76页 (文件大小：4478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYS64T32900HU-3.7-A [QIMONDA]

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