HYS64T32X00EDL_1 [QIMONDA]
200-Pin SO-DIMM DDR2 SDRAM Modules; 200针SO -DIMM DDR2 SDRAM模组![HYS64T32X00EDL_1](http://pdffile.icpdf.com/pdf1/p00107/img/icpdf/HYS64T128021EDL-25FB2_580596_icpdf.jpg)
型号: | HYS64T32X00EDL_1 |
厂家: | ![]() |
描述: | 200-Pin SO-DIMM DDR2 SDRAM Modules |
文件: | 总79页 (文件大小:4652K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
October 2007
HYS64T32x00EDL–[25F/…/3.7]–B2
HYS64T64x20EDL–[25F/…/3.7]–B2
HYS64T128x21EDL–[25F/…/3.7]B2
200-Pin SO-DIMM DDR2 SDRAM Modules
DDR2 SDRAM
RoHs Compliant Products
Internet Data Sheet
Rev. 1.13
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
HYS64T32x00EDL–[25F/…/3.7]–B2, HYS64T64x20EDL–[25F/…/3.7]–B2, HYS64T128x21EDL–[25F/…/3.7]B2
Revision History: 2007-10, Rev. 1.13
Page
Subjects (major changes since last revision)
5-11
Editorial change and adapted to internet edition
Previous revision 1.11, 2007-09
16, 17, 23 Technical Change, Figure updated
Previous revision 1.11, 2007-08
All
Editorial change
Previous revision 1.1, 2007-01
All
4
Updated HYS64T[32/64/128]9xxEDL–[25F/.../3.7](–)B2
Table 2 corrected product string to 21 digits
Previous revision 1.0, 2006-10
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
08212006-PKYN-2H1B
2
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 200-pin small-outline DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
200-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
128M × 64, 32M × 64, 64M × 64 module organization, and
32M × 16, 64M × 8 chip organization
1GB, 512MB, 256MB Modules built with 512MBit DDR2
SDRAMs in PG-TFBGA-60 and PG-TFBGA-84 chipsize
packages .
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
•
•
•
Serial Presence Detect with E2PROM
SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm
wide
•
•
•
•
Based on standard reference layouts Raw Cards 'A', 'C'
and 'E'
RoHS compliant products1)
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
Unit
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2
PC2
–800D
–6400D
5–5–5
–800E
–6400E
6–6–6
–667C
–5300C
4–4–4
–667D
–5300D
5–5–5
–533C
–4200C
4–4–4
tCK
Max.
Clock Frequency
CL3
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
400
–
200
266
333
400
15
200
333
333
–
200
266
333
–
200
266
266
–
MHz
MHz
MHz
MHz
ns
CL4
CL5
CL6
Min. RAS-CAS-Delay
12.5
12.5
45
12
15
15
Min. Row Precharge Time
Min. Row Active Time1)
Min. Row Cycle Time
15
12
15
15
ns
tRAS
tRC
45
45
45
45
ns
57.5
60
57
60
60
ns
1) Product released after 01-08-2007 will support tRAS = 40 ns for all DDR2 speed sort.
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.13, 2007-10
3
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
module family are small-outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
available as non-ECC modules
in128M × 64 (1GB),
32M × 64 (256MB), 64M × 64 (512MB) in organization and
density, intended for mounting into 200-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-6400-555
HYS64T128921EDL–25FB2
HYS64T64920EDL–25F–B2
HYS64T32900EDL–25F–B2
HYS64T128021EDL–25FB2
HYS64T64020EDL–25F–B2
HYS64T32000EDL–25F–B2
PC2-6400-666
1GB 2R×8 PC2–6400S–555–12–E0
512MB 2R×16 PC2–6400S–555–12–A0
256MB 1R×16 PC2–6400S–555–12–C0
1GB 2R×8 PC2–6400S–555–12–E0
512MB 2R×16 PC2–6400S–555–12–A0
256MB 1R×16 PC2–6400S–555–12–C0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
HYS64T128921EDL–2.5B2
HYS64T64920EDL–2.5–B2
HYS64T32900EDL–2.5–B2
HYS64T128021EDL–2.5B2
HYS64T64020EDL–2.5–B2
HYS64T32000EDL–2.5–B2
PC2-5300-444
1GB 2R×8 PC2–6400S–666–12–E0
512MB 2R×16 PC2–6400S–666–12–A0
256MB 1R×16 PC2–6400S–666–12–C0
1GB 2R×8 PC2–6400S–666–12–E0
512MB 2R×16 PC2–6400S–666–12–A0
256MB 1R×16 PC2–6400S–666–12–C0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
HYS64T128921EDL–3–B2
HYS64T64920EDL–3–B2
HYS64T32900EDL–3–B2
HYS64T128021EDL–3–B2
HYS64T64020EDL–3–B2
HYS64T32000EDL–3–B2
PC2-5300-555
1GB 2R×8 PC2–5300S–444–12–E0
512MB 2R×16 PC2–5300S–444–12–A0
256MB 1R×16 PC2–5300S–444–12–C0
1GB 2R×8 PC2–5300S–444–12–E0
512MB 2R×16 PC2–5300S–444–12–A0
256MB 1R×16 PC2–5300S–444–12–C0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
HYS64T128921EDL–3S–B2
HYS64T64920EDL–3S–B2
HYS64T32900EDL–3S–B2
HYS64T128021EDL–3S–B2
HYS64T64020EDL–3S–B2
HYS64T32000EDL–3S–B2
1GB 2R×8 PC2–5300S–555–12–E0
512MB 2R×16 PC2–5300S–555–12–A0
256MB 1R×16 PC2–5300S–555–12–C0
1GB 2R×8 PC2–5300S–555–12–E0
512MB 2R×16 PC2–5300S–555–12–A0
256MB 1R×16 PC2–5300S–555–12–C0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
Rev. 1.13, 2007-10
4
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-4200-444
HYS64T128921EDL–3.7B2
HYS64T64920EDL–3.7–B2
HYS64T32900EDL–3.7–B2
HYS64T128021EDL–3.7B2
HYS64T64020EDL–3.7–B2
HYS64T32000EDL–3.7–B2
1GB 2R×8 PC2–4200S–444–12–E0
512MB 2R×16 PC2–4200S–444–12–A0
256MB 1R×16 PC2–4200S–444–12–C0
1GB 2R×8 PC2–4200S–444–12–E0
512MB 2R×16 PC2–4200S–444–12–A0
256MB 1R×16 PC2–4200S–444–12–C0
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×16)
1 Rank, Non-ECC
512Mbit (×16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–E0" where 6400S
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card "E".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
1GB
128M × 64
64M × 64
32M × 64
2
2
1
Non-ECC
Non-ECC
Non-ECC
16
8
14/2/10
13/2/10
13/2/10
E
A
C
512MB
256MB
4
TABLE 4
Components on Modules
DRAM Organisation
Product Type1)2)
DRAM Components1)
DRAM Density
HYS64T128921EDL
HYS64T128021EDL
HYS64T64920EDL
HYS64T64020EDL
HYS64T32900EDL
HYB18T512800B2F
HYB18T512800B2F
HYB18T512160B2F
HYB18T512160B2F
HYB18T512160B2F
HYB18T512160B2F
512Mbit
512Mbit
512Mbit
512Mbit
512Mbit
512Mbit
64M × 8
64M × 8
32M × 16
32M × 16
32M × 16
32M × 16
HYS64T32000EDL
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.13, 2007-10
5
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2
Pin Configurations
2.1
Pin Configurations
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations
used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted
in Figure 1
TABLE 5
Pin Configuration of SO-DIMM
Pin No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
30
CK0
CK1
CK0
CK1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signals 1:0, Complement Clock Signals 1:0
The system clock inputs. All address and command lines
are sampled on the cross point of the rising edge of CK and
the falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
164
32
166
79
80
CKE0
CKE1
I
I
SSTL
SSTL
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and
deactivates the CK signal when LOW. By deactivating the
clocks, CKE LOW initiates the Power Down Mode or the
Self Refresh Mode.
Note: 2 Ranks module
Not Connected
NC
NC
—
Note: 1-rank module
Control Signals
110
115
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command decoder
when LOW and disables the command decoder when
HIGH. When the command decoder is disabled, new
commands are ignored but previous operations continue.
Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks
are also called "Physical banks".2 Ranks module
NC
NC
I
—
Not Connected
Note: 1-rank module
108
113
RAS
SSTL
Row Address Strobe
When sampled at the cross point of the rising edge of CK,
and falling edge of CK, RAS, CAS and WE define the
operation to be executed by the SDRAM.
CAS
I
SSTL
Column Address Strobe
Rev. 1.13, 2007-10
6
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
109
WE
I
SSTL
Write Enable
Address Signals
107
106
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or eight
is activated.
85
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
A0
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Less than 1Gb DDR2 SDRAMS
102
101
100
99
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address Bus 12:0
During a Bank Activate command cycle, defines the row
address when sampled at the cross-point of the rising edge
of CK and falling edge of CK. During a Read or Write
command cycle, defines the column address when sampled
at the cross point of the rising edge of CK and falling edge
of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If AP is HIGH, autoprecharge is selected and
BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control
which bank(s) to precharge. If AP is HIGH, all banks will be
precharged regardless of the state of BA0-BAn inputs. If AP
is LOW, then BA0-BAn are used to define which bank to
precharge.
A1
A2
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10
AP
A11
A12
90
89
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Address Signal 13
116
A13
NC
I
SSTL
—
Note: 1 Gbit based module
Not Connected
NC
I
Note: Module based on 512 Mbit or smaller dies
Address Signal 14
86
A14
NC
SSTL
—
Note: 2 Gbit based module
Not Connected
NC
Note: Module based on 1 Gbit or smaller dies
Data Signals
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Note: Data Input / Output pins
7
17
19
4
6
14
16
23
Rev. 1.13, 2007-10
7
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
25
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input / Output pins
35
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
Rev. 1.13, 2007-10
8
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
154
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input / Output pins
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
Data Strobe Signals
13
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 7:0
The data strobes, associated with one data byte, sourced
with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data
window. In Read mode the data strobe is sourced by the
DDR2 SDRAM and is sent at the leading edge of the data
window. DQS signals are complements, and timing is
relative to the cross-point of respective DQS and DQS. If the
module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and
DDR2 SDRAM mode registers programmed appropriately.
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
Data Mask Signals
Rev. 1.13, 2007-10
9
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
10
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 7:0
The data write masks, associated with one data byte. In
Write mode, DM operates as a byte mask by allowing input
data to be written if it is LOW but blocks the write operation
if it is HIGH. In Read mode, DM lines have no effect.
26
52
67
130
147
170
185
EEPROM
197
SCL
SDA
I
CMOS Serial Bus Clock
This signal is used to clock data into and out of the SPD
EEPROM and Thermal sensor.
195
I/O
OD
Serial Bus Data
This is a bidirectional pin use to transfer data into and out of
the SPD EEPROM and Thermal sensor. A resistor must be
connected from SDA to VDDSPD on the motherboard to act as
a pull-up.
198
200
SA0
SA1
I
I
CMOS Serial Address Select Bus 2:0
Address pins used to select the SPD and Thermal sensor
CMOS
base address.
50
EVENT
O
OD
-
EVENT
The optional EVENT pin is reserved for use to flag critical
module temperature and is used in conjunction with
Thermal Sensor.
NC
-
Not Connected
Not connected on modules without temperature sensors.
Power Supplies
1
VREF
AI
—
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
199
VDDSPD PWR
EEPROM Power Supply
Power supplies for Serial Presence Detect, Thermal Sensor
and ground for the module.
81,82,87,88,95,96,103,104,
111,112,117,118
VDD
VSS
PWR
GND
—
—
Power Supply
Power supplies for core, I/O and ground for the module.
2,3,8,9,12,15,18,21,24,27,28,
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,13
9,144,145,149,150,155,156,
161,162,165,168,171,172,177,
178,183,184,187,190,193,196
Ground Plane
Power supplies for core, I/O, Serial Presence Detect,
Thermal Sensor and ground for the module.
Other pins
114
ODT0
I
SSTL
On-Die Termination Control 1:0
Rev. 1.13, 2007-10
10
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
Name
Pin
Buffer
Function
Type Type
119
ODT1
I
SSTL
On-Die Termination Control 1
Asserts on-die termination for DQ, DM, DQS, and DQS
signals if enabled via the DDR2 SDRAM mode register.
Note: 2 Rank modules
Not Connected
NC
NC
NC
NC
—
—
Note: 1 Rank modules
69,83,84,120,163
Not connected
Pins not connected on Qimonda SO-DIMMs
TABLE 6
Abbreviations for pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and
allows multiple devices to share as a wire-OR.
Rev. 1.13, 2007-10
11
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
FIGURE 1
Pin Configuration SO-DIMM (200 pin)
6
2%& ꢇ 0IN ꢀꢀꢁ
0IN ꢀꢀꢃ ꢇ
0IN ꢀꢀꢄ ꢇ
0IN ꢀꢁꢀ ꢇ
0IN ꢀꢁꢂ ꢇ
0IN ꢀꢁꢅ ꢇ
0IN ꢀꢃꢃ ꢇ
0IN ꢀꢃꢄ ꢇ
0IN ꢀꢆꢀ ꢇ
0IN ꢀꢆꢂ ꢇ
0IN ꢀꢆꢅ ꢇ
633
633
ꢇ 0IN ꢀꢀꢆ
0IN ꢀꢀꢂ ꢇ
$1ꢂ
$1ꢀ ꢇ 0IN ꢀꢀꢈ
633 ꢇ 0IN ꢀꢀꢊ
$1ꢈ
$-ꢀ
$1ꢄ
633
$1ꢁ ꢇ 0IN ꢀꢀꢉ
0IN ꢀꢀꢅ ꢇ 633
0IN ꢀꢁꢃ ꢇ 633
0IN ꢀꢁꢄ ꢇ $1ꢉ
0IN ꢀꢃꢀ ꢇ $1ꢁꢃ
0IN ꢀꢃꢂ ꢇ 633
0IN ꢀꢃꢅ ꢇ 633
0IN ꢀꢆꢃ ꢇ #+ꢀ
0IN ꢀꢆꢄ ꢇ $1ꢁꢂ
0IN ꢀꢂꢀ ꢇ 633
$13ꢀ ꢇ 0IN ꢀꢁꢁ
$13ꢀ ꢇ 0IN ꢀꢁꢆ
$1ꢃ ꢇ 0IN ꢀꢁꢉ
633 ꢇ 0IN ꢀꢃꢁ
6
33 ꢇ 0IN ꢀꢁꢈ
$1ꢆ ꢇ 0IN ꢀꢁꢊ
$1ꢅ ꢇ 0IN ꢀꢃꢆ
$1ꢁꢆ
$-ꢁ
#+ꢀ
633
$1ꢊ ꢇ 0IN ꢀꢃꢈ
$13ꢁ ꢇ 0IN ꢀꢃꢊ
633 ꢇ 0IN ꢀꢆꢆ
6
33 ꢇ 0IN ꢀꢃꢉ
$13ꢁ ꢇ 0IN ꢀꢆꢁ
$1ꢁꢀ ꢇ 0IN ꢀꢆꢈ
633 ꢇ 0IN ꢀꢆꢊ
$1ꢁꢁ ꢇ 0IN ꢀꢆꢉ
$1ꢁꢈ
6
33 ꢇ 0IN ꢀꢂꢁ
0IN ꢀꢂꢃ ꢇ 633
0IN ꢀꢂꢄ ꢇ $1ꢃꢁ
0IN ꢀꢈꢀ ꢇ .#ꢋ%6%.4
0IN ꢀꢈꢂ ꢇ 633
0IN ꢀꢈꢅ ꢇ $1ꢃꢆ
0IN ꢀꢄꢃ ꢇ $1ꢃꢅ
0IN ꢀꢄꢄ ꢇ 633
0IN ꢀꢉꢀ ꢇ $13ꢆ
0IN ꢀꢉꢂ ꢇ $1ꢆꢀ
0IN ꢀꢉꢅ ꢇ 633
0IN ꢀꢅꢃ ꢇ 6$$
0IN ꢀꢅꢄ ꢇ .#ꢋ!ꢁꢂ
0IN ꢀꢊꢀ ꢇ !ꢁꢁ
0IN ꢀꢊꢂ ꢇ !ꢄ
&
2
/
.
4
3
)
$1ꢁꢄ ꢇ 0IN ꢀꢂꢆ
0IN ꢀꢂꢂ ꢇ $1ꢃꢀ
0IN ꢀꢂꢅ ꢇ 633
0IN ꢀꢈꢃ ꢇ $-ꢃ
0IN ꢀꢈꢄ ꢇ $1ꢃꢃ
0IN ꢀꢄꢀ ꢇ 633
0IN ꢀꢄꢂ ꢇ $1ꢃꢊ
0IN ꢀꢄꢅ ꢇ $13ꢆ
0IN ꢀꢉꢃ ꢇ 633
0IN ꢀꢉꢄ ꢇ $1ꢆꢁ
0IN ꢀꢅꢀ ꢇ .#ꢋ#+%ꢁ
0IN ꢀꢅꢂ ꢇ .#
$1ꢁꢉ ꢇ 0IN ꢀꢂꢈ
$13ꢃ ꢇ 0IN ꢀꢂꢊ
633 ꢇ 0IN ꢀꢈꢆ
$1ꢁꢊ ꢇ 0IN ꢀꢈꢉ
$1ꢃꢂ ꢇ 0IN ꢀꢄꢁ
633 ꢇ 0IN ꢀꢄꢈ
.# ꢇ 0IN ꢀꢄꢊ
"
!
#
+
3
)
6
33 ꢇ 0IN ꢀꢂꢉ
$13ꢃ ꢇ 0IN ꢀꢈꢁ
$1ꢁꢅ ꢇ 0IN ꢀꢈꢈ
633 ꢇ 0IN ꢀꢈꢊ
$1ꢃꢈ ꢇ 0IN ꢀꢄꢆ
$-ꢆ ꢇ 0IN ꢀꢄꢉ
633 ꢇ 0IN ꢀꢉꢁ
$
%
$
%
$1ꢃꢄ ꢇ 0IN ꢀꢉꢆ
633 ꢇ 0IN ꢀꢉꢉ
6$$ ꢇ 0IN ꢀꢅꢁ
.#ꢋ"!ꢃ ꢇ 0IN ꢀꢅꢈ
!ꢁꢃ ꢇ 0IN ꢀꢅꢊ
!ꢅ ꢇ 0IN ꢀꢊꢆ
$1ꢃꢉ ꢇ 0IN ꢀꢉꢈ
#+%ꢀ ꢇ 0IN ꢀꢉꢊ
.# ꢇ 0IN ꢀꢅꢆ
6$$ ꢇ 0IN ꢀꢅꢉ
0IN ꢀꢅꢅ ꢇ 6$$
0IN ꢀꢊꢃ ꢇ !ꢉ
0IN ꢀꢊꢄ ꢇ 6$$
0IN ꢁꢀꢀ ꢇ !ꢃ
!ꢊ ꢇ 0IN ꢀꢊꢁ
6$$ ꢇ 0IN ꢀꢊꢈ
!ꢈ ꢇ 0IN ꢀꢊꢉ
0IN ꢀꢊꢅ ꢇ !ꢂ
!ꢆ ꢇ 0IN ꢀꢊꢊ
!ꢁ ꢇ 0IN ꢁꢀꢁ
0IN ꢁꢀꢃ ꢇ !ꢀ
6$$ ꢇ 0IN ꢁꢀꢆ
0IN ꢁꢀꢂ ꢇ 6$$
0IN ꢁꢀꢅ ꢇ 2!3
0IN ꢁꢁꢃ ꢇ 6$$
0IN ꢁꢁꢄ ꢇ .#ꢋ!ꢁꢆ
0IN ꢁꢃꢀ ꢇ .#
!ꢁꢀꢋ!0 ꢇ 0IN ꢁꢀꢈ
7% ꢇ 0IN ꢁꢀꢊ
#!3 ꢇ 0IN ꢁꢁꢆ
6$$ ꢇ 0IN ꢁꢁꢉ
633 ꢇ 0IN ꢁꢃꢁ
$1ꢆꢆ ꢇ 0IN ꢁꢃꢈ
$13ꢂ ꢇ 0IN ꢁꢃꢊ
633 ꢇ 0IN ꢁꢆꢆ
$1ꢆꢈ ꢇ 0IN ꢁꢆꢉ
$1ꢂꢀ ꢇ 0IN ꢁꢂꢁ
633 ꢇ 0IN ꢁꢂꢈ
633 ꢇ 0IN ꢁꢂꢊ
$1ꢂꢆ ꢇ 0IN ꢁꢈꢆ
$1ꢂꢅ ꢇ 0IN ꢁꢈꢉ
633 ꢇ 0IN ꢁꢄꢁ
633 ꢇ 0IN ꢁꢄꢈ
0IN ꢁꢀꢄ ꢇ "!ꢁ
0IN ꢁꢁꢀ ꢇ 3ꢀ
"!ꢀ ꢇ 0IN ꢁꢀꢉ
6$$ ꢇ 0IN ꢁꢁꢁ
0IN ꢁꢁꢂ ꢇ /$4ꢀ
0IN ꢁꢁꢅ ꢇ 6$$
0IN ꢁꢃꢃ ꢇ 633
0IN ꢁꢃꢄ ꢇ $1ꢆꢉ
0IN ꢁꢆꢀ ꢇ $-ꢂ
0IN ꢁꢆꢂ ꢇ $1ꢆꢅ
0IN ꢁꢆꢅ ꢇ 633
0IN ꢁꢂꢃ ꢇ $1ꢂꢈ
0IN ꢁꢂꢄ ꢇ $13ꢈ
0IN ꢁꢈꢀ ꢇ 633
0IN ꢁꢈꢂ ꢇ $1ꢂꢉ
0IN ꢁꢈꢅ ꢇ $1ꢈꢃ
0IN ꢁꢄꢃ ꢇ 633
0IN ꢁꢄꢄ ꢇ #+ꢁ
.#ꢋ3ꢁ ꢇ 0IN ꢁꢁꢈ
.#ꢋ/$4ꢁ ꢇ 0IN ꢁꢁꢊ
$1ꢆꢃ ꢇ 0IN ꢁꢃꢆ
633 ꢇ 0IN ꢁꢃꢉ
0IN ꢁꢃꢂ ꢇ $1ꢆꢄ
0IN ꢁꢃꢅ ꢇ 633
0IN ꢁꢆꢃ ꢇ 633
0IN ꢁꢆꢄ ꢇ $1ꢆꢊ
0IN ꢁꢂꢀ ꢇ $1ꢂꢂ
0IN ꢁꢂꢂ ꢇ 633
0IN ꢁꢂꢅ ꢇ $13ꢈ
0IN ꢁꢈꢃ ꢇ $1ꢂꢄ
0IN ꢁꢈꢄ ꢇ 633
0IN ꢁꢄꢀ ꢇ $1ꢈꢆ
0IN ꢁꢄꢂ ꢇ #+ꢁ
0IN ꢁꢄꢅ ꢇ 633
0IN ꢁꢉꢃ ꢇ 633
0IN ꢁꢉꢄ ꢇ $1ꢈꢈ
0IN ꢁꢅꢀ ꢇ $1ꢄꢀ
0IN ꢁꢅꢂ ꢇ 633
0IN ꢁꢅꢅ ꢇ $13ꢉ
0IN ꢁꢊꢃ ꢇ $1ꢄꢃ
0IN ꢁꢊꢄ ꢇ 633
0IN ꢃꢀꢀ ꢇ 3!ꢁ
$13ꢂ ꢇ 0IN ꢁꢆꢁ
$1ꢆꢂ ꢇ 0IN ꢁꢆꢈ
633 ꢇ 0IN ꢁꢆꢊ
$1ꢂꢁ ꢇ 0IN ꢁꢂꢆ
$-ꢈ ꢇ 0IN ꢁꢂꢉ
$1ꢂꢃ ꢇ 0IN ꢁꢈꢁ
633 ꢇ 0IN ꢁꢈꢈ
$1ꢂꢊ ꢇ 0IN ꢁꢈꢊ
.# ꢇ 0IN ꢁꢄꢆ
$13ꢄ ꢇ 0IN ꢁꢄꢉ
633 ꢇ 0IN ꢁꢉꢁ
0IN ꢁꢄꢊ
0IN ꢁꢉꢀ
ꢇ $-ꢄ
$13ꢄ ꢇ
$1ꢈꢀ ꢇ 0IN ꢁꢉꢆ
633 ꢇ 0IN ꢁꢉꢉ
0IN ꢁꢉꢂ ꢇ $1ꢈꢂ
0IN ꢁꢉꢅ ꢇ 633
$1ꢈꢁ ꢇ 0IN ꢁꢉꢈ
$1ꢈꢄ ꢇ 0IN ꢁꢉꢊ
633 ꢇ 0IN ꢁꢅꢆ
$1ꢈꢉ ꢇ 0IN ꢁꢅꢁ
$-ꢉ ꢇ 0IN ꢁꢅꢈ
0IN ꢁꢅꢃ ꢇ $1ꢄꢁ
0IN ꢁꢅꢄ ꢇ $13ꢉ
633 ꢇ 0IN ꢁꢅꢉ
0IN ꢁꢅꢊ
0IN ꢁꢊꢀ
$1ꢈꢅ ꢇ
633 ꢇ 0IN ꢁꢊꢆ
0IN ꢁꢊꢉ
ꢇ 633
0IN ꢁꢊꢂ ꢇ $1ꢄꢆ
0IN ꢁꢊꢅ
$1ꢈꢊ ꢇ 0IN ꢁꢊꢁ
3$! ꢇ 0IN ꢁꢊꢈ
6$$30$ ꢇ 0IN ꢁꢊꢊ
3#, ꢇ
ꢇ 3!ꢀ
-004ꢀꢁꢂꢀ
Rev. 1.13, 2007-10
12
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
–1.0
–0.5
–0.5
–0.5
+2.3
+2.3
+2.3
+2.3
V
V
V
V
1)1)
1)1)
1)
VDDQ
VDDL
VIN, VOUT
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
TABLE 9
Environmental Requirements
Parameter
Symbol
Values
Min.
Unit
Note
Max.
Operating temperature (ambient)
Storage Temperature
TOPR
TSTG
PBar
HOPR
HSTG
0
+65
+100
+105
90
°C
°C
kPa
%
1)
2)
– 50
+69
10
5
Barometric Pressure (operating & storage)
Operating Humidity (relative)
Storage Humidity (without condensation)
95
%
1) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
2) Up to 3000 m.
Rev. 1.13, 2007-10
13
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 10
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TCASE
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
3.2
DC Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
DC Input Logic High
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Rev. 1.13, 2007-10
14
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade
DDR2–800D
–25F
DDR2–800E
–2.5
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
Min.
6–6–6
tCK
Symbol
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)6)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period
@ CL = 3
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
@ CL = 4
@ CL = 5
@ CL = 6
tCK
3.75
2.5
2.5
45
8
3.75
3
8
tCK
8
8
tCK
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRC
tRCD
tRP
70k
—
—
—
70k
—
—
—
57.5
12.5
12.5
Row Precharge Time
TABLE 13
Speed Grade Definition
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
DDR2–533C
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
4–4–4
5–5–5
4–4–4
tCK
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)6)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3
8
3.75
3
8
3.75
3.75
45
8
tCK
3
8
8
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRC
tRCD
tRP
45
57
12
12
70k
—
—
—
45
60
15
15
70k
—
—
—
70k
—
—
—
60
15
Row Precharge Time
15
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) mentioned in Component datasheet.
Rev. 1.13, 2007-10
15
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT
.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
6) Product released after 01-08-2007 will support tRAS = 40 ns for all DDR2 speed sort.
3.3.2
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note2)3)5
)6)7)8)
Min.
Max.
Min.
Max.
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
2
—
2
—
nCK
tCK.AVG
ps
10)11)
12)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
10)11)
13)14)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
tCK .AVG + tIH
––
ns
15)19)20)
DQ and DM input hold time
tDH.BASE
125
––
—
175
––
—
ps
DQ and DM input pulse width for each tDIPW
0.35
0.35
tCK.AVG
input
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
tCK.AVG
tCK.AVG
ps
—
—
16)
17)
DQS-DQ skew for DQS & associated tDQSQ
200
240
DQ signals
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
18)19)20)
17)
DQ and DM input setup time
tDS.BASE
50
––
—
—
__
100
––
—
—
__
ps
DQS falling edge hold time from CK tDSH
0.2
0.2
tCK.AVG
tCK.AVG
ps
17)
DQS falling edge to CK setup time
CK half pulse width
tDSS
tHP
0.2
0.2
21)
Min(tCH.ABS
,
Min(tCH.ABS,
tCL.ABS
)
tCL.ABS)
9)22)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
23)25)
Address and control input hold time tIH.BASE
250
0.6
—
—
275
0.6
—
—
ps
Control & address input pulse width tIPW
tCK.AVG
for each input
24)25)
Address and control input setup time tIS.BASE
175
—
200
—
ps
Rev. 1.13, 2007-10
16
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol DDR2–800
Min.
DDR2–667
Min.
Unit
Note2)3)5
)6)7)8)
Max.
Max.
9)22)
9)22)
DQ low impedance time from CK/CK tLZ.DQ
2 x tAC.MIN
tAC.MAX
2 x tAC.MIN
tAC.MAX
tAC.MAX
ps
ps
DQS/DQS low-impedance time from tLZ.DQS
tAC.MIN
tAC.MAX
tAC.MIN
CK / CK
35)
MRS command to ODT update delay tMOD
0
2
12
—
0
2
12
—
ns
Mode register set command cycle
time
tMRD
nCK
35)
OCD drive mode output delay
tOIT
0
12
0
12
ns
ps
ps
µs
µs
ns
26)
DQ/DQS output hold time from DQS tQH
t
HP – tQHS
—
t
HP – tQHS
—
27)
DQ hold skew factor
tQHS
tREFI
—
300
7.8
3.9
—
—
340
7.8
3.9
—
28)29)
28)30)
31)
Average periodic refresh Interval
—
—
—
—
Auto-Refresh to Active/Auto-Refresh tRFC
105
105
command period
Precharge-All (4 banks) command
period
tRP
tRP
—
tRP
—
ns
32)33)
32)34)
35)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for tRRD
1KB page size products
35)
35)
Active to active command period for tRRD
2KB page size products
10
—
—
10
—
—
ns
ns
Internal Read to Precharge command tRTP
7.5
7.5
delay
Write preamble
tWPRE
tWPST
tWR
0.35
0.4
—
0.6
—
—
—
—
0.35
0.4
—
0.6
—
—
—
—
tCK.AVG
tCK.AVG
ns
Write postamble
Write recovery time
35)
15
15
35)36)
Internal write to read command delay tWTR
Exit power down to read command tXARD
7.5
7.5
ns
2
2
nCK
nCK
Exit active power-down mode to read tXARDS
8 – AL
7 – AL
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
ns
35)
Exit self-refresh to a non-read
command
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
Exit self-refresh to read command
tXSRD
200
200
nCK
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Rev. 1.13, 2007-10
17
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT. component datasheet
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters component datasheet are referred to as 'input clock jitter spec parameters' and these
parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship component datasheet between the
average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
component datasheet).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Rev. 1.13, 2007-10
18
08212006-PKYN-2H1B
5(ꢀꢀEHJLꢀQꢀSRLQWꢀ
7
ꢀ
Hꢀ
ꢀSRLꢀQW
ꢀ
92/
ꢀꢄꢀꢂ[ꢀP9
ꢀꢄꢀ[ꢀP9
ꢀ
977ꢀꢃꢀ[ꢀP
9ꢀ
92/
ꢀ
977ꢀꢃꢀꢂ[ꢀP9ꢀ
7ꢁꢀ 7ꢂꢀ
W+=ꢅW536
7ꢀꢀHQG
ꢀSRLQ
Wꢀꢀ
ꢀꢂꢆ
7ꢁꢃ7ꢂꢀ
W/=ꢅW
535(ꢀEꢀ
Wꢀꢀ
ꢀꢂꢆ7
ꢁꢃ7ꢂꢀ
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
29) 0 °C≤ TCASE ≤ 85 °C.
30) 85 °C < TCASE ≤ 95 °C.
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
32) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
92+
ꢀꢃꢀ[ꢀP9
ꢀ
977ꢀꢄꢀꢂ[ꢀP9ꢀ
977ꢀꢄꢀ[ꢀP9ꢀ
92+
ꢀꢃꢀꢂ[ꢀP9ꢀ
W/=ꢀ
W53
W+=ꢀ
W536 QG
7ꢁꢀ 7ꢂꢀ
HJLQꢀSRLQ
Rev. 1.13, 2007-10
19
08212006-PKYN-2H1B
6
W'+ꢀꢀ
W'6ꢀꢀ
''4ꢀꢀ
9ꢀ,+ꢀ ꢊDF ꢀPL
Q
Q
ꢀꢀ
ꢀꢀ
ꢋꢀꢀ
9ꢀ,+ꢀ ꢊGF ꢀPL
ꢋꢀꢀ
9ꢀꢀ F ꢀPD
[
[
ꢀꢀ
ꢀꢀ
,/ꢊ
G ꢋꢀꢀ
9ꢀꢀ F ꢀPD
,/ꢊ
D ꢋꢀꢀ
W,+ꢀ
W,+
ꢀ
W,6ꢀ
W,6ꢀ
ꢀ
ꢋꢀ
ꢋꢀ
9,ꢀ/ꢊGF ꢀPD[
ꢀ
ꢀ
ꢋꢀ
9,ꢀ/ꢊDF ꢀPD[
ꢋꢀ
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
FIGURE 3
Differential input waveform timing tDS and tDH
'46ꢀꢀ
'4 ꢀꢀ
W'+ꢀꢀ
W'6ꢀꢀ
9ꢀꢀ
9ꢀꢀ
5()ꢊGFꢋꢀꢀ
9ꢀꢀ
66ꢀꢀ
0377ꢂꢇꢈꢉ
FIGURE 4
Differential input waveform timing tlS and tlH
&.ꢀ
&.ꢀ
9'ꢀ '4
9,ꢀ+ꢊDF ꢀPLQꢀ
9,ꢀ+ꢊGF ꢀPLQꢀ
95ꢀ ()ꢊGFꢋꢀ
96ꢀ 6ꢀ
Rev. 1.13, 2007-10
20
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Notes2)3)4)5)6)
7)
Min.
Max.
CAS A to CAS B command period
CK, CK high-level width
tCCD
tCH
2
—
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width tCKE
CK, CK low-level width
tCL
0.45
WR + tRP
0.55
—
8)
Auto-Precharge write recovery +
precharge time
tDAL
9)
Minimum time clocks remain ON after
CKE asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
—
ns
ps
ps
tCK
10)
11)
DQ and DM input hold time (differential tDH.BASE
data strobe)
DQ and DM input hold time (single ended tDH1.BASE
data strobe)
–25
DQ and DM input pulse width (each
input)
tDIPW
0.35
DQS input HIGH pulse width (write cycle) tDQSH
DQS input LOW pulse width (write cycle) tDQSL
0.35
0.35
—
—
tCK
tCK
ps
—
11)
DQS-DQ skew (for DQS & associated
DQ signals)
tDQSQ
300
Write command to 1st DQS latching
transition
tDQSS
– 0.25
100
–25
0.2
+ 0.25
—
tCK
ps
11)
11)
DQ and DM input setup time (differential tDS.BASE
data strobe)
DQ and DM input setup time (single
ended data strobe)
tDS1.BASE
tDSH
—
ps
DQS falling edge hold time from CK
(write cycle)
—
tCK
tCK
DQS falling edge to CK setup time (write tDSS
0.2
—
cycle)
Four Activate Window period
Four Activate Window period
Clock half period
tFAW
tFAW
tHP
37.5
—
—
ns
ns
13)
12)
13)
50
MIN. (tCL, tCH
)
Data-out high-impedance time from CK / tHZ
—
tAC.MAX
ps
CK
11)
Address and control input hold time
tIH.BASE
375
0.6
—
—
ps
Address and control input pulse width
(each input)
tIPW
tCK
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
tIS.BASE
tLZ(DQ)
tLZ(DQS)
tMOD
250
—
ps
ps
ps
ns
2 × tAC.MIN
tAC.MIN
0
tAC.MAX
tAC.MAX
12
Rev. 1.13, 2007-10
21
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Notes2)3)4)5)6)
7)
Max.
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tMRD
tOIT
2
0
—
tCK
12
—
ns
tQH
tHP –tQHS
tQHS
tREFI
tRFC
—
400
7.8
—
ps
µs
ns
14)15)
17)
Average periodic refresh Interval
—
Auto-Refresh to Active/Auto-Refresh
command period
105
Precharge-All (4 banks) command period tRP
Precharge-All (8 banks) command period tRP
tRP
—
ns
ns
tCK
tCK
ns
t
RP + 1 × tCK
—
14)
Read preamble
Read postamble
tRPRE
tRPST
0.9
1.1
0.60
—
14)
0.40
7.5
14)18)
Active bank A to Active bank B command tRRD
period
16)22)
Active bank A to Active bank B command tRRD
period
10
—
—
ns
ns
Internal Read to Precharge command
delay
tRTP
7.5
Write preamble
Write postamble
tWPRE
tWPST
tWR
0.25
0.40
15
—
tCK
tCK
ns
19)
0.60
—
Write recovery time for write without
Auto-Precharge
20)
21)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command tXARD
tCK
(other than NOP or Deselect)
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid tXP
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command tXSNR
t
RFC +10
200
WR/tCK
—
—
ns
Exit Self-Refresh to Read command
tXSRD
tCK
tCK
22)
Write recovery time for write with Auto-
Precharge
WR
t
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT. component datasheet
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
Rev. 1.13, 2007-10
22
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C.
16) 85 °C < TCASE ≤ 95 °C.
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device
18) The tRRD timing parameter depends on the page size of the DRAM organization.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.13, 2007-10
23
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tAC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
tAC.MIN + 2 ns
2.5 tCK +
t
AC.MAX + 1 ns
ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-533
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tAC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
tAC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.13, 2007-10
24
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
TABLE 18
DD Measurement Conditions
I
Parameter
Symbol Note1)2)
3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
6)
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD4R
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
6)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
IDD4W
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Rev. 1.13, 2007-10
25
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol Note1)2)
3)4)5)
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
2)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 19
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output.
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter
LOW
Description
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
Inputs are stable at a HIGH or LOW level
Inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.13, 2007-10
26
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 20
IDDSpecification for HYS64T[32/64/128]xxxEDL–25F–B2
Product Type
Unit
Note1)
Organization
256 MB
1 Rank
×64
512 MB
2 Ranks
×64
1 GB
2 Ranks
×64
–25F
–25F
–25F
Max.
Symbol
Max.
Max.
2)
IDD0
420
480
204
36
456
516
408
72
744
872
816
144
720
960
624
208
1312
1312
1232
176
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
180
240
156
52
360
480
312
104
756
836
616
88
3)
4)3)
5)3)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
720
800
580
44
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
24
40
IDD7
1060
1096
1432
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.13, 2007-10
27
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 21
IDDSpecification for HYS64T[32/64/128]xxxEDL–2.5–B2
Product Type
Unit
Note1)
Organization
256 MB
1 Rank
×64
512 MB
2 Ranks
×64
1 GB
2 Ranks
×64
–2.5
–2.5
–2.5
Symbol
Max.
Max.
Max.
2)
IDD0
400
460
204
36
436
496
408
72
712
832
816
144
720
960
624
208
1312
1312
1232
176
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
180
240
156
52
360
480
312
104
756
836
616
88
3)
4)3)
5)3)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
720
800
580
44
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
24
40
IDD7
1020
1056
1352
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.13, 2007-10
28
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 22
IDDSpecification for HYS64T[32/64/128]xxxEDL–3–B2
Product Type
Unit
Note1)
Organization
256 MB
1 Rank
×64
512 MB
2 Ranks
×64
1 GB
2 Ranks
×64
–3
–3
–3
Symbol
Max.
Max.
Max.
2)
IDD0
380
420
180
36
416
456
360
72
672
792
720
144
640
800
528
208
1112
1112
1192
176
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
160
200
132
52
320
400
264
104
656
716
596
88
3)
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
620
680
560
44
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
24
40
IDD7
1008
1044
1352
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.13, 2007-10
29
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 23
IDDSpecification for HYS64T[32/64/128]xxxEDL–3S–B2
Product Type
Unit
Note1)
Organization
256 MB
1 Rank
×64
512 MB
2 Ranks
×64
1 GB
2 Ranks
×64
–3S
–3S
–3S
Symbol
Max.
Max.
Max.
2)
IDD0
360
400
180
36
396
436
360
72
640
752
720
144
640
800
528
208
1112
1112
1192
176
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
160
200
132
52
320
400
264
104
656
716
596
88
3)
4)3)
5)3)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
620
680
560
44
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
24
40
IDD7
960
996
1288
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.13, 2007-10
30
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 24
IDDSpecification for HYS64T[32/64/128]xxxEDL–3.7–B2
Product Type
Unit
Note1)
Organization
256 MB
1 Rank
×64
512 MB
2 Ranks
×64
1 GB
2 Ranks
×64
–3.7
–3.7
–3.7
Symbol
Max.
Max.
Max.
2)
IDD0
320
360
152
36
356
396
304
72
592
672
608
144
560
688
448
208
952
952
1112
176
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
140
172
112
52
280
344
224
104
556
616
556
88
3)
4)3)
5)3)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
520
580
520
44
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
24
40
IDD7
920
956
1232
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.13, 2007-10
31
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
•
•
•
•
Table 25 “HYS64T[32/64/128]0xxEDL-25F-B2” on Page 32
Table 26 “HYS64T[32/64/128]9xxEDL-25F-B2” on Page 37
Table 27 “HYS64T[32/64/128]0xxEDL-2.5-B2” on Page 41
Table 28 “HYS64T[32/64/128]9xxEDL-2.5-B2” on Page 45
Table 29 “HYS64T[32/64/128]0xxEDL-3-B2” on Page 49
Table 30 “HYS64T[32/64/128]9xxEDL-3-B2” on Page 53
Table 31 “HYS64T[32/64/128]0xxEDL-3S-B2” on Page 57
Table 32 “HYS64T[32/64/128]9xxEDL-3S-B2” on Page 61
Table 33 “HYS64T[32/64/128]0xxEDL-3.7-B2” on Page 65
Table 34 “HYS64T[32/64/128]9xxEDL-3.7-B2” on Page 69
TABLE 25
HYS64T[32/64/128]0xxEDL-25F-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
1
2
3
4
5
6
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
80
08
08
0D
0A
61
40
80
08
08
0E
0A
61
40
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
Rev. 1.13, 2007-10
32
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
7
Not used
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
25
40
3D
50
32
28
32
2D
40
17
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
25
40
3D
50
32
28
32
2D
40
17
00
05
25
40
00
82
08
00
00
0C
04
70
01
04
00
07
25
40
3D
50
32
1E
32
2D
80
17
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
AS.MIN and tCS.MIN [ns]
t
Rev. 1.13, 2007-10
33
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
t
t
t
t
t
t
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
56
7A
7F
3B
36
2E
5A
2A
68
22
3D
00
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
56
7A
7F
3B
36
2E
5A
2A
68
22
3D
00
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
50
7A
5F
3B
36
2E
5A
2A
5A
22
27
00
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Rev. 1.13, 2007-10
34
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Psi(ca) REG
00
00
00
12
54
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
12
55
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
12
3A
7F
7F
7F
7F
7F
51
00
00
xx
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
54
33
32
30
30
30
45
44
4C
32
36
34
54
36
34
30
32
30
45
44
4C
32
36
34
54
31
32
38
30
32
31
45
44
4C
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Rev. 1.13, 2007-10
35
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
85
86
87
88
89
90
91
92
93
94
Product Type, Char 13
35
46
42
32
20
20
3x
xx
xx
xx
xx
00
FF
35
46
42
32
20
20
3x
xx
xx
xx
xx
00
FF
32
35
46
42
32
20
3x
xx
xx
xx
xx
00
FF
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
36
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 26
HYS64T[32/64/128]9xxEDL-25F-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0D
0A
61
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
04
70
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
37
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
25
40
3D
50
32
28
32
2D
40
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
56
7A
25
40
3D
50
32
28
32
2D
40
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
56
7A
25
40
3D
50
32
1E
32
2D
80
17
25
05
12
3C
1E
1E
00
30
39
69
80
14
1E
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
38
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
7F
3B
36
2E
5A
2A
68
22
3D
00
00
00
00
12
54
7F
7F
7F
7F
7F
51
00
00
xx
7F
3B
36
2E
5A
2A
68
22
3D
00
00
00
00
12
55
7F
7F
7F
7F
7F
51
00
00
xx
5F
3B
36
2E
5A
2A
5A
22
27
00
00
00
00
12
3A
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
39
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555 PC2–6400S–555 PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
39
30
30
45
44
4C
32
35
46
42
32
20
20
0x
xx
54
36
34
39
32
30
45
44
4C
32
35
46
42
32
20
20
0x
xx
54
31
32
38
39
32
31
45
44
4C
32
35
46
42
32
20
0x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
40
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 27
HYS64T[32/64/128]0xxEDL-2.5-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0D
0A
61
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
04
70
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
41
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
30
45
3D
50
3C
28
3C
2D
40
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
56
7A
30
45
3D
50
3C
28
3C
2D
40
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
56
7A
30
45
3D
50
3C
1E
3C
2D
80
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
42
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
77
3B
36
2E
5A
2A
68
22
3B
00
00
00
00
12
41
7F
7F
7F
7F
7F
51
00
00
xx
77
3B
36
2E
5A
2A
68
22
3B
00
00
00
00
12
42
7F
7F
7F
7F
7F
51
00
00
xx
5B
3B
36
2E
5A
2A
5A
22
25
00
00
00
00
12
2B
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
43
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
30
30
30
45
44
4C
32
2E
35
42
32
20
20
3x
xx
54
36
34
30
32
30
45
44
4C
32
2E
35
42
32
20
20
3x
xx
54
31
32
38
30
32
31
45
44
4C
32
2E
35
42
32
20
3x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
44
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 28
HYS64T[32/64/128]9xxEDL-2.5-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0D
0A
61
40
00
05
25
40
00
82
10
00
00
0C
04
70
01
04
00
07
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
04
70
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
45
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
30
45
3D
50
3C
28
3C
2D
40
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
56
7A
30
45
3D
50
3C
28
3C
2D
40
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
56
7A
30
45
3D
50
3C
1E
3C
2D
80
17
25
05
12
3C
1E
1E
00
00
3C
69
80
14
1E
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
46
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
77
3B
36
2E
5A
2A
68
22
3B
00
00
00
00
12
41
7F
7F
7F
7F
7F
51
00
00
xx
77
3B
36
2E
5A
2A
68
22
3B
00
00
00
00
12
42
7F
7F
7F
7F
7F
51
00
00
xx
5B
3B
36
2E
5A
2A
5A
22
25
00
00
00
00
12
2B
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
47
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666 PC2–6400S–666 PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
39
30
30
45
44
4C
32
2E
35
42
32
20
20
0x
xx
54
36
34
39
32
30
45
44
4C
32
2E
35
42
32
20
20
0x
xx
54
31
32
38
39
32
31
45
44
4C
32
2E
35
42
32
20
0x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
48
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 29
HYS64T[32/64/128]0xxEDL-3-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
49
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
30
45
50
60
30
28
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
54
7A
30
45
50
60
30
28
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
54
7A
30
45
50
60
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
50
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
6F
34
36
27
4C
2A
5A
20
3A
00
00
00
00
12
0D
7F
7F
7F
7F
7F
51
00
00
xx
6F
34
36
27
4C
2A
5A
20
3A
00
00
00
00
12
0E
7F
7F
7F
7F
7F
51
00
00
xx
53
34
36
27
4C
2A
4C
20
25
00
00
00
00
12
FA
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
51
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
30
30
30
45
44
4C
33
42
32
20
20
20
20
2x
xx
54
36
34
30
32
30
45
44
4C
33
42
32
20
20
20
20
2x
xx
54
31
32
38
30
32
31
45
44
4C
33
42
32
20
20
20
2x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
52
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 30
HYS64T[32/64/128]9xxEDL-3-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
53
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
30
45
50
60
30
28
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
54
7A
30
45
50
60
30
28
30
2D
40
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
54
7A
30
45
50
60
30
1E
30
2D
80
20
27
10
17
3C
1E
1E
00
00
39
69
80
18
22
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
54
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
6F
34
36
27
4C
2A
5A
20
3A
00
00
00
00
12
0D
7F
7F
7F
7F
7F
51
00
00
xx
6F
34
36
27
4C
2A
5A
20
3A
00
00
00
00
12
0E
7F
7F
7F
7F
7F
51
00
00
xx
53
34
36
27
4C
2A
4C
20
25
00
00
00
00
12
FA
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
55
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444 PC2–5300S–444 PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
39
30
30
45
44
4C
33
42
32
20
20
20
20
0x
xx
54
36
34
39
32
30
45
44
4C
33
42
32
20
20
20
20
0x
xx
54
31
32
38
39
32
31
45
44
4C
33
42
32
20
20
20
0x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
56
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 31
HYS64T[32/64/128]0xxEDL-3S-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
57
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
54
7A
3D
50
50
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
54
7A
3D
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
58
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
67
34
36
27
4C
2A
5A
20
38
00
00
00
00
12
36
7F
7F
7F
7F
7F
51
00
00
xx
67
34
36
27
4C
2A
5A
20
38
00
00
00
00
12
37
7F
7F
7F
7F
7F
51
00
00
xx
4B
34
36
27
4C
2A
4C
20
23
00
00
00
00
12
23
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
59
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
30
30
30
45
44
4C
33
53
42
32
20
20
20
2x
xx
54
36
34
30
32
30
45
44
4C
33
53
42
32
20
20
20
2x
xx
54
31
32
38
30
32
31
45
44
4C
33
53
42
32
20
20
2x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
60
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 32
HYS64T[32/64/128]9xxEDL-3S-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
30
45
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
61
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
54
7A
3D
50
50
60
3C
28
3C
2D
40
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
54
7A
3D
50
50
60
3C
1E
3C
2D
80
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
62
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
67
34
36
27
4C
2A
5A
20
38
00
00
00
00
12
36
7F
7F
7F
7F
7F
51
00
00
xx
67
34
36
27
4C
2A
5A
20
38
00
00
00
00
12
37
7F
7F
7F
7F
7F
51
00
00
xx
4B
34
36
27
4C
2A
4C
20
23
00
00
00
00
12
23
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
63
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555 PC2–5300S–555 PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
39
30
30
45
44
4C
33
53
42
32
20
20
20
0x
xx
54
36
34
39
32
30
45
44
4C
33
53
42
32
20
20
20
0x
xx
54
31
32
38
39
32
31
45
44
4C
33
53
42
32
20
20
0x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
64
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 33
HYS64T[32/64/128]0xxEDL-3.7-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
3D
50
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
65
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
7A
3D
50
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
7A
3D
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
66
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
5B
2C
36
21
41
2A
4C
1E
35
00
00
00
00
12
42
7F
7F
7F
7F
7F
51
00
00
xx
5B
2C
36
21
41
2A
4C
1E
35
00
00
00
00
12
43
7F
7F
7F
7F
7F
51
00
00
xx
43
2C
36
21
41
2A
40
1E
22
00
00
00
00
12
37
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
67
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
30
30
30
45
44
4C
33
2E
37
42
32
20
20
2x
xx
54
36
34
30
32
30
45
44
4C
33
2E
37
42
32
20
20
2x
xx
54
31
32
38
30
32
31
45
44
4C
33
2E
37
42
32
20
2x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
68
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 34
HYS64T[32/64/128]9xxEDL-3.7-B2
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0D
0A
60
40
00
05
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0D
0A
61
40
00
05
3D
50
00
82
10
00
00
0C
04
38
01
04
00
07
80
08
08
0E
0A
61
40
00
05
3D
50
00
82
08
00
00
0C
04
38
01
04
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 1.13, 2007-10
69
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
3D
50
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
7A
3D
50
50
60
3C
28
3C
2D
40
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
54
7A
3D
50
50
60
3C
1E
3C
2D
80
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
00
50
7A
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 1.13, 2007-10
70
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
5B
2C
36
21
41
2A
4C
1E
35
00
00
00
00
12
42
7F
7F
7F
7F
7F
51
00
00
xx
5B
2C
36
21
41
2A
4C
1E
35
00
00
00
00
12
43
7F
7F
7F
7F
7F
51
00
00
xx
43
2C
36
21
41
2A
40
1E
22
00
00
00
00
12
37
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 1.13, 2007-10
71
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Product Type
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444 PC2–4200S–444 PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
33
32
39
30
30
45
44
4C
33
2E
37
42
32
20
20
0x
xx
54
36
34
39
32
30
45
44
4C
33
2E
37
42
32
20
20
0x
xx
54
31
32
38
39
32
31
45
44
4C
33
2E
37
42
32
20
0x
xx
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
99 - 127 Not used
xx
xx
xx
00
FF
00
FF
00
FF
128 -
255
Blank for customer use
Rev. 1.13, 2007-10
72
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
5
Package Outlines
FIGURE 5
Package Outline Raw Card C L-DIM-200-30
ꢃꢅꢁꢃ
ꢄꢁꢈ -!8ꢁ
ꢀꢁꢂ
ꢃꢄꢁꢃ
ꢂꢋ
ꢂ
ꢂꢌꢌ
ꢉꢊꢁꢂꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢂꢅꢁꢇꢇ
ꢂ
ꢀꢁꢂ
ꢊꢁꢅ
ꢉꢂꢁꢇꢋ
ꢀꢁꢂ
ꢂꢂꢁꢆ
ꢀꢁꢂ
ꢆꢅꢁꢆ
ꢉꢂꢁꢈꢋ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢂꢇꢋ
ꢊꢀꢀ
ꢊꢁꢆ
ꢀꢁꢂ
ꢂ
$ETAIL OF CONTACTS
ꢊ
ꢊꢋ
ꢀꢁꢀꢄ
ꢀꢁꢆꢇ
ꢀꢁꢂ
ꢀꢁꢃ
ꢊ -).ꢁ
$RAWING ACCORDING TO )3/ ꢈꢀꢂꢇ
'ENERAL TOLERANCES ꢀꢁꢂꢇ
$IMENSIONS IN MM
)32B/Bꢃ',0BBBBꢃꢂꢉꢉꢃꢉꢇꢉ
Notes
1. Thermal Sensor (Optional)
2. SPD or Combidevice (if used then no Thermal Sensor needed)
Rev. 1.13, 2007-10
73
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
FIGURE 6
Package Outline Raw Card A L-DIM-200-31
ꢃꢅꢁꢃ
ꢄꢁꢈ -!8ꢁ
ꢀꢁꢂ
ꢃꢄꢁꢃ
ꢂꢋ
ꢂ
ꢂꢌꢌ
ꢉꢊꢁꢂꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢂꢅꢁꢇꢇ
ꢂ
ꢀꢁꢂ
ꢊꢁꢅ
ꢉꢂꢁꢇꢋ
ꢀꢁꢂ
ꢂꢂꢁꢆ
ꢀꢁꢂ
ꢆꢅꢁꢆ
ꢉꢂꢁꢈꢋ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢂꢇꢋ
ꢊꢀꢀ
ꢊꢁꢆ
ꢀꢁꢂ
ꢂ
$ETAIL OF CONTACTS
ꢊ
ꢊꢋ
ꢀꢁꢀꢄ
ꢀꢁꢆꢇ
ꢀꢁꢂ
ꢀꢁꢃ
ꢊ -).ꢁ
$RAWING ACCORDING TO )3/ ꢈꢀꢂꢇ
'ENERAL TOLERANCES ꢀꢁꢂꢇ
$IMENSIONS IN MM
)32B/Bꢃ',0BBBBꢃꢂꢉꢉꢃꢉꢇꢁ
Notes
1. Thermal Sensor (Optional)
2. SPD or Combidevice (if used then no Thermal Sensor needed)
Rev. 1.13, 2007-10
74
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
FIGURE 7
Package Outline Raw Card E L-DIM-200-36
ꢃꢅꢁꢃ
ꢄꢁꢈ -!8ꢁ
ꢀꢁꢂ
ꢃꢄꢁꢃ
ꢂꢋ
ꢂ
ꢂꢌꢌ
ꢉꢊꢁꢂꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢂꢅꢁꢇꢇ
ꢂ
ꢀꢁꢂ
ꢊꢁꢅ
ꢉꢂꢁꢇꢋ
ꢀꢁꢂ
ꢂꢂꢁꢆ
ꢀꢁꢂ
ꢆꢅꢁꢆ
ꢉꢂꢁꢈꢋ
ꢉꢊꢁꢆꢇꢋ
ꢀꢁꢂ
ꢉꢊꢁꢂꢇꢋ
ꢊꢀꢀ
ꢊꢁꢆ
ꢀꢁꢂ
ꢂ
$ETAIL OF CONTACTS
ꢊ
ꢀꢁꢀꢄ
ꢀꢁꢆꢇ
ꢀꢁꢂ
ꢀꢁꢃ
ꢊꢋ
ꢊ -).ꢁ
)32B/Bꢃ',0BBBBꢃꢂꢉꢉꢃꢉꢇꢌ
$RAWING ACCORDING TO )3/ ꢈꢀꢂꢇ
'ENERAL TOLERANCES ꢀꢁꢂꢄ
$IMENSION IN MM
Notes
1. SPD or Combidevice (if used then no Thermal Sensor needed)
2. Thermal Sensor (Optional)
Rev. 1.13, 2007-10
75
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some proprietary coding. Table 35 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 36 and for components in Table 37.
TABLE 35
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
512/1G 16
TABLE 36
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
Rev. 1.13, 2007-10
76
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–19F
–1.9
–25F
–2.5
–3
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 37
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
F
10
–19F
–1.9
–25F
–2.5
–3
–3S
–3.7
–5
Rev. 1.13, 2007-10
77
08212006-PKYN-2H1B
Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Speed Grade Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Rev. 1.13, 2007-10
78
08212006-PKYN-2H1B
Internet Data Sheet
Edition 2007-10
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
相关型号:
©2020 ICPDF网 联系我们和版权申明