HYS64T32900HU-3.7-B [QIMONDA]

240-Pin unbuffered DDR2 SDRAM Modules; 240针无缓冲DDR2 SDRAM模组


型号：	HYS64T32900HU-3.7-B
厂家：	QIMONDA AG
描述：	240-Pin unbuffered DDR2 SDRAM Modules 240针无缓冲DDR2 SDRAM模组存储内存集成电路动态存储器双倍数据速率时钟
文件：	总87页 (文件大小：5113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

December 2006

HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B

HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B

HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B

240-Pin unbuffered DDR2 SDRAM Modules

DDR2 SDRAM

UDIMM SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.3

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

HYS64T32x00HU–[25F/2.5/3/3S/3.7/5]–B, HYS[64/72]T64x00HU–[25F/2.5/3/3S/3.7/5]–B,

HYS[64/72]T128x20HU–[25F/2.5/3/3S/3.7/5]–B

Revision History: 2006-12, Rev. 1.3

Page

Subjects (major changes since last revision)

All

Adapted internet edition

4, 5

Added WhiteBox Products for Speed Grade –3S and –3.7

Added WhiteBox Products for Speed Grade –3S and –3.7 to IDD tables.

45, 46

70, 74, 78, Updated SPD codes for –3S and –3.7 WhiteBox Products.

Previous Revision: 2006-09, Rev. 1.21

All

Previous Revision: 2006-06, Rev. 1.2

43 SPD codes updated

Previous Revision: 2006-01, Rev. 1.1

Qimonda update

Added PC2-6400-555 product types

Added I_DDcurrents

Added Speed Grade bin for DDR2-800D

Added I_DDMeasurement Contions for DDR2-800D

Added SPD codes for PC2-6400-555 product types

Previous Revision: Rev. 1.0

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-08-07

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Overview

This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main

characteristics.

1.1

Features

Feature list and performance tables

•

240-Pin PC2–6400, PC2–5300, PC2–4200 and

PC2–3200 DDR2 SDRAM memory modules.

32M × 64, 64M × 64, 64M × 72, 128M × 64 and 128M ×72

module organization and 32M × 16, 64M × 8 chip

organization

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply

•

Auto Refresh (CBR) and Self Refresh

Programmable self refresh rate via EMRS2 setting

Programmable partial array refresh via EMRS2 settings

Average Refresh Period 7.8 µs at a T_CASElower than

85 °C, 3.9µs between 85 °C and 95 °C.

DCC enabling via EMRS2 setting

•

All inputs and outputs SSTL_1.8 compatible

Off-Chip Driver Impedance Adjustment (OCD) and

On-Die Termination (ODT)

256MB, 512MB and 1GB modules built with 512-Mbit

DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60

chipsize packages

•

Serial Presence Detect with E²PROM

UDIMM Dimensions (nominal):

•

All speed grades faster than DDR2–400 comply with

DDR2–400 timing specifications.

Programmable CAS Latencies (3, 4 and 5),

Burst Length (8 & 4) and Burst Type

30 mm high, 133.35 mm wide

•

Based on standard reference layouts Raw Card “C”,

“D”,”E”,”F” and “G“

RoHS compliant products¹⁾

TABLE 1

Performance Table

Product Type Speed Code

Speed Grade

–25F

–2.5

–3

–3S

–3.7

–5

Unit

PC2–6400 PC2–6400 PC2–5300 PC2–5300 PC2–4200 PC2–3200

—

5–5–5

6–6–6

4–4–4

5–5–5

4–4–4

3–3–3

Max. Clock Frequency @CL6 f_CK6400

@CL5 f_CK5400

400

333

266

200

—

MHz

333

200

333

266

200

266

200

@CL4 f_CK4266

@CL3 f_CK3200

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

t_RCD12.5

t_RP12.5

t_RAS45

t_RC57.5

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

1.2

Description

The Qimonda HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

module family are unbuffered DIMM modules “UDIMMs” with

30 mm height based on DDR2 technology. DIMMs are

available as non-ECC modules in 32M × 64 (256 MB),

64M × 64 (512 MB), 128M × 64(1 GB) and as ECC modules

in 64M × 72 (512 MB), 128M × 72(1 GB) organization and

density, intended for mounting into 240-pin connector

sockets.

The memory array is designed with 512-Mbit Double-Data-

Rate-Two (DDR2) Synchronous DRAMs. Decoupling

capacitors are mounted on the PCB board. The DIMMs

feature serial presence detect based on a serial E²PROM

device using the 2-pin I²C protocol. The first 128 bytes are

programmed with configuration data and are write protected;

the second 128 bytes are available to the customer.

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

PC2–6400

HYS64T32000HU–25F–B

HYS64T64000HU–25F–B

HYS72T64000HU–25F–B

HYS64T128020HU–25F–B

HYS72T128020HU–25F–B

PC2–6400

256 MB 1R×16 PC2–6400U–555–12–C1

512 MB 1R×8 PC2–6400U–555–12–D0

512 MB 1R×8 PC2–6400E–555–12–F0

1 GB 2R×8 PC2–6400U–555–12–E0

1 GB 2R×8 PC2–6400E–555–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–2.5–B

HYS64T64000HU–2.5–B

HYS72T64000HU–2.5–B

HYS64T128020HU–2.5–B

HYS72T128020HU–2.5–B

PC2–5300

256 MB 1R×16 PC2–6400U–666–12–C1

512 MB 1R×8 PC2–6400U–666–12–D0

512 MB 1R×8 PC2–6400E–666–12–F0

1 GB 2R×8 PC2–6400U–666–12–E0

1 GB 2R×8 PC2–6400E–666–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–3–B

HYS64T64000HU–3–B

HYS72T64000HU–3–B

HYS64T128020HU–3–B

HYS72T128020HU–3–B

PC2–5300

256 MB 1R×16 PC2–5300U–444–12–C1

512 MB 1R×8 PC2–5300U–444–12–D0

512 MB 1R×8 PC2–5300E–444–12–F0

1 GB 2R×8 PC2–5300U–444–12–E0

1 GB 2R×8 PC2–5300E–444–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–3S–B

HYS64T32900HU–3S–B

HYS64T64000HU–3S–B

HYS64T64900HU–3S–B

HYS72T64000HU–3S–B

HYS64T128020HU–3S–B

HYS64T128920HU–3S–B

HYS72T128020HU–3S–B

256 MB 1R×16 PC2–5300U–555–12–C1

512 MB 1R×8 PC2–5300U–555–12–D0

512 MB 1R×8 PC2–5300E–555–12–F0

1 GB 2R×8 PC2–5300U–555–12–E0

1 GB 2R×8 PC2–5300E–555–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

PC2–4200

HYS64T32000HU–3.7–B

HYS64T32900HU–3.7–B

HYS64T64000HU–3.7–B

HYS64T64900HU–3.7–B

HYS72T64000HU–3.7–B

HYS64T128020HU–3.7–B

HYS64T128920HU–3.7–B

HYS72T128020HU–3.7–B

PC2–3200

256 MB 1R×16 PC2–4200U–444–12–C1

512 MB 1R×8 PC2–4200U–444–12–D0

512 MB 1R×8 PC2–4200E–444–12–F0

1 GB 2R×8 PC2–4200U–444–12–E0

1 GB 2R×8 PC2–4200E–444–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

HYS64T32000HU–5–B

HYS64T64000HU–5–B

HYS72T64000HU–5–B

HYS64T128020HU–5–B

HYS72T128020HU–5–B

256 MB 1R×16 PC2–3200U–333–12–C1

512 MB 1R×8 PC2–3200U–333–12–D0

512 MB 1R×8 PC2–3200E–333–12–F0

1 GB 2R×8 PC2–3200U–333–12–E0

1 GB 2R×8 PC2–3200E–333–12–G0

1 Rank, Non-ECC

1 Rank, ECC

512 Mbit (×16)

512 Mbit (×8)

2 Ranks, Non-ECC

2 Ranks, ECC

1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3.7–B, indicating Rev.

“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data

sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–C1”, where

4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)

latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and

produced on the Raw Card “C”.

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

TABLE 3

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of SDRAMs # of row/bank/column

bits

Raw

Card

256 MByte

512 MByte

1 GByte

32M × 64

64M × 64

72M × 64

128M × 64

128M × 72

Non-ECC

ECC

13/2/10

14/2/10

Non-ECC

ECC

1 GByte

TABLE 4

Components on Modules

DRAM Organisation Note²⁾

32M × 16

Product Type¹⁾

DRAM Components¹⁾

DRAM Density

HYS64T32000HU

HYS64T32900HU

HYB18T512160BF

512 Mbit

HYS64T64000HU

HYS64T64900HU

HYB18T512800BF

512 Mbit

64M × 8

HYS72T64000HU

HYB18T512800BF

512 Mbit

64M × 8

HYS64T128020HU

HYS64T128920HU

HYS72T128020HU

1) Green Product

HYB18T512800BF

512 Mbit

64M × 8

2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Pin Configuration

This chapter describes the Pin Configuration.

2.1

Pin Configuration

This chapter contains the Pin Configuration tables.

and Table 7 respectively. The pin numbering is depicted in

Figure 1 for non-ECC modules (×64) and Figure 2 for ECC

modules (×72).

The pin configuration of the Unbuffered DDR2 SDRAM DIMM

is listed by function in Table 5 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 6

TABLE 5

Pin Configuration of UDIMM

Ball No.

Name Pin

Buffer Function

Type Type

Clock Signals

185

137

220

186

138

221

CK0

CK1

CK2

CK0

CK1

CK2

CKE0

CKE1

SSTL

—

Clock Signals 2:0, Complement Clock Signals 2:0

Clock Enable Rank 1:0

Note: 2 Ranks module

171

Not Connected

Note: 1 Rank module

Control Signals

193

S0#

S1#

SSTL

—

Chip Select Rank 1:0

Note: 2 Ranks module

Not Connected

Note: 1 Rank module

Row Address Strobe

Column Address Strobe

Write Enable

192

RAS

CAS

SSTL

Address Signals

BA0

BA1

BA2

SSTL

Bank Address Bus 1:0

190

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

—

Not Connected

Less than 1Gb DDR2 SDRAMS

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Ball No.

Name Pin

Buffer Function

Type Type

188

183

SSTL

Address Bus 12:0

182

180

179

177

A10

A11

A12

A13

176

196

Address Signal 13

Note: 1 Gbit based module and 512M ×4/×8

Not Connected

—

Note: Module based on 1 Gbit ×16

Module based on 512 Mbit ×16 or smaller

174

A14

SSTL

—

Address Signal 14

Note: Modules based on 2 Gbit

Not Connected

Note: Modules based on 1 Gbit or smaller

Data Signals

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

122

123

128

129

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Ball No.

Name Pin

Buffer Function

Type Type

DQ8

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

131

132

140

141

143

144

149

150

152

153

158

159

199

200

205

206

208

209

214

215

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Ball No.

Name Pin

Buffer Function

Type Type

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bit Signals

CB0

I/O

SSTL

—

Check Bit 0

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 1

CB1

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 2

CB2

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 3

CB3

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 4

161

162

CB4

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Check Bit 5

CB5

SSTL

—

Note: ECC type module only

Not Connected

Note: ECC type module only

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Ball No.

Name Pin

Buffer Function

Type Type

167

CB6

I/O SSTL

Check Bit 6

Note: ECC type module only

Not Connected

—

Note: ECC type module only

Check Bit 7

168

CB7

I/O

SSTL

—

Note: ECC type module only

Not Connected

Note: Non-ECC module

Data Strobe Bus

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

DQS0 I/O

DQS1 I/O

DQS2 I/O

DQS3 I/O

DQS4 I/O

DQS5 I/O

DQS6 I/O

DQS7 I/O

DQS8 I/O

SSTL

Data Strobe Bus 8:0

105

114

Complement Data Strobe Bus 8:0

104

113

Data Mask Signals

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

SSTL

Data Mask Bus 8:0

134

146

155

202

211

223

232

164

EEPROM

120

SCL

SDA

CMOS Serial Bus Clock

119

I/O

Serial Bus Data

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Ball No.

Name Pin

Buffer Function

Type Type

239

SA0

SA1

SA2

CMOS Serial Address Select Bus 2:0

240

CMOS

101

Power Supplies

V_REF

—

I/O Reference Voltage

EEPROM Power Supply

I/O Driver Power Supply

238

V_DDSPDPWR

51,56,62,72,75,,

78,170,175,181,,

191,194

V_DDQ

V_DD

V_SS

PWR

GND

53,59,64,67,69,,

172,178,184,187,

189,197

—

Power Supply

Ground Plane

2,5,8,11,14,17,,

20,23,26,29,32,

35,38,41,44,47,,

50,65,66,79,82,

85,88,91,94,97,,

100,103,106,

109,112,115,118,

121,124,127,,

130,133,136,139,

142,145,148,,

151,154,157,160,

163,166,169,

198,201,204,207,

210,213,216,,

219,222,225,228,

231,234,237

Other Pins

195

ODT0

ODT1

SSTL

On-Die Termination Control 0

On-Die Termination Control 1

Note: 2 Rank modules

—

Not Connected

Note: 1 Rank modules

18,19,55,68,102,1 NC

26,135,147,

Not connected

Note: Pins not connected on Qimonda UDIMMs

156,165,173,203,

212, 224,233

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

TABLE 6

Abbreviations for Pin Type

Abbreviation

Description

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

PWR

GND

Ground

Not Connected

TABLE 7

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

LV-CMOS

CMOS

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tri-state,

and allows multiple devices to share as a wire-OR.

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

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FIGURE 1

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Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

FIGURE 2

Pin Configuration UDIMM ×72 (240 Pin)

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Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Electrical Characteristics

This chapter describes the Electrical Characteristics.

3.1

Absolute Maximum Ratings

Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.

TABLE 8

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Note

Max.

V_DD

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0

–0.5

–55

+2.3

+100

1)2)

V_DDQ

V_DDL

V_IN, V_OUT

T_STG

1)2)

°C

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 9

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Note

Min.

Max.

1)2)3)4)

T_OPER

Operating Temperature

°C

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 95 °C under all other specification parameters.

3) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

3.2

DC Operating Conditions

This chapter contains the DC Operating Conditions tables.

TABLE 10

Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Max.

Operating temperature (ambient)

DRAM Case Temperature

T_OPR

T_CASE

T_STG

PBar

H_OPR

+65

+95

+100

+105

°C

kPa

1)2)3)4)

Storage Temperature

– 50

+69

Barometric Pressure (operating & storage)

Operating Humidity (relative)

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported

3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%.

5) Up to 3000 m.

TABLE 11

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Typ.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

1.9

V_DDQ

V_REF

1.7

1.8

1.9

0.49 × V_DDQ

0.5 × V_DDQ

0.51 × V_DDQ

V_DDSPD

V_IH(DC)

V_{IL (DC}

I_L

1.7

—

3.6

DC Input Logic High

V_REF+ 0.125

_DDQ+ 0.3

DC Input Logic Low

)

– 0.30

– 5

_REF– 0.125

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

3.3

Timing Characteristics

This chapter describes the AC Characteristics.

3.3.1

Speed Grade Definitions

All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(t_CK= 5ns with t_RAS= 40ns).

Speed Grade Definition for: DDR2–800(Table 12), DDR2–667(Table 13), DDR2–533C(Table 14) and DDR2–400B(Table 15)

TABLE 12

Speed Grade Definition Speed Bins for DDR2–800

Speed Grade

DDR2–800D

DDR2–800E

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–25F

–2.5

5–5–5

6–6–6

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

@ CL = 6

t_CK

3.75

2.5

3.75

t_CK

2.5

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

70000

—

57.5

12.5

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

TABLE 13

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667C

DDR2–667D

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3

–3S

4–4–4

5–5–5

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

3.75

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Speed Grade

DDR2–667C

–3

DDR2–667D

–3S

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

5–5–5

t_CK

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)5)

1)2)3)4)

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

TABLE 14

Speed Grade Definition Speed Bins for DDR2–533C

Speed Grade

DDR2–533C

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3.7

4–4–4

t_CK

Parameter

Symbol

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

3.75

t_CK

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

TABLE 15

Speed Grade Definition Speed Bins for DDR2-400B

Speed Grade

DDR2–400B

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–5

3–3–3

t_CK

—

Parameter

Symbol

Min.

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

3.3.2

Component AC Timing Parameters

Timing Parameters for: DDR2–800(Table 16), DDR2–667(Table 17), DDR2–533C(Table 18) and DDR2–400B(Table 19)

TABLE 16

DRAM Component Timing Parameter by Speed Grade - DDR2–800

Parameter

Symbol

DDR2–800

Unit

Note

1)2)3)4)5)6)7)8)

Min.

Max.

DQ output access time from CK / CK

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_AC

–400

+400

—

t_CCD

nCK

t_CK.AVG

10)11)

12)

t_CH.AVG

t_CK.AVG

0.48

2500

0.52

8000

—

CKE minimum pulse width ( high and low pulse t_CKE

nCK

width)

10)11)

13)14)

Average clock low pulse width

t_CL.AVG

0.48

0.52

—

t_CK.AVG

nCK

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_{CK .AVG}

t_IH

––

19)20)15)

DQ and DM input hold time

t_DH.BASE

125

––

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Parameter

Symbol

DDR2–800

Min.

Unit

Note

1)2)3)4)5)6)7)8)

Max.

DQ and DM input pulse width for each input

DQS output access time from CK / CK

DQS input high pulse width

t_DIPW

0.35

–350

0.35

—

t_CK.AVG

t_DQSCK

t_DQSH

t_DQSL

+350

—

t_CK.AVG

DQS input low pulse width

—

16)

17)

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

200

+ 0.25

DQS latching rising transition to associated clock t_DQSS

– 0.25

t_CK.AVG

edges

18)19)20)

17)

DQ and DM input setup time

DQS falling edge hold time from CK

DQS falling edge to CK setup time

CK half pulse width

t_DS.BASE

––

—

t_DSH

t_DSS

t_HP

0.2

t_CK.AVG

17)

21)

Min(t_CH.ABS

t_CL.ABS

)

9)22)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

—

23)25)

t_IH.BASE

250

0.6

Control & address input pulse width for each input t_IPW

—

t_CK.AVG

24)25)

9)22)

31)

Address and control input setup time

DQ low impedance time from CK/CK

DQS/DQS low-impedance time from CK / CK

MRS command to ODT update delay

Mode register set command cycle time

OCD drive mode output delay

DQ/DQS output hold time from DQS

DQ hold skew factor

t_IS.BASE

175

—

t_LZ.DQ

t_LZ.DQS

t_MOD

t_MRD

t_OIT

2 x t_AC.MIN

t_AC.MAX

t_AC.MIN

—

nCK

31)

26)

t_QH

_HP– t_QHS

—

27)

t_QHS

—

300

1.1

0.6

—

28)29)

28)30)

31)

Read preamble

t_RPRE

t_RPST

t_RTP

0.9

0.4

7.5

0.35

0.4

t_CK.AVG

Read postamble

Internal Read to Precharge command delay

Write preamble

t_WPRE

t_WPST

t_WR

—

t_CK.AVG

Write postamble

0.6

—

31)

Write recovery time

31)32)

Internal write to read command delay

Exit power down to read command

t_WTR

t_XARD

7.5

—

nCK

Exit active power-down mode to read command t_XARDS

8 – AL

—

(slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XP

—

nCK

31)

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_XSNR

t_XSRD

_RFC+10

—

200

nCK

Write command to DQS associated clock edges WL

RL – 1

1) For details and notes see the relevant Qimonda component data sheet

_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V. See notes ^5)6)7)8)

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

t_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to

DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.

11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and

the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).

12) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

13) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

14) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

15) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

V_IH.DC.MIN. See Figure 4.

16) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

18) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 4.

19) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

21) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

22) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

23) Input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 5.

24) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 5.

25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

26) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under the

max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

27) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

28) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

31) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

t_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

32) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

TABLE 17

DRAM Component Timing Parameter by Speed Grade - DDR2–667

Parameter

Symbol

DDR2–667

Unit

Note

1)2)3)4)5)6)7)8)

Min.

Max.

DQ output access time from CK / CK

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_AC

–450

+450

—

t_CCD

nCK

t_CK.AVG

10)11)

12)

t_CH.AVG

t_CK.AVG

0.48

3000

0.52

8000

—

CKE minimum pulse width ( high and low pulse t_CKE

nCK

width)

10)11)

13)14)

Average clock low pulse width

t_CL.AVG

0.48

0.52

—

t_CK.AVG

nCK

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_{CK .AVG}

t_IH

—

19)20)15)

DQ and DM input hold time

t_DH.BASE

t_DIPW

t_DQSCK

t_DQSH

175

—

DQ and DM input pulse width for each input

DQS output access time from CK / CK

DQS input high pulse width

0.35

–400

0.35

—

t_CK.AVG

+400

—

t_CK.AVG

DQS input low pulse width

t_DQSL

—

16)

17)

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

240

+ 0.25

DQS latching rising transition to associated clock t_DQSS

– 0.25

t_CK.AVG

edges

Rev. 1.3, 2006-12

03292006-6GMD-RSFT

Internet Data Sheet

HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B

Unbuffered DDR2 SDRAM Module

Parameter

Symbol

DDR2–667

Min.

Unit

Note

1)2)3)4)5)6)7)8)

Max.

18)19)20)

17)

DQ and DM input setup time

DQS falling edge hold time from CK

DQS falling edge to CK setup time

CK half pulse width

t_DS.BASE

t_DSH

100

0.2

—

t_CK.AVG

17)

t_DSS

21)

t_HP

Min(t_CH.ABS,

t_CL.ABS

)

9)22)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

—

25)23)

t_IH.BASE

275

0.6

Control & address input pulse width for each input t_IPW

—

t_CK.AVG

24)25)

9)22)

31)

Address and control input setup time

DQ low impedance time from CK/CK

DQS/DQS low-impedance time from CK / CK

MRS command to ODT update delay

Mode register set command cycle time

OCD drive mode output delay

DQ/DQS output hold time from DQS

DQ hold skew factor

t_IS.BASE

200

—

t_LZ.DQ

t_LZ.DQS

t_MOD

t_MRD

t_OIT

2 x t_AC.MIN

t_AC.MAX

t_AC.MIN

—

nCK

31)

26)

t_QH

_HP– t_QHS

—

27)

t_QHS

—

340

1.1

0.6

—

28)29)

28)30)

31)

Read preamble

t_RPRE

t_RPST

t_RTP

0.9

0.4

7.5

0.35

0.4

t_CK.AVG

Read postamble

Internal Read to Precharge command delay

Write preamble

t_WPRE

t_WPST

t_WR

—

t_CK.AVG

Write postamble

0.6

—

31)

Write recovery time

31)32)

Internal write to read command delay

Exit power down to read command

t_WTR

t_XARD

7.5

—

nCK

Exit active power-down mode to read command t_XARDS

7 – AL

—

(slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XP

—

nCK

31)

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_XSNR

t_XSRD

_RFC+10

—

200

nCK

Write command to DQS associated clock edges WL

RL–1