PLL602-30 [PLL]
750kHz - 800MHz Low Phase Noise XO (for 12 - 25MHz Crystals); 750kHz的 - 800MHz的低相位噪声XO （ 12 - 25MHz的晶体）
| 型号： | PLL602-30 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | 750kHz - 800MHz Low Phase Noise XO (for 12 - 25MHz Crystals) |
| 文件： | 总8页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
DIE CONFIGURATION
65 mil
•
•
750kHz to 800MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -123dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
115dBc/Hz for 622.08MHz).
Selectable CMOS, PECL and LVDS output.
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
(1550,1475)
17
25
24 23 22 21
20
19
18
GNDBUF
26
16
15
14
XIN
CMOS
LVDSB
PECLB
Die ID:
A1414-14E
•
•
27
28
XOUT
SEL3
13
12
VDDBUF
VDDBUF
•
•
•
•
12MHz to 25MHz crystal input.
Output Enable selector.
3.3V operation.
Available in DIE (65 mil x 62 mil).
29
SEL2
11
PECL
30
31
OE_CTRL
N/C
C502A
10
9
LVDS
OE_SEL^
1
2
3
4
5
6
7
8
DESCRIPTION
(0,0)
Y
The PLL602-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) XO IC
Die, with selectable CMOS, LVDS or PECL output,
covering the 750kHz to 800MHz output range, using
a low frequency crystal.
This makes the PLL602-30 ideal as a universal die
for applications ranging from low frequency to
SONET.
X
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
Selected Output
0
0
1
1
0
1
0
1
High Drive CMOS
Standard CMOS
PECL
DIE SPECIFICATIONS
LVDS
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
Name
Value
0 (Default) Output enabled
Size
62 x 65 mil
GND
0
1
0
Tri-state
Tri-state
Reverse side
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
1 (Default)
1 (Default) Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “0”
BLOCK DIAGRAM
Logical states defined by CMOS levels if OE_SELECT is “1”
VCO
Divider
Charge
Pump
CLKBAR
VCO
Phase
Reference
Divider
SEL
+
Detector
CLK
Loop
Filter
OE
XIN
XOUT
XTAL
OSC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
SEL2
(Pad #29)
SEL1
(Pad #19)
SEL0
(Pad #20)
Selected Multiplier
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Fin x 32
Reserved
Reserved
Fin / 8
Fin x 2
Reserved
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
FXIN
CONDITIONS
MIN.
TYP.
MAX.
UNITS
MHz
pF
Parallel Fundamental Mode
12
25
CL (xtal)
RE
20
AT cut
30
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
3. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
Fout<24MHz
MIN.
TYP.
MAX.
UNITS
25/25/15
65/45/30
100/80/40
3.63
Supply Current,
Dynamic (with
IDD
PECL/LVDS/CMOS
mA
24MHz<Fout<96MHz
96MHz<Fout<700MHz
Loaded Outputs)
2.97
Operating Voltage
VDD
V
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock
Duty Cycle
%
Short Circuit
Current
mA
±50
4. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
MIN.
TYP.
MAX.
UNITS
19.44MHz
77.76MHz
106.25MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
106.25MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
2.1
3.5
4.1
4.3
6.0
17
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter RMS1
ps
30
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter Peak-to-
Peak1
ps
ps
28
27
40
2.6
2.5
4
4
Integrated jitter RMS2
Integrated 12 kHz to 20 MHz
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
19.44MHz
106.25MHz
155.52MHz
622.08MHz
-80
-70
-60
-50
-108
-98
-90
-77
-132
-122
-115
-102
-142
-123
-125
-115
-142
-117
-119
-108
Phase Noise2 relative
to carrier
(typical)
dBc/Hz
1) Jitter analyzer: Wavecrest SIA-3000
2) Phase Noise System: Agilent E5500
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
6. CMOS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
MIN.
30
TYP.
MAX.
UNITS
mA
IOH
IOL
IOH
IOL
Output drive current
(High Drive)
30
mA
10
mA
Output drive current
(Standard Drive)
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.2
0.2
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 6
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
PAD ASSIGNMENT
Pad #
Name
Description
X (µm)
Y (µm)
1
2
3
4
5
6
7
8
GND
GND
248
361
109
109
109
109
109
109
109
109
Ground.
Ground.
GND
473
Ground.
GND
587
Ground.
GND
702
Ground.
N/C
874
No Connection.
Ground.
GND
1042
1171
GNDBUF
Ground, buffer circuitry.
Used to select between PECL or CMOS logic states for OE.
Internal pull up.
9
OE_SELECT
1400
125
10
11
12
13
14
15
16
17
LVDS
PECL
1400
1400
1400
1400
1400
1400
1400
1389
259
476
LVDS Output.
PECL Output.
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
616
3.3V power supply, Buffer circuitry.
3.3V power supply, Buffer circuitry.
Complementary PECL Output.
Complementary LVDS Output.
CMOS Output.
716
871
1089
1227
1365
GNDBUF
Ground, buffer circuitry.
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
18
OUTSEL1
1232
1365
19
20
21
22
23
24
SEL1
SEL0
VDD
VDD
VDD
VDD
1042
854
659
559
459
358
1365
1365
1365
1365
1365
1365
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
3.3V power supply.
3.3V power supply.
3.3V power supply.
3.3V power supply.
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
25
OUTSEL0
194
1365
26
27
28
29
XIN
109
109
109
109
1223
1017
858
Crystal input. See crystal specification page 3.
Crystal output. See crystal specification page 3.
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
XOUT
SEL3
SEL2
646
Used to enable/disable the output(s). See Output Selection and
Enable table on page 1.
30
31
OE_CTRL
NC
109
109
397
181
No Connect
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 7
PLL602-30
750kHz – 800MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-30 D C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
D=DIE
Order Number
PLL602-30DC
Marking
Package Option
Die – Waffle Pack
PLL602-30DC
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 8
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