PLL602-35 [PLL]
750kHz -800MHz Low Phase Noise Multiplier XO; 750kHz的-800MHz低相位噪声乘数XO
| 型号： | PLL602-35 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | 750kHz -800MHz Low Phase Noise Multiplier XO |
| 文件： | 总8页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FEATURES
PIN CONFIGURATION
(Top View)
•
•
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz, -
110dBc/Hz for 622.08MHz).
CMOS (PLL602-37), PECL (PLL602-35 and
PLL602-38) or LVDS (PLL602-39) output.
12 to 25MHz crystal input.
No external load capacitor required.
Output Enable selector.
Selectable 1/16 to 32x frequency multiplier.
3.3V operation.
VDD
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
XOUT
SEL3^
SEL2^
OE
•
CLKC
VDD
•
•
•
•
•
•
CLKT
GND
GND
GND
GND
Available in 16-Pin (TSSOP or 3x3mm QFN).
DESCRIPTION
The PLL602-35 (PECL with inverted OE), PLL602-37
(CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS)
are high performance and low phase noise XO IC
chips. They provide phase noise performance as low
as –125dBc at 1kHz offset (at 155MHz) and a typical
RMS jitter of 4pS RMS ( at 155MHz ). They accept
fundamental parallel resonant mode crystals from 12
to 25MHz.
12
11
10
9
13
8
7
6
5
XOUT
GND
14 PLL602-3X
CLKC
VDD
SEL3^
SEL2^
15
16
CLKT
OE
1
2
3
4
BLOCK DIAGRAM
SEL
^: Internal pull-up
*: On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
OE
PLL
Q
(Phase
Locked
Q
Oscillator
Amplifier
Loop)
XIN
OUTPUT ENABLE LOGICAL LEVELS
XOUT
Part #
OE
State
PLL by-pass
0 (Default) Output enabled
PLL602-3x
PLL602-38
1
0
Tri-state
Tri-state
PLL602-35
PLL602-37
PLL602-39
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL602-38
Logical states defined by CMOS levels for
PLL602-35/-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
0
1
0
1
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package
PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39)
TSSOP
Pin number
3x3mm QFN
Pin number
Name
Type
Description
XIN
XOUT
OE
2
12
I
I
Crystal input. See Crystal Specifications on page 3.
Crystal output. See Crystal Specifications on page 3.
Output enable pin (see OE logic state table on page 1).
Ground.
3
13
6
16
I
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
7,8,9,10,14
1,2,3,4,8,11
P
O
O
I
11
13
16
15
5
5
True output PECL
7
Complementary output PECL.
Not available
9
15
I
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
I
4
14
I
1, 12
6,10
P
Power Supply.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS PLL602-37/-39 (see previous page of PLL602-35/-38)
TSSOP
Pin number
3x3mm QFN
Pin number
Name
Type
Description
XIN
XOUT
OE
2
12
13
I
I
Crystal input. See Crystal Specifications on page 3.
Crystal output. See Crystal Specifications on page 3.
Output enable pin (see OE logic state table on page 1).
Ground.
3
6
16
I
GND
7,8,9,10,14
1,2,3,4,8
P
True output LVDS (PLL602-39)
(N/C for PLL602-37)
Complementary output LVDS (PLL602-39)
(CMOS out for PLL602-37).
CLKT
CLKC
11
13
5
7
O
O
SEL0
SEL1
SEL2
SEL3
VDD
16
15
10
9
I
I
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
5
15
I
4
14
I
1, 12
6,11
P
Power Supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
FXIN
CL (xtal)
RE
Parallel Fundamental Mode
12
25
MHz
pF
20
AT cut
30
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
3. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
Fout<24MHz
MIN.
TYP.
MAX.
UNITS
25/25/15
65/45/30
100/80/40
3.63
Supply Current,
Dynamic (with
IDD
PECL/LVDS/CMOS
mA
24MHz<Fout<96MHz
96MHz<Fout<800MHz
Loaded Outputs)
2.97
Operating Voltage
VDD
V
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock
Duty Cycle
%
Short Circuit
Current
mA
±50
4. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
MIN.
TYP.
MAX.
UNITS
19.44MHz
2.2
3.5
4.3
5.0
17
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
77.76MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
Period jitter RMS1
ps
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
25
Period jitter Peak-to-
Peak1
ps
ps
27
35
2.6
2.5
4
4
Integrated jitter RMS2
Integrated 12 kHz to 20 MHz
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
19.44MHz
77.76MHz
155.52MHz
622.08MHz
-80
-72
-65
-55
-108
-103
-95
-132
-122
-120
-109
-142
-130
-125
-115
-150
-125
-121
-110
Phase Noise2 relative
to carrier
(typical)
dBc/Hz
-85
6. CMOS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
10
10
mA
mA
ns
Output drive current
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
2.4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.2
0.2
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
0.8V ~ 2.0V
1.5
1.5
60
ns
ns
%
Clock Fall Time
Duty Cycle
2.0V ~ 0.8V
Measured @ 1.4V
40
50
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
PACKAGE INFORMATION
16 PIN TSSOP ( mm )
Symbol
Min.
-
Max.
1.20
0.15
0.30
0.20
5.10
4.50
E
H
A
A1
B
C
D
E
0.05
0.19
0.09
4.90
4.30
D
A
H
L
e
A1
C
L
B
e
3x3mm QFN
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7
PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-3X X C X X
NONE= TUBE
PART NUMBER
R= TAPE AND REEL
NONE= NORMAL PACKAGE
L= GREEN PACKAGE
TEMPERATURE
C=COMMERCIAL
I= INDUSTRIAL
PACKAGE TYPE
O=TSSOP
Q=QFN
Order Number
Marking
Package Option
Order Number
Marking
Package Option
PLL602-35OC-R
PLL602-35OC
PLL602-35OC TSSOP - Tape and Reel
PLL602-35OC TSSOP – Tube
PLL602-38OC-R
PLL602-38OC
PLL602-38QC-R
PLL602-38QC
PLL602-38OC TSSOP - Tape and Reel
PLL602-38OC TSSOP – Tube
PLL602-38QC QFN - Tape and Reel
PLL602-38QC QFN – Tube
PLL602-35QC-R
PLL602-35QC
PLL602-35QC QFN - Tape and Reel
PLL602-35QC QFN – Tube
PLL602-35OCL-R
PLL602-35OCL
PLL602-35QCL-R
PLL602-35QCL
PLL602-37OC-R
PLL602-37OC
PLL602-35OCL TSSOP - Tape and Reel (GREEN)
PLL602-35OCL TSSOP – Tube (GREEN)
PLL602-35QCL QFN - Tape and Reel (GREEN)
PLL602-35QCL QFN – Tube (GREEN)
PLL602-37OC TSSOP - Tape and Reel
PLL602-37OC TSSOP – Tube
PLL602-38OCL-R PLL602-38OCL TSSOP - Tape and Reel (GREEN)
PLL602-38OCL PLL602-38OCL TSSOP – Tube (GREEN)
PLL602-38QCL-R PLL602-38QCL QFN - Tape and Reel (GREEN)
PLL602-38QCL
PLL602-39OC-R
PLL602-39OC
PLL602-39QC-R
PLL602-39QC
PLL602-38QCL QFN – Tube (GREEN)
PLL602-39OC TSSOP - Tape and Reel
PLL602-39OC TSSOP – Tube
PLL602-37QC-R
PLL602-37QC
PLL602-37QC QFN - Tape and Reel
PLL602-37QC QFN – Tube
PLL602-39QC QFN - Tape and Reel
PLL602-39QC QFN - Tube
PLL602-37OCL-R
PLL602-37OCL
PLL602-37QCL-R
PLL602-37QCL
PLL602-37OCL TSSOP - Tape and Reel (GREEN)
PLL602-37OCL TSSOP – Tube (GREEN)
PLL602-37QCL QFN - Tape and Reel (GREEN)
PLL602-37QCL QFN – Tube (GREEN)
PLL602-39OCL-R PLL602-39OCL TSSOP - Tape and Reel (GREEN)
PLL602-39OCL PLL602-39OCL TSSOP – Tube (GREEN)
PLL602-39QCL-R PLL602-39QCL QFN - Tape and Reel (GREEN)
PLL602-39QCL PLL602-39QCL QFN – Tube (GREEN)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8
相关型号：
©2020 ICPDF网 联系我们和版权申明