PLL602-30DC [MICROCHIP]
IC,MISCELLANEOUS CLOCK GENERATOR,DIE;
| 型号： | PLL602-30DC |
| 厂家： | 
MICROCHIP |
| 描述： | IC,MISCELLANEOUS CLOCK GENERATOR,DIE 时钟 局域网 外围集成电路 |
| 文件： | 总8页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
FEATURES
DIE CONFIGURATION
65 mil
750kHz to 800MHz output range.
Low phase noise output
-127dBc/Hz for 155.52MHz @ 10kHz offset
-115dBc/Hz for 622.08MHz @ 10kHz offset
(1550,1475)
17
25
24 23 22 21
20
19
18
GNDBUF
26
16
15
14
XIN
LVCMOS
LVDSB
Selectable LVCMOS, LVPECL or LVDS output.
Selectable High Drive or Standard Drive LVCMOS.
12MHz to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Die ID:
A2828-29
27
28
XOUT
SEL3^
LVPECLB
13
12
VDDBUF
VDDBUF
29
SEL2^
3.3V operation.
Available in Die form (65 mil x 62 mil).
11
LVPECL
30
31
OE_CTRL
NC
C502A
10
9
LVDS
OE_SEL^
1
2
3
4
5
6
7
8
(0,0)
Y
DESCRIPTION
X
Note: ^ denotes internal pull up
The PLL602-30 is a monolithic low jitter and low
phase noise XO IC with LVCMOS, LVDS and
LVPECL output capabilities, covering the 750kHz to
800MHz output range using a low cost 12MHz to
25MHz crystal.
OUTPUT SELECTION AND ENABLE
This one IC can be used to produce a XO with
output frequencies ranging from FXIN / 16 to FXIN x 32
thanks to the four frequency selector pads. This
makes the PLL602-30 ideal as a universal die for
applications ranging from ADSL to SONET.
OUTSEL1 OUTSEL0
Selected Output
(Pad #18)
(Pad #25)
0
0
1
1
0
1
0
1
High Drive LVCMOS
Standard Drive LVCMOS
LVPECL
LVDS
DIE SPECIFICATIONS
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
Name
Value
State
Size
62 x 65 mil
GND
0 (Default)
Output enabled
Tri-state
0
Reverse side
Pad dimensions
Thickness
1
80 micron x 80 micron
10 mil
0
Tri-state
1 (Default)
1 (Default)
Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 1
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
BLOCK DIAGRAM
XIN
VCO
Divider
Xtal Osc
XOUT
Charge
Pump
+
Loop
Filter
CLKBAR
CLK
Reference
Divider
Phase
Detector
VCO
SEL[3:0]
OE
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
SEL2
(Pad #29)
SEL1
(Pad #19)
SEL0
(Pad #20)
Selected Multiplier
Reserved
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Fin x 32
Reserved
Reserved
Fin / 8
Fin x 2
Reserved
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 2
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
Output Voltage, dc
Storage Temperature
-0.5
-0.5
-65
V
VO
TS
TA
TJ
V
C
C
C
C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied. Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
FXIN
CL (xtal)
RE
Parallel Fundamental Mode
12
25
MHz
pF
20
AT cut
30
Ω
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Fout<24MHz
60/28/15
65/45/30
100/80/40
3.63
Supply Current, Dynamic
(with loaded outputs,
15pF)
LVPECL/
LVDS/
LVCMOS
IDD
mA
24MHz<Fout<96MHz
96MHz<Fout<700MHz
Operating Voltage
VDD
2.97
45
V
@ 50% VDD (LVCMOS)
@ 1.25V (LVDS)
Output Clock Duty Cycle
50
55
%
@ VDD – 1.3V (LVPECL)
4. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
MIN.
TYP.
MAX.
UNITS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 3
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
155.52MHz
622.08MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
4.3
5.0
35
Period Jitter,
RMS
ps
ps
ps
Period Jitter,
Peak-to-Peak
45
2.4
2.5
Integrated Jitter,
RMS
Integrated 12 kHz to 20 MHz
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz UNITS
Phase Noise,
relative to carrier
(typical)
155.52MHz
622.08MHz
-63
-52
-93
-83
-117
-105
-126
-113
-123
dBc/Hz
-110
6. LVCMOS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
IOL
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
10
10
30
30
mA
mA
mA
mA
Output Drive Current
(Standard Drive)
Output Drive Current
(High Drive)
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
2.4
1.2
ns
Output Clock Rise/Fall Time
(High Drive)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 4
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
VOS
Vout = VDD or GND
VDD = 0V
Power-Off Leakage
IOXD
IOSD
uA
1
10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50?
50?
VOD
VOS
VDIFF
RL = 100?
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 5
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
9. LVPECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
10. LVPECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - LVPECL
@80/20% - LVPECL
0.6
0.5
1.5
1.5
ns
ns
LVPECL Levels Test Circuit
LVPECL Output Skew
OUT
VDD
OUT
50
50
2.0V
50%
OUT
tSKEW
OUT
LVPECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 6
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
PAD ASSIGNMENT
Pad #
Name
Description
X (m)
Y (m)
1
2
3
4
5
6
7
8
GND
GND
248
361
109
109
109
109
109
109
109
109
Ground.
Ground.
GND
473
Ground.
GND
587
Ground.
GND
702
Ground.
NC
874
No connection.
Ground.
GND
1042
1171
GNDBUF
Ground, buffer circuitry.
Used to select between LVPECL or LVCMOS logic states for
OE. Internal pull up.
9
OE_SELECT
1400
125
10
11
12
13
14
15
16
17
LVDS
1400
1400
1400
1400
1400
1400
1400
1389
259
476
LVDS output.
LVPECL
VDDBUF
VDDBUF
LVPECLB
LVDSB
LVPECL output.
616
3.3V power supply, buffer circuitry.
3.3V power supply, buffer circuitry.
Complementary LVPECL output.
Complementary LVDS output.
LVCMOS output.
716
871
1089
1227
1365
LVCMOS
GNDBUF
Ground, buffer circuitry.
Used to select LVCMOS, LVPECL or LVDS output type.
Internal pull up.
18
OUTSEL1
1232
1365
19
20
21
22
23
24
SEL1
SEL0
VDD
VDD
VDD
VDD
1042
854
659
559
459
358
1365
1365
1365
1365
1365
1365
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
3.3V power supply.
3.3V power supply.
3.3V power supply.
3.3V power supply.
Used to select LVCMOS, LVPECL or LVDS output type.
Internal pull up.
25
OUTSEL0
194
1365
26
27
28
29
XIN
109
109
109
109
1223
1017
858
Crystal input. See crystal specification page 3.
Crystal output. See crystal specification page 3.
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
XOUT
SEL3
SEL2
646
Used to enable/disable the output(s). See Output Selection and
Enable table on page 1.
30
31
OE_CTRL
NC
109
109
397
181
No connection
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 7
750kHz – 800MHz Low Phase Noise XO (for 12 to 25MHz Crystals)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part Number, Package Type and Operating Temperature Range
Part Number
Temperature
C=Commercial (0°C to 70°C)
Package Type
D=Die
W=Wafer
Part Number/Order Number
Marking
Package Option
PLL602-30DC
PLL602-30WC
P602-30DC
P602-30WC
Die (Waffle Pack
Wafer
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/15/08 Page 8
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