TDA1306T [NXP]

Noise shaping filter DAC; 噪声整形滤波器DAC
TDA1306T
型号: TDA1306T
厂家: NXP    NXP
描述:

Noise shaping filter DAC
噪声整形滤波器DAC

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INTEGRATED CIRCUITS  
DATA SHEET  
TDA1306T  
Noise shaping filter DAC  
1998 Jan 06  
Product specification  
Supersedes data of September 1994  
File under Integrated Circuits, IC01  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
FEATURES  
General  
GENERAL DESCRIPTION  
The TDA1306T is a dual CMOS digital-to-analog  
converter with up-sampling filter and noise shaper.  
The combination of oversampling up to 4fs, noise shaping  
and continuous calibration conversion ensures that only  
simple 1st-order analog post-filtering is required.  
Double-speed mode  
Digital volume control  
Soft mute function  
The TDA1306T supports the I2S-bus data input mode  
(fsys = 256fs) with word lengths of up to 20 bits and the  
LSB fixed serial data input format (fsys = 384fs) with word  
lengths of 16, 18 or 20 bits. Two cascaded IIR filters  
increase the sampling rate 4 times.  
12 dB attenuation  
Low power dissipation  
Digital de-emphasis  
TDA1305T pin compatible.  
The DACs are of the continuous calibration type and  
incorporate a special data coding. This ensures a high  
signal-to-noise ratio, wide dynamic range and immunity to  
process variation and component ageing.  
Easy application  
Voltage output  
Only 1st-order analog post-filtering required  
Operational amplifiers and digital filter integrated  
Selectable system clock (fsys) 256fs or 384fs  
Two on-board operational amplifiers convert the  
digital-to-analog current to an output voltage.  
I2S-bus (fsys = 256fs) or 16, 18 or 20 bits LSB fixed  
serial input format (fsys = 384fs)  
Single rail supply.  
High performance  
Superior signal-to-noise ratio  
Wide dynamic range  
No zero crossing distortion  
Inherently monotonic  
Continuous calibration digital-to-analog conversion  
combined with noise shaping technique.  
ORDERING INFORMATION  
PACKAGE  
TYPE NUMBER  
NAME  
DESCRIPTION  
plastic small outline package; 24 leads; body width 7.5 mm.  
VERSION  
TDA1306T  
SO24  
SOT1371  
1998 Jan 06  
2
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
QUICK REFERENCE DATA  
All power supply pins VDD and VSS must be connected to the same external supply unit.  
SYMBOL  
Supply  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VDDD  
VDDA  
VDDO  
digital supply voltage  
analog supply voltage  
4.5  
5.0  
5.5  
V
V
V
4.5  
4.5  
5.0  
5.0  
5.5  
5.5  
operational amplifier  
supply voltage  
IDDD  
IDDA  
IDDO  
digital supply current  
VDDD = 5 V;  
at code 00000H  
5
3
2
8
5
4
mA  
mA  
mA  
analog supply current  
VDDA = 5 V;  
at code 00000H  
operational amplifier  
supply current  
VDDO = 5 V;  
at code 00000H  
Analog signals  
VFS(rms)  
full-scale output voltage  
(RMS value)  
VDDD = VDDA = VDDO = 5 V; 0.935  
RL > 5 kΩ  
1.1  
1.265  
V
RL  
output load resistance  
5
kΩ  
DAC performance  
(THD + N)/S  
total harmonic distortion  
plus noise-to-signal ratio  
at 0 dB signal level;  
fi = 1 kHz;  
70  
0.032  
42  
0.8  
dB  
%
at 60 dB signal level;  
fi = 1 kHz;  
32  
2.5  
96  
2.822  
dB  
%
S/N  
BR  
signal-to-noise ratio  
no signal; A-weighted  
108  
dB  
input bit rate at data input fs = 44.1 kHz;  
normal speed  
Mbits/s  
fs = 44.1 kHz;  
double speed  
5.645  
18.432  
+85  
Mbits/s  
MHz  
°C  
fsys  
system clock frequency  
(pin 12)  
6.4  
40  
Tamb  
operating ambient  
temperature  
1998 Jan 06  
3
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
BLOCK DIAGRAM  
Fig.1 Block diagram.  
4
1998 Jan 06  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
PINNING  
SYMBOL PIN  
DESCRIPTION  
VDDA  
1
2
3
analog supply voltage (+5 V)  
analog ground  
VSSA  
TEST1  
test input 1; pin should be connected  
to ground  
BCK  
4
5
6
7
8
9
bit clock input  
WS  
word select input  
DATA  
CLKS1  
CLKS2  
VSSD  
data input  
clock and format selection 1 input  
clock and format selection 2 input  
digital ground  
VDDD  
TEST2  
10 digital supply voltage (+5 V)  
11 test input 2; pin should be connected  
to ground  
SYSCLK  
APP3  
APPL  
APP2  
APP1  
APP0  
VOL  
12 system clock input 256fs or 384fs  
13 application mode 3 input  
14 application mode selection input  
15 application mode 2 input  
16 application mode 1 input  
17 application mode 0 input  
18 left channel output  
FILTCL  
19 capacitor for left channel 1st order  
filter function; should be connected  
between pins 19 and 18  
FILTCR  
20 capacitor for right channel 1st order  
filter function; should be connected  
between pins 20 and 21  
VOR  
Vref  
21 right channel output  
22 internal reference voltage for output  
channels; 0.5VDDO (typ.)  
VSSO  
VDDO  
23 operational amplifier ground  
Fig.2 Pin configuration.  
24 operational amplifier supply voltage  
1998 Jan 06  
5
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
The TDA1306T supports the following data input modes:  
FUNCTIONAL DESCRIPTION  
I2S-bus with data word length of up to 20 bits  
(fsys = 256fs)  
The TDA1306T CMOS DAC incorporates an up-sampling  
filter, a noise shaper, continuous calibrated current  
sources and operational amplifiers.  
LSB fixed serial format with data word length of 16, 18  
or 20 bits (fsys = 384fs). As this format idles on the MSB  
it is necessary to know how many bits are being  
transmitted.  
System clock and data input format  
The TDA1306T accommodates slave mode only.  
Consequently, in all applications, the system devices must  
provide the system clock. The system frequency is  
selectable at pins CLKS1 and CLKS2 (see Table 1).  
The input formats are illustrated in Fig.9. Left and right  
data channel words are time multiplexed.  
Table 1 Data input format and system clock  
SYSTEM CLOCK  
CLKS1  
CLKS2  
DATA INPUT FORMAT  
I2S-bus  
NORMAL SPEED  
DOUBLE SPEED  
0
0
1
1
0
1
0
1
256fs  
384fs  
384fs  
384fs  
128fs  
192fs  
192fs  
192fs  
LSB fixed 16 bits  
LSB fixed 18 bits  
LSB fixed 20 bits  
Device operation  
When the APPL pin is held HIGH and APP3 is held LOW,  
pins APP0, APP1 and APP2 form a microcontroller  
interface. When the APPL pin is held LOW, pins APP0,  
APP1, APP2 and APP3 form a pseudo-static application  
(TDA1305T pin compatible).  
PSEUDO-STATIC APPLICATION MODE (APPL = LOGIC 0)  
In this mode, the device operation is controlled by  
pseudo-static application pins where:  
APP0 = attenuation mode control  
APP1 = double-speed mode control  
APP2 = mute mode control  
APP3 = de-emphasis mode control.  
In the pseudo-static application mode the TDA1306T is pin  
compatible with the TDA1305T slave mode.  
The correspondence between TDA1306T pin number,  
TDA1306T pin name, TDA1305T pin mnemonic and a  
description of the effects is given in Table 2.  
1998 Jan 06  
6
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
Table 2 Pseudo-static application mode  
PIN  
MNEMONIC  
TDA1305T  
FUNCTION  
PIN NUMBER  
VALUE  
DESCRIPTION  
APP0  
17  
ATSB  
0
12 dB attenuation (from full scale) activated  
(only if MUSB = logic 1)  
1
0
1
0
1
0
1
full scale (only if MUSB = logic 1)  
double-speed mode  
APP1  
APP2  
APP3  
16  
15  
13  
DSMB  
MUSB  
DEEM1  
normal-speed mode  
samples decrease to mute level  
level according to ATSB  
de-emphasis OFF (44.1 kHz)  
de-emphasis ON (44.1 kHz)  
MICROCONTROLLER APPLICATION MODE (APPL = LOGIC  
1 AND APP3 = LOGIC 0)  
MICROCONTROLLER WRITE OPERATION SEQUENCE  
The microcontroller write operation follows the following  
sequence:  
In this mode, the device operation is controlled by a set of  
flags in an 8-bit mode control register. The 8-bit mode  
control register is written by a microcontroller interface  
where:  
APP2 is held LOW by the microcontroller  
Microcontroller data is clocked into the internal shift  
register on the LOW-to-HIGH transition on pin APP1  
APPL = logic 1  
APP0 = Data  
APP1 = Clock  
APP2 = RAB  
APP3 = logic 0.  
Data D7 to D0 is latched into the appropriate control  
register on the LOW-to-HIGH transition of pin APP2  
(APP1 = HIGH)  
If more data is clocked into the TDA1306T before the  
LOW-to-HIGH transition on pin APP2 then only the last  
8 bits are used  
The correspondence between serial-to-parallel  
conversion, mode control flags and a summary of the  
effect of the control flags is given in Table 3.  
Figures 3 and 4 illustrate the mode set timing.  
If less data is clocked into the TDA1306T unpredictable  
operation will result  
If the LOW-to-HIGH transition of pin APP2 occurs when  
APP1 = LOW, the command will be disregarded.  
Fig.3 Microcontroller timing.  
1998 Jan 06  
7
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
between APP2 pulses. A minimum pause of 22 µs is  
necessary between any two step-up or step-down  
commands.  
MICROCONTROLLER WRITE OPERATION SEQUENCE (REPEAT  
MODE)  
The same command can be repeated several times (e.g.  
for fade function) by applying APP2 pulses as shown in  
Fig.4. It should be noted that APP1 must stay HIGH  
Fig.4 Microcontroller timing (repeat mode).  
Table 3 Microcontroller mode control register  
BIT POSITION  
FUNCTION  
DESCRIPTION  
ACTIVE LEVEL  
D7  
ATSB  
12 dB attenuation  
(from full scale)  
LOW  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
DSMB  
MUSB  
double speed  
mute  
LOW  
LOW  
DEEM  
de-emphasis  
full scale  
HIGH  
FS  
HIGH  
INCR  
increment  
decrement  
reserved  
HIGH  
DECR  
HIGH  
not applicable  
not applicable  
1998 Jan 06  
8
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
Volume control  
VOLUME CONTROL (PSEUDO-STATIC APPLICATION MODE)  
A digital level control is incorporated in the TDA1306T  
which performs the function of soft mute and attenuation  
(pseudo-static application mode) or soft mute, attenuation,  
fade, increment and decrement (microcontroller  
application mode). The volume control of both channels  
can be varied in small step changes determined by the  
value of the internal fade counter where:  
In the pseudo-static application mode (APPL = logic 0) the  
digital audio output level is controlled by APP0  
(attenuation) and APP2 (mute) so only the final volume  
levels full scale, 12 dB (attenuate) and mute (infinity dB)  
can be selected. The mute function has priority over the  
attenuation function. Accordingly, if MUSB is LOW, the  
state of ATSB has no effect. An example of volume control  
in this application mode is illustrated in Fig.5.  
Audio level = counter × maximum level/120.  
Where the counter is a 7-bit binary number between 0 and  
120. The time taken for mute to vary from 120 to 0 is  
1/120fs. For example, when fs = 44.1 kHz, the time taken  
is approximately 3 ms.  
Fig.5 Volume control (pseudo-static application mode).  
1998 Jan 06  
9
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
To control the fade counter in a continuous way, the  
VOLUME CONTROL (MICROCONTROLLER APPLICATION MODE)  
INCREMENT and DECREMENT commands are available  
(fade control Registers D1 and D2). They will increment  
and decrement the counter by 1 for each register write  
operation. When issuing more than 1 step-up or  
step-down command in sequence, the write repeat mode  
may be used (see microcontroller application mode). An  
example of volume control in this application mode is  
illustrated in Fig.6.  
In the microcontroller application mode (APPL = logic 1,  
APP3 = logic 0) the audio output level is controlled by  
volume control bits ATSB, MUSB, FS, INCR and DECR.  
Mute is activated by sending the MUSB command to the  
mode control register via the microcontroller interface. The  
audio output level will be reduced to zero in a maximum of  
120 steps (depending on the current position of the fade  
counter) and taking a maximum of 3 ms. Mute, attenuation  
and full scale are synchronized to prevent operation in the  
middle of a word.  
The counter is preset to 120 by the full scale command  
The counter is preset to 30 by the attenuate command  
when its value is more then 30. If the value of the  
counter is less than 30 dB the ATSB command has no  
effect.  
The counter is preset to logic 0 by the mute command  
MUSB  
Attenuation (12 dB) is activated by sending the ATSB  
command to the fade control register (D7)  
Attenuation and mute are cancelled by sending the  
full-scale command to the fade control register  
(Register D3).  
(1) INCR and DECR in repeat mode.  
Fig.6 Volume control (microcontroller application mode).  
1998 Jan 06  
10  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
There are two recommended application situations within  
the microcontroller mode:  
Double-speed mode  
The double-speed mode is controlled by the DSMB bit at  
register D6 (microcontroller application mode) or by  
activating the APP1 pin (pseudo-static application mode).  
When the control bit is active LOW the device operates in  
the double-speed mode.  
The customer wants to use the microcontroller interface  
without the volume setting facility. In this event the  
operation is as follows:  
– Mute ON; by sending the MUSB command  
– Mute OFF; by sending the FS command  
Oversampling filter and noise shaper  
– Attenuation ON; by sending the ATSB command  
– Attenuation OFF; by sending the FS command.  
The digital filter is a four times oversampling filter.  
It consists of two sections which each increase the sample  
rate by 2. The noise-shaper operates on 4fs and reduces  
the in-band noise density.  
It is possible to switch from ‘Attenuation ON’ to ‘Mute  
ON’ but not vice-versa.  
Incorporating the volume control feature operates as  
follows:  
DAC and operational amplifiers  
– Mute ON; by sending the MUSB command the  
microcontroller has to store the previous volume  
setting  
In this noise shaping filter DAC a special data code and  
bidirectional current sources are used in order to achieve  
true low-noise performance. The special data code  
guarantees that only small values of current flow to the  
output during small signal passages while larger positive  
or negative values are generated using the bidirectional  
current sources. The noise shaping filter-DAC uses the  
continuous calibration conversion technique.  
– Mute OFF; by sending succeeding INCR commands  
until the previous volume is reached  
– Attenuation ON; by sending succeeding DECR  
commands until a relative downstep of 12 dB is  
reached.  
The operational amplifiers and the internal conversion  
resistors RCONV1 and RCONV2 convert the DAC current to  
an output voltage available at VOL and VOR. Connecting an  
external capacitor between FILTCL and VOL, FILTCR and  
VOR respectively provides the required 1st-order post  
filtering.  
The microcontroller has to store the previous volume  
– Attenuation OFF; by sending the succeeding INCR  
commands until the previous volume is reached  
– Volume UP; by sending succeeding INCR  
commands  
– Volume DOWN; by sending succeeding DECR  
commands.  
De-emphasis  
A digital de-emphasis is implemented in the TDA1306T.  
By selecting the DEEM bit at register D4 (microcontroller  
application mode) or activating the APP3 pin  
(pseudo-static application mode), de-emphasis can be  
applied by means of an IIR filter. De-emphasis is  
synchronized to prevent operation in the middle of a word.  
1998 Jan 06  
11  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VDD  
PARAMETER  
supply voltage  
CONDITIONS  
MIN.  
MAX.  
7.0  
UNIT  
note 1  
V
Txtal  
Tstg  
Tamb  
Ves  
maximum crystal temperature  
storage temperature  
+150  
+125  
+85  
°C  
°C  
°C  
V
65  
operating ambient temperature  
electrostatic handling  
40  
note 2  
note 3  
2000  
200  
+2000  
+200  
V
Notes  
1. All VDD and VSS connections must be made to the same power supply.  
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kseries resistor.  
3. Equivalent to discharging a 200 pF capacitor via a 2.5 mH series inductor.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
in free air  
VALUE  
69  
UNIT  
Rth j-a  
thermal resistance from junction to ambient  
K/W  
QUALITY SPECIFICATION  
In accordance with “UZW-BO/FQ-0601”.  
1998 Jan 06  
12  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
DC CHARACTERISTICS  
VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; all voltages referenced to ground (pins 2, 9 and 23); unless otherwise  
specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
note 1  
MIN.  
TYP.  
MAX.  
5.5  
UNIT  
VDDD  
VDDA  
VDDO  
digital supply voltage (pin 10)  
analog supply voltage (pin 1)  
4.5  
4.5  
4.5  
5.0  
5.0  
5.0  
V
note 1  
note 1  
5.5  
5.5  
V
V
operational amplifier supply  
voltage (pin 24)  
IDDD  
IDDA  
IDDO  
digital supply current  
analog supply current  
fsys = 11.28 MHz  
at digital silence  
5
3
2
8
6
4
mA  
mA  
mA  
operational amplifier supply  
current  
no operational  
amplifier load resistor  
Ptot  
total power dissipation  
fsys = 11.28 MHz;  
digital silence; no  
operational amplifier  
load resistor  
50  
90  
mW  
VIH  
VIL  
HIGH level digital input voltage  
(pins 3 to 8 and 11 to 17)  
0.7VDDD  
0.5  
VDDD + 0.5  
+0.3VDDD  
134  
V
LOW level digital input voltage  
(pins 3 to 8 and 11 to 17)  
V
Rpd  
internal pull-down resistor to  
VSSD (pins 3 and 11)  
17  
kΩ  
|ILI|  
input leakage current  
input capacitance  
10  
µA  
pF  
V
Ci  
10  
Vref  
RCONV  
reference voltage (pin 22)  
with respect to VSSO  
0.45VDDO 0.5VDDO  
0.55VDDO  
3.6  
current-to-voltage conversion  
resistor  
2.4  
0.935  
5
3.0  
1.1  
kΩ  
VFS(rms)  
full-scale output voltage (RMS RL > 5 k; note 2  
value)  
1.265  
V
RL  
output load resistance  
kΩ  
Notes  
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.  
2. RL is the AC resistance of the external circuitry connected to the audio outputs of the application circuit.  
1998 Jan 06  
13  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
AC CHARACTERISTICS (ANALOG)  
VDDD = VDDA = VDDO = 5 V; Tamb = 25 °C; all voltages referenced to ground (pins 2, 9 and 23); unless otherwise  
specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
DACs  
SVRR  
supply voltage ripple  
rejection VDDA and VDDO  
fripple = 1 kHz;  
Vripple = 100 mV (p-p);  
C22 = 10 µF  
40  
dB  
Gv  
unbalance between the  
2 DAC voltage outputs  
(pins 18 and 21)  
maximum volume  
0.5  
dB  
dB  
α
crosstalk between the 2 DAC one output digital silence  
110  
85  
ct  
voltage outputs  
(pins 18 and 21)  
the other maximum volume  
(THD + N)/S total harmonic distortion  
plus noise-to-signal ratio  
at 0 dB signal level;  
fi = 1 kHz  
70  
dB  
%
0.032  
42  
at 60 dB signal level;  
fi = 1 kHz  
32  
2.5  
96  
dB  
%
0.8  
S/N  
signal-to-noise ratio  
no signal; A-weighted  
108  
dB  
Operational amplifiers  
Gv  
open-loop voltage gain  
power supply rejection ratio  
85  
90  
dB  
dB  
PSRR  
f
V
ripple = 3 kHz;  
ripple = 100 mV (p-p);  
A-weighted  
(THD + N)/S total harmonic distortion  
plus noise-to-signal ratio  
RL > 5 k; fi = 1 kHz;  
Vo = 2.8 V (p-p)  
100  
dB  
fUG  
unity gain frequency  
AC output impedance  
open loop  
4.5  
1.5  
MHz  
|Zo|  
RL > 5 kΩ  
150  
1998 Jan 06  
14  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
AC CHARACTERISTICS (DIGITAL)  
VDDD = VDDA = VDDO 4.5 to 5.5 V; all voltages referenced to ground (pins 2, 9 and 23); Tamb = 40 to +85 °C; unless  
otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
54.2  
TYP.  
59.1  
MAX.  
104  
UNIT  
ns  
TWX  
clock cycle time  
fsys = 384fs; normal speed  
f
sys = 192fs; double speed  
fsys = 256fs; normal speed  
sys = 128fs; double speed  
54.2  
81.3  
81.3  
22  
59.1  
88.6  
88.6  
104  
156  
156  
ns  
ns  
ns  
ns  
ns  
f
tCWL  
tCWH  
fsys LOW level pulse width  
fsys HIGH level pulse width  
22  
Serial input data timing (see Fig.8)  
fs  
word select input audio  
sample frequency  
normal speed  
25  
50  
44.1  
88.2  
48  
96  
64fs  
64fs  
64fs  
48fs  
20  
20  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
ns  
double speed  
fBCK  
clock input frequency  
(data input rate)  
fsys = 384fs; normal speed; note 1  
f
sys = 192fs; double speed; note 1  
fsys = 256fs; normal speed  
sys = 128fs; double speed; note 2  
f
tr  
rise time  
tf  
fall time  
ns  
tH  
bit clock HIGH time  
bit clock LOW time  
data set-up time  
data hold time  
55  
55  
20  
10  
20  
10  
ns  
tL  
ns  
tsu  
th  
ns  
ns  
tsuWS  
thWS  
word select set-up time  
word select hold time  
ns  
ns  
Microcontroller interface timing (see Fig.9)  
tL  
input LOW time  
2
2
1
1
1
µs  
µs  
µs  
µs  
µs  
tH  
Input HIGH time  
tsuDC  
thCD  
tsuCR  
set-up time DATA to CLOCK  
hold time CLOCK to DATA  
set-up time CLOCK to RAB  
Notes  
1. A clock frequency of up to 96fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.  
2. A clock frequency of up to 64fs is possible in the event of a rising edge of BCK occurring during SYSCLK = LOW.  
1998 Jan 06  
15  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
1998 Jan 06  
16  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
Fig.8 Timing of input signals.  
Fig.9 Microcontroller timing.  
17  
1998 Jan 06  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
TEST AND APPLICATION INFORMATION  
Filter characteristics  
Table 4 Digital filter specification (fs = 44.1 kHz)  
BAND  
0 to 19 kHz  
ATTENUATION  
< 0.001 dB  
19 to 20 kHz  
24 kHz  
< 0.03 dB  
> 25 dB  
> 40 dB  
> 50 dB  
> 31 dB  
> 35 dB  
> 40 dB  
25 to 35 kHz  
35 to 64 kHz  
64 to 68 kHz  
68 kHz  
69 to 88 kHz  
Table 5 Digital filter phase distortion (fs = 44.1 kHz)  
BAND PHASE DISTORTION  
0 to 16 kHz < ±1°  
1998 Jan 06  
18  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
PACKAGE OUTLINE  
SO24: plastic small outline package; 24 leads; body width 7.5 mm  
SOT137-1  
D
E
A
X
c
H
v
M
A
E
y
Z
24  
13  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
12  
w
detail X  
e
M
b
p
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
max.  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30  
0.10  
2.45  
2.25  
0.49  
0.36  
0.32  
0.23  
15.6  
15.2  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.1  
1.0  
0.9  
0.4  
mm  
2.65  
0.25  
0.01  
1.27  
0.050  
1.4  
0.25 0.25  
0.01  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.019 0.013 0.61  
0.014 0.009 0.60  
0.30  
0.29  
0.419  
0.394  
0.043 0.043  
0.016 0.039  
0.035  
0.016  
inches 0.10  
0.055  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-01-24  
97-05-22  
SOT137-1  
075E05  
MS-013AD  
1998 Jan 06  
19  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
SOLDERING  
Introduction  
Wave soldering  
Wave soldering techniques can be used for all SO  
packages if the following conditions are observed:  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave) soldering  
technique should be used.  
The longitudinal axis of the package footprint must be  
parallel to the solder flow.  
The package footprint must incorporate solder thieves at  
the downstream end.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011).  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Reflow soldering  
Reflow soldering techniques are suitable for all SO  
packages.  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Several techniques exist for reflowing; for example,  
thermal conduction by heated belt. Dwell times vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow temperatures range from  
215 to 250 °C.  
Repairing soldered joints  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheating duration: 45 minutes at  
45 °C.  
1998 Jan 06  
20  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1998 Jan 06  
21  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
NOTES  
1998 Jan 06  
22  
Philips Semiconductors  
Product specification  
Noise shaping filter DAC  
TDA1306T  
NOTES  
1998 Jan 06  
23  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
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Tel. +31 40 27 82785, Fax. +31 40 27 88399  
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Brazil: see South America  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
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Tel. +359 2 689 211, Fax. +359 2 689 102  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
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Czech Republic: see Austria  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
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Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427  
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Tel. +34 3 301 6312, Fax. +34 3 301 4107  
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Tel. +49 40 23 53 60, Fax. +49 40 23 536 300  
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Tel. +46 8 632 2000, Fax. +46 8 632 2745  
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Tel. +30 1 4894 339/239, Fax. +30 1 4814 240  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2686, Fax. +41 1 488 3263  
Hungary: see Austria  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
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Tel. +66 2 745 4090, Fax. +66 2 398 0793  
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Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,  
Tel. +90 212 279 2770, Fax. +90 212 282 6707  
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TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,  
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421  
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Tel. +81 3 3740 5130, Fax. +81 3 3740 5077  
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Tel. +1 800 234 7381  
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Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Uruguay: see South America  
Vietnam: see Singapore  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 625 344, Fax.+381 11 635 777  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,  
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1998  
SCA57  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
547027/1200/02/pp24  
Date of release: 1998 Jan 06  
Document order number: 9397 750 03168  

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