TDA1307 [NXP]
High-performance bitstream digital filter; 高性能流数字滤波器
| 型号： | TDA1307 |
| 厂家： | 
NXP |
| 描述： | High-performance bitstream digital filter |
| 文件： | 总36页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA1307
High-performance bitstream digital
filter
1996 Jan 08
Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
FEATURES
• Multiple format inputs: I2S, Sony 16, 18 and 20-bit
• 8-sample interpolation error concealment
• Digital mute, attenuation −12 dB
• Digital audio output function (biphase-mark encoded)
according to IEC 958
• Digital silence detection (output)
• Digital de-emphasis (selectable, FS-programmable)
• Differential mode bitstream: complementary data
outputs available
• 8 × oversampling finite impulse response (FIR) filter
• DC-cancelling filter (selectable)
• Simple 3-line serial microprocessor command interface
• Flexible system clock oscillator circuitry
• Power-on reset
• Peak detection (continuous) and read-out to
microprocessor
• Fade function: sophisticated volume control
• Selectable 3rd/4th order noise shaping
• Selectable dither generation and automatic scaling
• Dedicated TDA1547 1-bit output
• Standby function
• SDIP42 package.
QUICK REFERENCE DATA
Voltages are referenced to VSS (ground = 0 V); all VSS and all VDD connections should be connected externally to the
same supply.
SYMBOL
VDDC1,2,3
PARAMETER
supply voltage
CONDITIONS
MIN.
4.5
TYP.
5.0
MAX.
5.5
UNIT
V
(pins 21, 41 and 8)
VDDOSC
VDDAR
supply voltage (pin 24)
supply voltage (pin 32)
supply voltage (pin 29)
4.5
4.5
4.5
−
5.0
5.0
5.0
75
5.5
5.5
5.5
−
V
V
V
VDDAL
IDDC1,2,3
supply current
VDD = 5 V
mA
(pins 21, 41 and 8)
IDDOSC
IDDAR
IDDAL
fXTAL
Tamb
Ptot
supply current (pin 24)
supply current (pin 32)
supply current (pin 29)
oscillator clock frequency
operating ambient temperature
total power consumption
VDD = 5 V
VDD = 5 V
VDD = 5 V
−
2
−
mA
mA
mA
MHz
°C
−
2
−
−
1
−
−
33.8688
−
−
−20
−
+70
−
400
mW
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
DESCRIPTION
plastic shrink dual in-line package; 42 leads (600 mil)
NAME
VERSION
TDA1307
SDIP42
SOT270-1
1996 Jan 08
2
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
audio peak data information and an advanced patented
digital fade function are accessible through a simple
microprocessor command interface, which also provides
access to various integrated system settings
and functions.
GENERAL DESCRIPTION
The TDA1307 is an advanced oversampling digital filter
employing bitstream conversion technology, which has
been designed for use in premium performance digital
audio applications. Audio data is input to the TDA1307
through its multiple-format interface. Any of the four
formats (I2S, Sony 16, 18 or 20-bit) are acceptable. By
using a highly accurate audio data processing structure,
including 8 times oversampling digital filtering and up to
4th order noise shaping, a high quality bitstream is
produced which, when used in the recommended
combination with the TDA1547 bitstream DAC, provides
the optimum in dynamic range and signal-to-noise
performance. With the TDA1307, a high degree of
versatility is achieved by a multitude of functional features
and their easy accessibility; error concealment functions,
TDA1307 plus TDA1547 high-performance bitstream
digital filter plus DAC combination:
For many features:
• Highly accessible structure
• Intelligent audio data processing.
For optimum performance:
• 4th order noise shaping
• Improvement dynamic range (113 dB)
• Improvement signal-to-noise (115 dB).
f
= 768f
s
system
20-bit f
1-bit, 192f
s
L
s
TDA1307
TDA1547
R
8 × oversampling FIR
filter, 20-bit
24 × upsampling
1-bit high-performance
3rd order analog
digital-to-analog
converter
postfilter, f = 55 kHz
o
Butterworth response
3rd or 4th order noise shaping,
1-bit end quantization
MGB983
Fig.1 High performance bitstream reconstruction system.
1996 Jan 08
3
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
BLOCK DIAGRAM
1f AUDIO DATA INPUTS
s
WS
SCK
2
SD
EFAB
4
1
3
TDA1307
19
MULTIPLE FORMAT
INPUT INTERFACE
RESYNC
10
DOBM
13
DSTB
ERROR CONCEALMENT,
INTERPOLATION, MUTING
DIGITAL
OUTPUT
5
SBCL
6
SBDA
12
11
DSR
DIGITAL SILENCE DETECTION
DSL
36
37
TEST1
TEST2
25
V
SSOSC
DE–EMPHASIS FILTER
22
XTAL1
23
CRYSTAL
OSCILLATOR
XTAL2
FIR HALFBAND FILTER
STAGE 1: 1f to 2f
s
s
38
39
42
20
DA
CL
15
CLOCK
GENERATION
AND
DC–CANCELLING FILTER
PEAK DETECTION
CMIC
MICRO–
PROCESSOR
INTERFACE
7
CDEC
DISTRIBUTION
14
CLC1
RAB
POR
17
CLC2
18
CDCC
FADE FUNCTION
VOLUME CONTROL
9
V
SSC2
8
V
DDC3
DDC1
16
V
SSC3
30
21
V
V
FIR HALFBAND FILTER
STAGE 2: 2f to 4f
SSAL
31
s
s
V
SSAR
24
29
32
41
V
DDOSC
40
V
SSC1
FIR HALFBAND FILTER
STAGE 3: 4f to 8f
V
DDAL
s
s
V
DDAR
DITHER AND SCALING
V
DDC2
3rd/4th ORDER
NOISE SHAPER
27
DOL
28
35
34
33
DOR
26
MODE
MGB989
NDOL
CDAC
NDOR
BITSTREAM DATA OUTPUTS
Fig.2 Block diagram.
4
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
PINNING
SYMBOL
WS
PIN
TYPE, I/O
DESCRIPTION
word select input to data interface
1
2
3
4
5
I
SCK
SD
I
clock input to data interface
data input to interface
I
EFAB
SBCL
I(1)
I
error flag (active HIGH): input from decoder chip indicating unreliable data
subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes
the subcode data
SBDA
CDEC
6
7
I
subcode data: a 10-bit burst of data, including flags and sync bits, serially input
once per frame, clocked by burst clock input SBCL
O
decoder clock output: frequency division programmable by means of
pins 14 (CLC1) and 17 (CLC2) to output 192, 256, 384 or 768 times fs
VDDC3
VSSC2
DOBM
8
9
positive supply 3
ground 2
10
O
digital audio output: this output contains digital audio samples which have
received interpolation, attenuation and muting plus subcode data;
transmission is in biphase-mark code
DSL
11
12
13
14
15
O
O
I(2)
I
digital silence detected (active LOW) on left channel
digital silence detected (active LOW) on right channel
DOBM standby mode enforce pin (active HIGH)
DSR
DSTB
CLC1
CMIC
application mode programming pin for CDEC (pin 7) frequency division
O
clock output, provided to be used as running clock by microprocessor
(in master mode only), output 96fs
VSSC3
16
17
18
19
20
21
22
23
24
25
26
ground 3
CLC2
I
I
application mode programming pin for CDEC (pin 7) frequency division
master / slave mode selection pin
CDCC
RESYNC
POR
O
I(2)
resynchronization: out-of-lock indication from data input section (active HIGH)
power-on reset (active LOW)
VDDC1
XTAL1
XTAL2
VDDOSC
VSSOSC
MODE
supply voltage 1
I
crystal oscillator terminal: local crystal oscillator sense forced input in slave mode
crystal oscillator output: drive output to crystal
positive supply connection to crystal oscillator circuitry
ground connection to crystal oscillator circuitry
O
I(2)
evaluation mode programming pin (active LOW); in normal operation, this pin
should be left open-circuit or connected to the positive supply
DOL
27
28
29
30
31
32
33
O
O
data output left channel to bitstream DAC TDA1547
NDOL
VDDAL
VSSAL
VSSAR
VDDAR
DOR
complementary data output left channel to TDA1547 in double differential mode
positive supply connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, right channel
positive supply connection to output data driving circuitry, right channel
data output right channel to TDA1547
O
1996 Jan 08
5
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
SYMBOL
PIN
TYPE, I/O
DESCRIPTION
NDOR
CDAC
TEST1
TEST2
DA
34
35
O
complementary data output right channel to TDA1547 in double differential mode
clock output to bitstream DAC TDA1547
O
36 I(1)
37 I(1)
38 I/O(2)
test mode input; in normal operation this pin should be connected to ground
test mode input; in normal operation this pin should be connected to ground
bidirectional data line intended for control data from the microprocessor and peak
data from the TDA1307
CL
39 I(2)
40
clock input, to be generated by the microprocessor
ground 1
VSSC1
VDDC2
RAB
41
42 I(2)
supply voltage 2
command / peak data request line
Notes
1. These pins are configured as internal pull-down.
2. These pins are configured as internal pull-up.
handbook, halfpage
1
42
41
40
39
38
37
36
35
34
33
WS
SCK
RAB
V
2
3
DDC2
SD
V
SSC1
4
EFAB
SBCL
SBDA
CDEC
CL
5
DA
6
TEST2
TEST1
CDAC
NDOR
DOR
7
8
V
DDC3
9
V
SSC2
10
DOBM
11 TDA1307 32
DSL
DSR
V
DDAR
12
13
14
15
16
17
18
19
20
21
31
30
29
28
27
26
25
24
23
22
V
SSAR
DSTB
CLC1
CMIC
V
SSAL
V
DDAL
NDOL
DOL
V
SSC3
CLC2
MODE
CDCC
RESYNC
POR
V
SSOSC
V
DDOSC
XTAL2
XTAL1
V
DDC1
MGB980
Fig.3 Pin configuration.
6
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
a crystal of 768fs (33.8688 MHz) to the crystal oscillator
pins XTAL1 (pin 22) and XTAL2 (pin 23); and the slave
mode, in which the TDA1307 is supplied a clock by the IC
in the system that acts as the master (e.g. the digital audio
interface receiver). In this event a clock signal frequency of
256fs is input to pin XTAL1. Master or slave mode is
programmed by means of pin CDCC (pin 18) logic 1 for
master and logic 0 for slave mode. The circuit diagram of
Fig.4 shows the typical connection of the external
oscillator circuitry and crystal resonator for master mode
operation. Note that the positive supply VDDOSC is the
reference to the oscillator circuitry. The LC network is used
for suppression of the fundamental frequency component
of the overtone crystal. Figure 5 shows how to connect for
slave mode operation. A clock frequency of typical 256fs
and levels of 0 V/+5 V is input to XTAL1 via AC coupling.
The 100 kΩ resistor and the 10 nF capacitor are required
to provide the necessary biasing for XTAL2 by filtering and
feeding back the output signal of XTAL1.
FUNCTIONAL DESCRIPTION
In the block diagram, Fig.1, a general subdivision into
three main functional sections is illustrated. The actual
signal processing takes place in the central sequence of
blocks, a representation of the audio data path from top to
bottom. The two blocks named “Microprocessor Interface”
and “Clock Generation and Distribution” fulfil a general
auxiliary function to the audio data processing path. The
Microprocessor Interface provides access to all the blocks
in the audio path that require or allow for configuration or
selection, and manipulates data read-out from the Peak
Detection block, all via a simple three-line interface. The
Clock Generation and Distribution section, driven either by
its integrated oscillator circuit with external crystal or by an
externally provided master clock, provides the data
processing blocks with timebases, manages the system
mode dependent frequency settings, and conveniently
generates clocks for external use by the system decoder
IC and microprocessor. Following are detailed
Besides generating all necessary internal clocks for the
audio data processing blocks and the clock to the DAC, the
clock generation block further provides two clocks for
external use when operating in master mode. Pin CDEC
(pin 7) is used as the running clock for the system
decoder IC, and pin CMIC (pin 15) is used as the running
clock for the system microprocessor. CMIC outputs, by a
fixed divider ratio to XTAL2, a clock signal at 96fs. For
CDEC the divider ratio is programmable by means of pins
CLC1 (pin 14) and CLC2 (pin 17). Table 1 gives the clock
divider programming relationships.
explanations of the functions of each block in the audio
data processing path and their setting options manipulated
by the microprocessor interface, the use of the
microprocessor interface, and the functions of the clock
section with its various system settings.
Clock generation and distribution
The clock generation section of the TDA1307 is designed
to accommodate two main modes. The master mode, in
which the TDA1307 is the master in the digital audio
system, and for which the clock is generated by connecting
Table 1 Clock divider programming
CLC1
CLC2
CDEC OUTPUT FREQUENCY
0
0
1
1
0
1
0
1
256fs
384fs
768fs
192fs
1996 Jan 08
7
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
handbook, halfpage
XTAL2
33.8688
23
22
24
25
3.3
µH
100
kΩ
MHz
XTAL1
10
kΩ
10
pF
10
pF
1 nF
TDA1307
V
DDOSC
+5 V
V
SSOSC
MGB981
Fig.4 External crystal oscillator circuit.
handbook, halfpage
f = 256f
20 pF
XTAL2
XTAL1
23
22
24
25
i
s
30
pF
100 kΩ
10 nF
TDA1307
V
DDOSC
+5 V
V
SSOSC
MGB982
Fig.5 External clock input connections.
8
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
Microprocessor interface
THREE-LINE MICROPROCESSOR INTERFACE BUS
The microprocessor interface provides access to virtually
all of the functional blocks in the audio data processing
section. Its destination is two-fold: system constants (such
as input format and sample frequency) as well as system
variables (attenuation, muting, de-emphasis, volume
control data etc.) can be ‘written to’ the respective blocks
(command mode), and continuously collected stereo peak
data ‘read from’ the peak detection block (peak request).
The system settings are stored in the TDA1307 in an
internal register file. Peak data is read from the stereo
peak value register.
Communication is realized by a three-line bus, consisting
of the following signals (see Fig.6):
• Clock input CL (pin 39), to be generated by the
microprocessor
• Command/request input RAB (pin 42), by which either
of the two mode commands (RAB = 0) and peak request
(RAB = 1) are invoked
• Bidirectional data line DA (pin 38), which either receives
command data from the microprocessor or outputs peak
data from the peak detection block.
CL and RAB both default HIGH by internal pull-up, DATA
is 3-state (high impedance, pull-up, pull-down).
+
RAB 42
REQUEST/COMMAND
+
COMMAND DATA
DA/ACK 38
PEAK DATA
+
CL 39
CLOCK
MICROPROCESSOR
TDA1307
MGB984
Fig.6 Three-line microprocessor interface bus.
1996 Jan 08
9
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
LOW are accepted; of the remaining set of addresses, only
four have meaning (see section “Organization and
programming of the internal register file”). The command
input receiver is provided with a built-in protection against
erroneous command transfer due to spikes, by a 2-bit
debounce mechanism on lines DA and CL. The
waveforms on these lines are sampled by the receiver at
the internal system clock rate 256fs. A state transition on
DA or CL is accepted only when the new state perseveres
for two consecutive sampled waveform instants.
INITIALIZATION OF THE BUS RECEIVER
The microprocessor interface section is initialized
automatically by the power-on reset function, POR
(pin 20). A LOW input on POR will initiate the reset
procedure, which encompasses a functional reset plus
setting of the initial states of the control words in the
command register file. A wait time of at least one audio
sample time after a LOW-to-HIGH transition of POR must
be observed before communication can successfully be
established between the TDA1307 and the
microprocessor. In addition to the POR function, a
software reset function issued from the microprocessor is
provided (see section “Organization and programming of
the internal register file”), which has the sole function of
reinstating the initial values of the microprocessor control
register. More information on initializing the TDA1307 can
be found under “Application Information”.
ORGANIZATION AND PROGRAMMING OF THE INTERNAL
REGISTER FILE
Command data received from the microprocessor is
stored in an internal register file (see Table 2), which is
organized as a page of 10 registers, each containing a
4-bit command data word (D3 to D0). Access to the words
in the register file involves two controls: selection of the
address of a set of registers (by means of A3, A2,
A1 and A0) and setting the number of the bank in which
the desired register is located (by means of the ‘bank bits’
B0 and B1). First the desired bank is selected by
programming the command word at address 0000
(supplying the bank bits plus refreshing bits ATT and DIM).
A subsequent addressing (one of three addresses, 1H, 4H
and 6H) will yield access to the register corresponding to
the last set bank.
COMMAND PROTOCOL
The protocol for writing data to the TDA1307 is illustrated
in Fig.7. The command mode is invoked by forcing RAB
LOW. A unit command is given in the form of an 8-bit burst
on the DA line, clocked on the rising edge of CL.
The command consists of 4 address bits followed by
4 control data bits (both MSB first). A next command may
be immediately issued while keeping RAB forced LOW.
Only commands for which the MSB of the address bits is
t
DRW
t
t
CKH
CKL
RAB
CL
1
8
DA (TDA1307)
t
DSM
t
DHM
A3
A2
A1
A1
A0
D3
D3
D2
D2
D1
D1
D0
D0
DA (µP)
A3
A2
A0
DA
MGB995
t
Fig.7 Microprocessor command protocol.
10
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
Table 2 Microprocessor control register file
ADDRESS
BANK
B0 B1
D3
D2
D1
D0
INITIAL STATE
A3 A2 A1 A0
0
0
0
0
0
0
0
1
X
0
1
1
0
1
1
0
1
1
X
1
0
1
1
0
1
1
0
1
BANK B0
FCON
FSS7
FSS3
DCEN
FN7
BANK B1
DIT
ATT
DIM
0 0 1 1
0 0 0 0
0 0 1 0
1 0 0 0
0 1 1 1
0 0 0 0
1 1 0 1
0 0 0 0
0 0 0 0
1 0 0 0
FSS9
FSS5
FSS1
FN9
FSS8
FSS4
FSS0
FN8
FSS6
FSS2
DCSH
FN6
0
0
1
1
0
1
0
0
FN5
FN4
FN3
FN2
FN1
FN0
DEMC1
INS1
DEMC0
INS0
RES0
FS1
RES1
FS0
RES2
NS
RST
STBY
Following is a list of the programming values for the
DIT
various control words in the register file. Information on the
meaning of the different controls can be found under the
sections covering the corresponding signal processing
blocks (see sections “Multiple format input interface” to
“Third and fourth order noise shaping”).
Dither control bit: logic 1 to activate dither addition, logic 0
deactivates.
FSS9 to FSS0
Fade function 10-bit control value to program fade speed,
in number of samples per fade step.
BANK B0, BANK B1
Programming of the bank bits is given in Table 2. The bank
bits can be changed by addressing register location 0000.
Subsequent addressing will result in access of locations
according to the last selected bank.
DCEN
DC-filter enable bit: logic 1 enables subtraction of the
DC-level from the input signal, logic 0 disables.
ATT
DCSH
Attenuation control bit: logic 1 to activate −12 dB
attenuation, logic 0 to deactivate. As the attenuate control
bit shares a control word with the bank bits, ATT has to be
refreshed each time a new bank is selected.
DC-filter sample or hold control bit: when DCSH = 0 the
DC-level of the input signal is continuously evaluated.
When DCSH = 1 the once acquired DC value, to be
subtracted from the input signal, is held constant.
DIM
FN9 to FN0
Digital mute control bit: logic 1 to activate mute, logic 0 to
deactivate. An active digital mute will override the
attenuation function. As with ATT, DIM needs to be
refreshed with each change in bank selection.
Fade function 10-bit control value to program volume level.
DEMC1, DEMC0
De-emphasis function enable and fs selection bits.
FCON
Fade function control bit: logic 1 to activate the fade
function, logic 0 to deactivate.
1996 Jan 08
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Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
Table 3 De-emphasis mode programming
RST
Software reset function. When RST = 1 the contents of the
microprocessor control registers will immediately be
preset to their initial values as shown in Table 2. As part of
this reset action, bit RST is automatically returned to its
initial state 0, that being normal operation.
DEMC1
DEMC0
DE-EMPHASIS FUNCTION
0
0
1
1
0
1
0
1
de-emphasis disabled
de-emphasis for fs = 32.0 kHz
de-emphasis for fs = 44.1 kHz
de-emphasis for fs = 48.0 kHz
STBY
Table 4 Input format programming
Standby mode control bit. When STBY = 1 the standby
mode will be initiated (explained under the section treating
the Digital Output block). STBY = 0 for normal activity.
INS1
INS0
INPUT FORMAT
I2S up to 20 bits
0
0
1
1
0
1
0
1
Sony format 16 bits
Sony format 18 bits
Sony format 20 bits
PEAK DATA OUTPUT PROTOCOL
The peak data read-out protocol is illustrated in Fig.8.
A peak request is performed by releasing RAB (which will
be pulled HIGH by TDA1307) while CL = HIGH, and
maintaining RAB = 1 throughout the peak data
Table 5 Sample frequency indication programming
transmission. TDA1307 will acknowledge the peak request
by returning a LOW state on the DA line. Upon this peak
acknowledge, the microprocessor may commence
collecting data from the internal peak data output register
(16-bit Left, 16-bit Right channel peak data) by sending a
clock onto the CL line. The contents of the peak data
output register will not change during the peak request.
The first peak bit, the MSB of the Left channel peak value,
is output upon the first LOW-to-HIGH transition of CL.
To access Right channel peak value, all 16 bits of channel
Left have to be read out, after which up to 16 bits of Right
channel peak data may be read out. The peak data read
out procedure may be aborted at any instant by returning
RAB LOW, marking the end of the peak request: the
internal peak register will be reset and the peak detector
will start collecting new peak data and transferring this to
the peak data output register.
DOBM SAMPLE
FREQUENCY INDICATION
FS1
FS0
0
0
1
1
0
1
0
1
fs = 44.1 kHz
fs = 48.0 kHz
no meaning
fs = 32.0 kHz
RES2 to RES0
These are reserved locations and have no functional
meaning in the TDA1307.
INS1, INS0
Input format selection control bits.
FS1, FS0
Sample frequency indication control bits for the digital
output section.
NS
Control bit for Noise Shaper section. When NS = 0, 3rd
order noise shaping is selected; when NS = 1, 4th order
noise shaping is selected.
1996 Jan 08
12
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
t
DWR
READ PEAK DATA
RAB
t
t
DHP
DSP
CL
DA (TDA1307)
DA (µP)
1
Q1
Q1
Q2
Q2
Q3
Q31 Q32
Q3
Q31 Q32
DA
MGB996
Fig.8 Peak data output protocol.
The reset action is flagged on the RESYNC (pin 19)
output, which may be optionally used for muting or related
purposes. RESYNC becomes HIGH the instant a reset is
initiated, and remains in that state for at least one sample
period (1/fs).
Multiple format input interface
Data input to the TDA1307 is accepted in four possible
formats, I2S (with word lengths of up to 20 bits), and Sony
formats of word lengths 16, 18 and 20-bit. The general
appearance of the allowed formats is given in Fig.9. The
selection of a format is achieved through programming of
the appropriate bits in the microprocessor register file.
Characteristic timing for the input interface is given in the
diagram of Fig.10.
ERROR FLAG INPUT EFAB
The error flag input EFAB (pin 4) is intended as request
line from the system decoder to the digital filter to indicate
erroneous audio samples requiring concealment.
A detected HIGH on input EFAB will be relayed by the
input interface block to the error concealment block, where
the samples flagged as erroneous will be processed
accordingly.
SYNCHRONIZATION
For correct data input to reach the central controller of
TDA1307, synchronization needs to be achieved to the
incoming 1fs I2S or Sony format input signals.
The incoming WS signal is sampled to detect whether its
phase transitions occur at the correct synchronous timing
instants. This sampling occurs at the TDA1307 internal
clock rate, 256fs. After one phase transition of WS, the
next is expected after a fixed delay, otherwise the
condition is regarded as out-of-lock and a reset is
performed, this operation is repeated until synchronization
is achieved. To allow for slight disturbances causing
unnecessary frequent resets, the critical WS transitions
are expected within a tolerance window (−4 to +4 periods
of the 256fs internal sampling clock instants).
1996 Jan 08
13
g
1
2
n
32
1
2
n
32
1
2
SCK
EFAB
WS
LEFT
RIGHT
MSB B2
MSB B2
MSB
SD
B2
SAMPLE IN RIGHT
SAMPLE IN LEFT
SAMPLE IN LEFT
2
INPUT FORMAT I S
1
2
3
4
5
6
7
8
9
10
23
24
1
2
3
4
5
6
7
8
9
10
23
24
SCK
WS
SD
LEFT
RIGHT
MSB B2
B15 LSB
MSB B2
B15 LSB
SAMPLE IN LEFT
SAMPLE IN RIGHT
INPUT FORMAT SONY 16-BIT
SD
SD
MSB B2
B3
B4
B17 LSB
MSB B2
B3
B4
B17 LSB
SAMPLE IN LEFT
SAMPLE IN RIGHT
INPUT FORMAT SONY 18-BIT
MSB B2
B3
B4
B5 B6
B19 LSB
MSB B2
B3
B4
B5
B6
B19 LSB
SAMPLE IN LEFT
SAMPLE IN RIGHT
MGB999
INPUT FORMAT SONY 20-BIT
Fig.9 Input formats.
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
RIGHT
LEFT
RIGHT
LEFT
WS
t
SU;WS
t
t
t
t
t
HD;WS
r
HB
f
LB
SCK
t
t
HD;DAT
SU;DAT
SD
MGB998
Fig.10 Typical I2S-bus data waveforms.
initiated over the maximum interpolation interval of eight
sampling instants.
Error concealment, interpolation and muting
The error concealment functional block performs three
functions:
ATTENUATION
1. interpolation of up to eight consecutive erroneous
audio samples flagged as such by input EFAB
The concealment block incorporates a digital −12 dB
attenuation function intended to be used in program
search or other player actions that may generate audible
transitional effects such as loud clicks. The attenuate
function is activated by means of bit ATT in the
microprocessor register file. Setting this bit to logic 1
causes the next audio sample (attenuate never takes
action on incomplete samples) to be attenuated with
immediate effect (the validity flag of the digital audio output
DOBM is set).
2. attenuation
3. muting of incoming audio, both the latter if so activated
by means of the microprocessor registers.
Furthermore, as these functions constitute error
processing functions, operation of any of these functions is
reported to the digital output DOBM by setting the validity
flag.
EIGHT-SAMPLE INTERPOLATION
The interpolation facility is called upon when an attenuate
command is given while the incoming data is flagged as
invalid by EFAB. If no more than eight samples in
succession are invalid, attenuate may take immediate
effect (this causes the output value to ramp linearly to the
final attenuated level). If nine or more samples in a row are
flagged erroneous, attenuation is postponed and the last
good sample held, until the next good sample becomes
available. Upon that instant, the output ramps linearly,
over the maximum interpolation time span, to the
Incoming audio samples may be visualized as entering a
memory pipeline, nine audio sample instants in depth,
upon entering the error concealment block. Any audio
samples marked as erroneous by the flag input EFAB will
be reconstructed by linear approximation from the values
of the adjacent correct samples (the last correct sample
still available, and the next correct sample). The linear
interpolation is started as soon as a correct sample
becomes available within nine sampling instants. Should a
flagged erroneous condition persevere for over eight
sampling instants, then the last correct sample will be held
for as long as necessary, i.e. until the next correct sample
enters the pipeline. The linear approximation is then
attenuated first correct sample. Releasing attenuate (bit
ATT reset to 0) always has immediate effect (i.e. the next
complete audio sample will pass unattenuated).
1996 Jan 08
15
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
• the Validity flag as output by the error concealment block
MUTING
• subcode information, as acquired by input via pins
SBDA (pin 6) and SBCL (pin 5)
The digital mute of the error concealment block
immediately (i.e. on the next whole audio sample) sets the
input to the digital filter to all zeros, regardless of any other
current action in the error concealment block. The digital
mute function is activated by means of bit DIM in the
microprocessor register file. Setting this bit to logic 1
causes the next audio sample to be muted (the validity flag
of the digital audio output DOBM is set).
• sampling frequency information as set by means of
bits FS1 and FS0 in the microprocessor register file.
As the digital output function is not always required, and
can give rise to interference problems in high-quality audio
conversion systems, the DOBM output can be switched on
or off by means of pin DSTB (digital output standby, 13).
Leaving DSTB open-circuit will cause it to pull HIGH and
deactivate the DOBM output; tying DSTB LOW enables
the digital output function.
Releasing the digital mute function (resetting bit DIM to 0)
will cause the output of the error concealment block to
approach the unaffected audio sample value by linear
approximation, on the condition that the mute action
spanned at least 8 consecutive audio samples. If there are
samples in error at the time of releasing mute, the release
action is postponed until good data becomes available,
after which the linear ramp can be made over the
maximum interpolation time span.
The programming of bits FS1 and FS0 is specified in
Table 5 under section “Microprocessor interface”. The
DOBM block of TDA1307 translates the settings of these
bits to the appropriate corresponding information in the
digital audio output sequence (as specified by IEC 958).
The inputs SBDA (subcode data, 6) and SBCL (subcode
clock, 5) allow for the merging of subcode data into the
output DOBM signal. The input sequence via these inputs
is defined as 10-bit burst words, arranged as illustrated in
Fig.11; the bit nomenclature corresponds to that used in
the IEC standard 958. Both subcode data and clock
signals are normally supplied by the decoder of the digital
audio system (e.g. SAA7310).
Digital output (DOBM)
The DOBM block constructs a biphase modulated digital
audio output signal which complies to the IEC standard
958, to be used as a digital transmission link between
digital audio systems. A variety of inputs are combined,
arranged and modulated to finally form the output
biphase-mark sequence. The inputs are the following:
For set-up and hold timing of the SBDA and SBCL inputs,
restrictions identical to the audio data inputs are valid.
• left and right audio data, word length 20-bit, as delivered
by the error concealment block
Q-CHANNEL PARITY
CHECK FLAG
(0 = FAIL)
SUBCODING
ERROR FLAG
SYNC (active LOW)
SBDA
P-BIT
W
V
U
T
S
R
Q
P-BIT
SBCL
MGB997
2.8224 MHz (typ.) BURST CLOCK
Fig.11 Format of subcode data input.
16
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
degradations in processing the mentioned types of
Digital silence detection
excitations. To dimension a high-fidelity digital filter, a
balance must be established between filter steepness and
overload susceptibility.
The TDA1307 is designed to detect digital silence
conditions in channels left and right, separately, and report
this via two separate output pins, one for each channel,
DSL (pin 11) and DSR (pin 12). This function is
implemented to allow for external manipulation of the
audio signal upon absence of program material, such as
muting or recorder control. The TDA1307 itself does not
influence the audio signal as a result of digital silence; the
sole function of this block is detection, and any further
treatment must be accomplished externally.
The oversampling digital filter function in the TDA1307 is
designed, in combination with the noise shaper, to deliver
the highest fidelity in signal reproduction possible. Not only
are stop-band suppression and pass-band ripple
parameters to the design, but also the prevention of
detrimental artifacts of too extreme filtering: impulse and
high-level overload responses. The outcome is a patented
design excelling in natural response to most conceivable
audio stimuli. It is realized as a series of three half-band
filters, each oversampling by a ratio of two, thus achieving
an eight times oversampled and interpolated data output
to be input to the noise shaper. Each stage has a finite
impulse response with symmetrical coefficients, which
makes for a linear phase response. Filter stages 1, 2 and
3 incorporate 119, 19 and 11 delay taps respectively.
To maintain an output accuracy of 20 bits, an internal data
path word length of 39 bits is used to supply the required
headroom in multiplications. Requantization back to 20-bit
word length is performed by noise shaping (thus effectively
preventing rounding errors in so far as they have effect in
the audio frequency band), at the output of each filter
section.
An active LOW output is produced at these pins if the
corresponding channel carries either all zeroes for at least
8820 consecutive audio samples
(200 ms for fs = 44.1 kHz).
The digital silence detection block receives its left and right
audio data from the error concealment block (implying that
a digital mute action will produce detection of a digital
silence condition), and passes it unaffected to the next
signal processing stage, the de-emphasis block.
De-emphasis filter
The TDA1307 incorporates selectable digital de-emphasis
filters, dimensioned to produce, with extreme accuracy,
the de-emphasis frequency characteristics for each of the
three possible sample rates 32, 44.1 and 48 kHz. As a
20-bit dynamic range is maintained throughout the filter,
considerable margin is kept with respect to the normal CD
resolution of 16-bit i.e. the digital de-emphasis of TDA1307
is a truly valid alternative to analog de-emphasis in
high-performance digital audio systems.
The successive half-band filter stages are, for efficiency,
distributed over the audio data processing path:
DC-filtering, peak value reading and volume control are
performed between stages 1 and 2 (the 2fs domain).
DC-cancelling filter
A mechanism for optionally eliminating potential DC
content of incoming audio data is implemented in the
TDA1307 for three main reasons. Most importantly
because it is called for by the implementation of volume
control in the TDA1307. An audio signal that is to be
subjected to volume control (multiplication by a controlled
attenuation factor) should be free of offset, otherwise the
controlled multiplication will produce the undesired side
effect of modulating the average DC content. The second
reason is supplied by the implementation of audio peak
data read-out in the TDA1307. As the peak value is
obtained from the absolute value of the audio data
referenced to zero DC level, its accuracy is impaired by the
presence of residual DC information, progressively so for
lower audio levels. The third reason is brought about by
application of the noise shaper. To optimize the dynamic
behaviour of the noise shaper especially for low-level
signals, it is supplied a predefined offset, sometimes
referred to as DC dither. Taking no precautions against DC
Selection of the de-emphasis filters is performed via the
microprocessor interface, bits DEMC1 and DEMC0, for
which the programming is given in Table 3.
Oversampling digital filter
The oversampling digital filter in the digital audio
reconstruction system is of paramount influence to the
fidelity of signal reproduction. Not only must the filter
deliver a desired stop-band suppression while sustaining a
certain tolerated pass-band ripple, but it must also be
capable of faithfully reproducing signals of high energy
content, such as signals of high level and frequency,
square wave-type signals and impulse-like signals (all of
these examples have their counterparts in actual music
program material). Filters optimized only towards
pass-band ripple and stop-band suppression are capable
of entering states of overload because of the clustered
energy content of these signals, thus introducing audible
1996 Jan 08
17
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
content of the source audio data may render the DC dither
potentially ineffective.
mainly in digital volume unit measurement and display,
and in automatic recording level control. The peak level
measurement of the TDA1307 occurs with a resolution of
16-bit, providing a dynamic range amply suitable for all
practical applications.
In applications where the DC content of the audio
information may be expected, application of the selectable
DC filter may be opted for. It is implemented as a first-order
high-pass filter with a corner frequency of 2 Hz. Control of
the DC filter is achieved by accessing the appropriate bits
DCEN (DC filter enable) and DCSH (DC filter sample or
hold) in the microprocessor register file. The principle of
operation is illustrated in Fig.12. The output of the DC filter,
referred to in the diagram as ‘audio output’ always equals
the audio input subtracted by the output of the low-pass
branch. Depending on the control bit DCSH, this
subtraction value is either the last value held constant or
a value continuously adapting to incoming DC content.
The DC filter is effectively switched on or off via control bit
DCEN, which selects the input of the low-pass section
either to be the audio input data (the output of the low-pass
section will settle to the low frequency content of the audio
data so that the filter is on) or a preset value of zero
(low-pass output will settle to zero meaning ‘filter off’).
The constant mode is implemented to provide a mode in
which a stable subtraction value is guaranteed; in this
mode however the high-pass function is inhibited so there
is no adaptation to changes in the DC content of the
incoming source information.
The output of the peak detection block is a register of two
16-bit words, one for each channel, representing the
absolute value of the accumulated peak value, accessible
via the microprocessor interface. The peak detection block
continuously monitors the audio information arriving from
the DC-cancelling filter, comparing its absolute value to
the value currently stored in the peak register. Any new
value greater than the currently held peak value will cause
the register to assume the new, greater value. Upon a
peak request (for which the protocol is described in section
“Peak data output protocol”), the contents of the peak
register are transferred to the microprocessor interface.
After a read action, the peak register will be reset, and the
collection of new peak data started.
The peak detection block receives data that has been
processed by the first half-band stage of the oversampling
interpolating digital filter (in the 2fs domain, but the peak
detection ‘samples’ at 1fs for efficiency). This means that
the scaling applied in this first half-band stage is noticeable
in the measured peak value. The frequency-independent
attenuation factor of the first half-band filter equals
0.175 dB - this results in a possible range for the output
peak value of 0 to 32114. When the audio signal may be
expected to carry DC content, use of the DC cancelling
filter of TDA1307 is recommended, to ensure correct and
accurate peak detection.
Peak detection
The TDA1307 provides a convenient way to monitor the
peak value of the audio data, for left and right channels
individually, by way of read-out via the microprocessor
interface. Peak value monitoring has its applications
audio input
audio output
+
+
from first
half-band stage
to peak
detection block
−
DCEN = 1
DCEN = 0
DCSH = 0
LPF
= 2 Hz
f
o
zero
T
DCSH = 1
MGB994
Fig.12 Schematic diagram of the DC filter.
18
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
audio input
from peak
audio output
to second
detection block
half-band stage
controlled
multiplication
factor
18
FN
(desired level)
10
VOLUME
CONTROL
ALGORITHM
from
FSS
10
microprocessor
register file
(fade speed)
FCON
MGB985
Fig.13 Schematic diagram of the volume control block.
calculates and applies intermediate volume levels
Fade function and volume control
according to an exponential approach curve. The speed at
which the approach curve progresses is determined by the
value of the fade speed control word, FSS. FSS + 2 is the
amount of time delay applied, in units of audio sample
instants, before a next value on the exponential curve is
calculated and applied.
One of the main features of TDA1307 is a patented,
advanced digital volume control with inherent fading
function, exhibiting an accuracy and smoothness
unsurpassed in presently available digital filters. Only the
desired volume and the fade speed need to be instructed
to the TDA1307, which can be realized in a single
instruction via the microprocessor interface. The volume
control function then autonomously performs automatic
fade in or fade out to the desired volume by a natural,
exponential approach. It allows for volume control to an
accuracy of 0.1 dB over the range from 0 dB of full scale to
beyond −100 dB. The speed of approach can be set over
a wide range, varying from less than one second to over
23 seconds for a complete fade. Furthermore the fade
algorithm manages the additional fading resolution, in
excess of the 0.1 dB available for the volume desired level,
needed to ensure gradual changes in volume at all times.
Figure 13 illustrates the volume control block.
The total duration of an exponential fade operation is the
product of the desired amount of volume change FN (in
LSBs of the 10-bit control word) and the amount of delay
per fade step FSS (in LSB times seconds), expressed as
follows:
(FSS + 2)
tfade, exp, total = ∆FN ×
,
----------------------------
fs
where fs is the base-band sampling frequency.
Thus the longest fade time achievable, occurring in the
event of maximum desired volume change ∆FN = 1023,
slowest speed setting FSS = 1023, and in the event that
fs = 44.1 kHz, is 23.7 seconds.
Three data entities in the microprocessor register file
pertain to the volume control block: a 10-bit control value
for the desired volume (bits FN9 to FN0), a 10-bit control
value for the fade speed (bits FSS9 to FSS0), and the fade
function override bit, FCON. The volume control word
ranges from 0 (representing a desired volume level or
0 dB) to 1023 (representing maximum desired volume
level of zero or −∞ dB). For values 1 to 1023, an LSB
change of the volume control word represents 0.1 dB
change of volume level. In changing from one volume level
to the next desired volume level, the volume control block
To smooth out fast volume changes however, the
TDA1307 fade function adds extra resolution to the
volume control by gradually changing from one
exponential step to the next, by a linear transition.
Whereas the 10-bit FN-value could not accomplish
discrete attenuation steps finer than 0.1 dB, the linear
transitional approach enhances volume change resolution
to 15-bit. The volume level therefore never changes faster
than one LSB of the 15-bit attenuation factor per audio
sample. As soon as the linear transition reaches the value
1996 Jan 08
19
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
determined by the exponential approach, the attenuation
value remains stable until the next exponential value is
due, which will again initially be approached linearly. For
exponential fade speeds higher than the linear approach
can follow, the approach remains linear unless the
exponential approach curve is intersected. For fast volume
decrease, the start of the approach will be linear, whereas
for a fast volume increase, the course of the fade approach
will be exponential at first, then saturating to linear.
Third and fourth order noise shaping
The noise shaper constitutes the final audio processing
stage of TDA1307, which takes the eight times
oversampled and interpolated audio data stream from the
digital filter as input, and by extreme oversampling and
1-bit end quantization processes the signal so that it can
be converted to analog by a one-bit digital-to-analog
converter. The order of the noise shaper is selectable,
between 3rd and 4th order, by means of the register file bit
NS (NS = 0: 3rd order, NS = 1: 4th order). Together with
the final oversampling ratio, the noise shaper order
determines the dynamic range (or accuracy) that the noise
shaper can achieve (the oversampling ratio will depend on
the system clock frequency and application mode used).
Table 6 gives the dynamic range of the noise shaper as a
function of these two parameters.
The fastest fade speed, for large volume changes, is
therefore determined by the linear approach. For a
maximum volume change at maximum speed, follows a
fade time of (215 − 1)/44100 = 0.74 seconds.
For immediate return to the maximum volume level without
altering the volume and fade speed settings, bit FCON in
the register file can be used. With this bit set to 1, the fade
function is active and operates as described above.
Resetting FCON to 0 will immediately deactivate the fade
function, that is, return the volume level to maximum at the
start of the next audio sample. Changing state of FCON
from 0 to 1 will cause a fade according to the current
settings of volume and speed control words FN and FSS.
Figures 15 and 16 show noise spectral density simulations
of the third and fourth order noise shaper respectively, with
a stimulus frequency of 1 kHz at a level of −10 dBfs, for
192 × 44.1 kHz oversampling. From the slope of the
shaped noise spectrum outside the audio band, the order
of noise shaping is apparent. It is important to note that, in
contrast to normal fourth-order noise shaping, where an
audio post-filter of equal order would be needed to
compensate the slope of the quantization noise, the
fourth-order noise shaper of the TDA1307 actually only
needs third order post-filtering to obtain the same amount
of stop-band suppression as with third order. The noise
density of the fourth order noise shaper starts at a lower
level for low frequencies, and only slightly exceeds the
third-order curve in the 200 to 300 kHz region.
In Fig.14, a few fading examples illustrate the operation of
the TDA1307 advanced digital volume control.
Dither and scaling
Prior to input to the noise shaper, final preprocessing is
performed upon the eight times oversampled and
interpolated audio data stream in the form of scaling and
dither addition. The fixed scaling factor, a
frequency-independent attenuation of 3 dB, is applied to
the signal in order to provide the noise shaper with
sufficient headroom. The application of dither is optional,
selectable by means of bit DIT in the microprocessor
register file.
With DIT set to 1, fixed dither levels of value 2−6 + 2−5 and
2−6 − 2−5 are added alternately to the audio signal, at an
alternation rate of 4fs. This amounts to a combination of an
AC dither signal of frequency 4fs and amplitude −24 dB of
full-scale, with a DC dither (offset) of 3.125% of full-scale
peak amplitude. With DIT set to 0, no dithering, AC or DC,
is performed.
Although the addition of dither is made selectable in the
TDA1307, it is generally recommended for use always, as
dither is essential to the accurate conversion of low-level
signals and reproduction of silence conditions by
noise-shaping circuits.
1996 Jan 08
20
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
max
volume
level
(FSS + 2)/f
s
0.1 dB
1/f
s
0
MGB991
A
B
C
D
E
F
G
time
A: Fade out to zero (FN = 0).
B: Fade in to maximum volume (FN = 1023).
C: Fast volume decrease resulting in initial linear regulation.
D: Slow volume decrease predominantly exponential.
E: Volume regulation overridden by resetting FCON to 0.
F: FN = 0, FSS = 0, FCON to 1 causes fastest maximum fade with linear regulation.
G: Medium speed volume increase starts exponential, ends linear.
Fig.14 Volume control examples.
Table 6 Noise shaper dynamic range
OVERSAMPLING/ORDER
3rd ORDER
4th ORDER
128fs
192fs
105 dB
117 dB
118 dB
134 dB
1996 Jan 08
21
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
MGB992
0
A
o
(dBf )
s
−50
−100
−150
−200
2
3
4
5
6
10
10
10
10
10
10
log frequency (Hz)
Fig.15 Noise shaper output spectrum (N = 3; 192fs).
MGB993
0
A
o
(dBf )
s
−50
−100
−150
−200
2
3
4
5
6
10
10
10
10
10
10
log frequency (Hz)
Fig.16 Noise shaper output spectrum (N = 4; 192fs).
22
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
supply voltages
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
V
V
(pins 8, 21, 24, 29, 32 and 41)
VI
maximum input voltage
note 1
−0.5
VDD + 0.5
IIK
DC clamp input diode current
VI < −0.5 V or
VI > VDD + 0.5 V
−
±10
mA
mA
mA
mA
mA
IOK
IO
DD, ISS
DC output clamp diode current;
(output type 4 mA)
V
O < −0.5 V or
−
−
−
−
±20
±20
±50
50
VO > VDD + 0.5 V
DC output source or sink current;
(output type 4 mA)
−0.5 V < VO < VDD + 0.5 V
I
DC VDD or GND current per
supply pin
PO, cell
power dissipation per output
(type 4 mA)
Tstg
Tamb
Ves
storage temperature
−55
+150
+70
°C
°C
V
operating ambient temperature
electrostatic handling
−20
100 pF; 1.5 kΩ
−2000
+2000
Note
1. Input voltage should not exceed 6.5 V.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
39
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
K/W
1996 Jan 08
23
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = −20 to +70 °C and oscillator frequency 33.8688 MHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDC1,2,3
supply voltage
4.5
5.0
5.5
V
(pins 8, 21 and 41)
VDDOSC
VDDAR
VDDAL
Vdiff
supply voltage (pin 24)
supply voltage (pin 32)
supply voltage (pin 29)
4.5
4.5
4.5
−
5.0
5.0
5.0
−
5.5
5.5
5.5
tbf
V
V
V
V
maximum difference between
supplies
IDDC1,2,3
supply current
VDD = 5 V
−
75
−
mA
(pins 8, 21 and 41)
IDDOSC
IDDAR
IDDAL
supply current (pin 24)
supply current (pin 32)
supply current (pin 29)
VDD = 5 V
VDD = 5 V
VDD = 5 V
−
−
−
2
2
1
−
−
−
mA
mA
mA
Inputs
CLC1, CLC2, EFAB, SCK, WS, SD, SBCL, DA, SBDA, CDCC, TEST1 AND TEST2
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
input resistance
note 1
note 1
note 2
note 3
−
−
−
−
−
−
0.3VDD
−
V
0.7VDD
V
−1
17
−
+1
µA
kΩ
pF
RI
134
10
CI
input capacitance
CL, RAB, POR, DSTB AND MODE
VIL
VIH
RI
LOW level input voltage
HIGH level input voltage
input resistance
note 1
note 1
note 3
−
−
−
−
−
0.2VDD
−
V
0.8VDD
V
17
134
10
kΩ
pF
CI
input capacitance
−
Outputs
CDEC AND CMIC (TYPE 4 MA)
VOL
VOH
CL
LOW level output voltage
IOL = 4 mA
−
−
−
−
0.5
−
V
HIGH level output voltage
load capacitance
IOH = −4 mA
V
DD−0.5
V
−
30
pF
CDAC (TYPE TBF MA)
VOL
VOH
CL
LOW level output voltage
IOL = 8 mA
−
V
−
−
−
−
0.5
−
V
HIGH level output voltage
load capacitance
IOH = −8 mA
DD−0.5
V
100
pF
1996 Jan 08
24
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DOR, DOL, NDOR AND NDOL (TYPE CUSTOM MA)
VOL
VOH
CL
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 2 mA
−
V
−
−
−
−
0.5
V
IOH = −2 mA
DD−0.5
−
V
100
pF
DOBM (TYPE 12 MA)
VOL
VOH
CL
LOW level output voltage
IOL = 12 mA
−
V
−
−
−
−
0.5
−
V
HIGH level output voltage
load capacitance
IOH = −12 mA
DD−0.5
DD−0.5
DD−0.5
V
50
pF
DSR, DSL AND RESYNC (TYPE 2 MA)
VOL
VOH
CL
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 2 mA
−
V
−
−
−
−
0.5
−
V
IOH = −2 mA
V
50
pF
DA (TYPE 2 MA)
VOL
VOH
CL
LOW level output voltage
HIGH level output voltage
load capacitance
IOL = 2 mA
−
V
−
−
−
−
−
0.5
−
V
IOH = −2 mA
V
50
134
pF
kΩ
RLint
internal load resistance
17
Crystal oscillator
INPUT: XTAL1
gm
Gv
ILI
mutual conductance
f = 2 MHz
Gv = gm × RO
note 2
−
0.4
72
−
−
mS
small-signal voltage gain
input leakage current
input capacitance
−
−
−1
−
+1
−
µA
CI
10
pF
Timing
fXTAL
operating frequency
33.8688
MHz
SCK, WS, DATA, SBDA, SBCL AND EFAB (SEE FIGS 8 AND 9)
fCL
SBCL clock frequency
SCK clock frequency
WS clock frequency
clock time LOW
clock time HIGH
input rise time
note 3
−
−
−
64fs
64fs
−
Hz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
fSCK
fWS
−
−
fXTAL/768
tLB
110
110
−
−
−
−
−
−
−
−
−
−
tHB
−
tr
20
20
−
tf
input fall time
−
tSU:DAT
tHD:DAT
tSU:WS
tHD:WS
data set-up time
data hold time
20
0
−
WS set-up time
WS hold time
20
0
−
−
1996 Jan 08
25
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
MICROCONTROLLER INTERFACE (SEE FIGS 6 AND 7)
fCK
CL input clock frequency
input clock time LOW
input clock time HIGH
−
−
−
−
−
46fs
kHz
tCKL
tCKH
tDSM
2.0
2.0
1.0
−
−
−
µs
µs
µs
microprocessor data set-up
time after CL LOW-to-HIGH
transition
tDHM
tDSP
tDHP
microprocessor data hold time
after CL LOW-to-HIGH transition
2.0
2.0
2.0
−
−
−
−
−
−
µs
µs
µs
peak data set-up time after CL
LOW-to-HIGH transition
peak data hold time after CL
LOW-to-HIGH transition
tdRW
tdWR
delay to write after read
delay to read after write
2.0
2.0
−
−
−
−
µs
µs
DOBM CIRCUIT
fDOBM
tr
data output frequency
output rise time
output fall time
−
128fs
−
Hz
ns
ns
ns
ns
CL = 50 pF
CL = 50 pF
−
−
−
−
−
10
10
−
tf
−
tSU;DAT
tHD;DAT
data set-up time
data hold time
40
5
−
CLOCK GENERATOR CIRCUIT (NOTE 4)
fXTAL1
fCDEC
fCMIC
XTAL1 input clock frequency
CDEC output clock frequency
CMIC output clock frequency
slave mode
−
−
−
256fs
256fs
96fs
−
−
−
Hz
Hz
Hz
Notes
1. Minimum VIL, maximum VIH are peak values to allow for transients.
2. II(min) measured at VI = 0 V; II(max) measured at VI = VDD; not valid for pins with pull-up/pull-down resistors.
3. II(min) measured at VI = 0 V (pull-up); II(max) measured at VI = VDD (pull-down); valid for pins with pull-up/pull-down
resistors.
4. Crystal frequency: 33.8688 MHz (768fs), the oscillator circuit oscillates at a frequency that is approximately 0.01%
above the crystal frequency.
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The numbers of the quality specification can be found in the “Quality Reference
Handbook”. This handbook can be ordered using the code 9397 750 00192.
1996 Jan 08
26
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
APPLICATION INFORMATION
Application modes
TDA1307 can be used as a digital reconstruction filter for CD, DCC, DAB and DAT applications. The configuration for
these different applications is given in Table 7.
Table 7 Application modes
BITSTREAM
OUTPUT
MODE
CD
CDCC
CRYSTAL
CLOCK INPUT
SAMPLING FREQUENCY
44.1 kHz
1
0
0
0
768fs
−
192fs
DCC
DAB
DAT
−
−
−
256fs
256fs
256fs
128fs
32.0 or 44.1 or 48.0 kHz
32.0 kHz
128fs
128fs
32.0 or 44.1 or 48.0 kHz
The crystal frequency for TDA1307, when operating in
master mode, is 768fs (fs = 44.1 kHz). TDA1307 can also
operate in slave mode, in which the clock input receives a
clock signal of 256fs (fs = 32.0, 44.1 or 48.0 kHz). In the
latter configuration, no resonator is connected to
TDA1307.
Typical application with TDA1547 Bitstream DAC
The high-quality one-bit audio data stream produced by
the TDA1307 is optimumly converted to analog using the
TDA1547 high-performance bitstream digital-to-analog
converter. The TDA1547 takes the data outputs DOL
(pin 27) and DOR (pin 33) of the TDA1307 as input,
clocked by TDA1307 output CDAC (pin 35), and converts
the digital data to ‘one-bit’ analog values (positive
reference value and negative reference value) through a
differentially configured high-speed, high-accuracy
switched capacitor network.
Basic application
Figures 17 to 20 show the connections for an example of
a complete bitstream reconstruction system, using
TDA1307 together with TDA1547, as implemented in a
demonstration application printed-circuit board. Figure 15
shows the connections pertaining to TDA1307. Both
master and slave operation is possible, by setting of
switches J1 and J2, and by programming the desired
mode and frequency divisions by switch block SW1. Both
test pins of TDA1307 are tied to ground in order to obtain
immunity to crosstalk from the adjacent clock output
CDAC. At pin POR (pin 20), an RC-timing network presets
a typical power-on-reset LOW-time (10 ms for an
instantaneously setting 5 V supply).
This differential application can be further enhanced to a
double-differential application, combining the assertive
data outputs with the complementary data outputs NDOL
(pin 28) and NDOR (pin 34) into a set of two TDA1547s, by
which it is possible to achieve additional noise margin. The
application of Figs 17 to 19 is an example of a differential
application. A schematic diagram of the double differential
mode application is illustrated in Fig.20.
1996 Jan 08
27
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
+5 V DC
100 µF
0 V
C
C
C
DGND
V
V
V
V
V
V
DDC3
SSC1 DDC1 SSC2
21
DDC2 SSC3
16 8
XSYS_IN
CON2
40
20
9
41
47 kΩ
POR
1 µF
100 pF
s
+5 V
XTAL2
CON1
J1
m
23
2
4
1
3
5
7
9
(1)
33.8688 MHz
BIT CLOCK
SCK
2
1
3
4
6
WORD CLOCK
SERIAL DATA
WS
SD
100
kΩ
X1
8
3.3
µH
10
ERROR FLAG EFAB
10
pF
10
kΩ
m
J2
s
XTAL1
22
24
10 kΩ
10
pF
RESYNC
(1)
19
1 nF
10
nF
+5 V
SW1
V
DDOSC
4xR
+5 V
1
2
6
5
CDCC
CLC2
CLC1
DSTB
8
18
17
14
13
C
7
3
4
V
SSOSC
25
7
CDEC_out
CMIC_out
DIG_out
CDEC
CON3
CON4
CON5
47 Ω
TDA1307
47 Ω
SBCL
SBDA
CMIC
5
6
15
10
(from decoder)
TR1
560 Ω
DOBM
TEST1
TEST2
MODE
36
37
26
620
Ω
DSL
11
(to analog output stage
TDA1547 circuit; optional)
12 DSR
4.7 Ω
V
DDAR
32
31
+5 V
C
C
V
NDOR
SSAR
100
µF
34
33
35
27
28
DOR
CDAC
DOL
(to TDA1547 circuit)
V
DDAL
29
30
V
NDOL
SSAL
42
RAB
39
38
CL
DA
MGB990
(to/from microprocessor)
C = 100 nF chip capacitor.
R = 10 kΩ chip resistor.
(1) s = slave mode switch position.
m = master mode switch position.
Fig.17 Basic connections TDA1307.
28
1996 Jan 08
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
34
NDOR
33
DOR
TDA1307
35
27
28
CDAC
DOL
NDOL
IN R
CLK R
CLK L IN L
28 30
3
5
V
V
10 Ω
10 Ω
DGND
SUB
SSD
−5 V
(digital)
1
2
32
C
C
10 Ω
V
DDD
−5 V
(digital)
+5 V
(digital)
31
C
n.c.
n.c.
V
4
6
29
27
10 Ω
V
DDD R
10 Ω
DDD L
+5 V
(digital)
+5 V
(digital)
C
C
1.5 kΩ
V
C
V
V
1.5 kΩ
SSD R
SSD L
−5 V
(digital)
−5 V
(digital)
7
26
3.3
kΩ
3.3
kΩ
C
TDA1547
560 Ω
V
560 Ω
−5 V
ref L
ref R
−5 V
(analog)
8
9
25
(analog)
220
µF
220
µF
3.3
kΩ
3.3
kΩ
C
C
AGND
DAC L
AGND
DAC R
24
23
22
− DAC R
+ DAC R
AGND R
n.c.
− DAC L
10
11
+ DAC L
AGND L
12
13
14
15
16
21
20
19
18
17
to analog
output stage
to analog
output stage
n.c.
+ OUT R
− OUT R
+ OUT L
− OUT L
4.7 Ω
V
V
4.7 Ω
+5 V
SSA
DDA
−5 V
(analog)
(analog)
C
C
+5 V DC
(digital)
+5 V DC
(analog)
100
µF
100
µF
DGND
AGND
0V
0V
100
µF
100
µF
−5 V DC
(digital)
−5 V DC
(analog)
MGB988
C = 100 nF chip capacitor.
Fig.18 Connections for TDA1307.
29
1996 Jan 08
w
56 pF
220 pF
10 kΩ
13 kΩ
100 µH
2.61 kΩ
2.2 nF
CON6
100 µF
10 kΩ
4.7 Ω
AUDIO
OUTPUT
LEFT
1 kΩ
1.62 kΩ
220 pF
1/2 IC3
3.3 kΩ
1.5
1/2 IC3
560 pF
kΩ
J5
820
pF
13 kΩ
3.3
kΩ
470
Ω
3.3
nF
DSL
KILL
(optional)
33
nF
(optional from TDA1307)
23
22
21
19
18
+15 V DC
DE–EMPHASIS
(optional)
J3
4.7
Ω
4.7
Ω
33
µF
33
µF
C
C
C
C
ANALOG OUTPUT SECTION
TDA1547
IC3
IC4
33
µF
33
µF
DE–EMPHASIS
(optional from
decoder)
4.7
Ω
4.7
Ω
56 pF
−15 V DC
10
11
12
14
15
10 kΩ
100 µH
2.2 nF
1.62 kΩ
CON7
100 µF
10 kΩ
4.7 Ω
AUDIO
1 kΩ
2.61 kΩ
OUTPUT
RIGHT
820
pF
13 kΩ
1/2 IC4
3.3 kΩ
1.5
kΩ
1/2 IC4
560 pF
J6
220 pF
3.3
470
Ω
3.3
nF
kΩ
13 kΩ
DSR
KILL
(optional)
33
nF
(optional from TDA1307)
MGB987
220 pF
DE–EMPHASIS
(optional)
J4
C = 100 nF chip capacitor.
IC3 = IC4 = NE5532(A) or equivalent.
Fig.19 Connections for output section of TDA1307.
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
R
R1
+
−
2R1
=
=
=
=
−R1
audio
output
right
+
4R
TDA1547
=
=
+
DOR
−R2
−
+
2R2
2L2
Rn
Ln
NDOR
CDAC
NDOL
DOL
R2
20-bit, f
s
TDA1307
L2
+
−
−L2
audio
output
left
+
+
4L
TDA1547
−L1
−
+
2L1
L
L2
MGB986
Fig.20 Schematic diagram for double differential application.
1996 Jan 08
31
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
PACKAGE OUTLINE
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
42
22
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
3.2
2.9
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-02-13
95-02-04
SOT270-1
1996 Jan 08
32
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
Short-form specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jan 08
33
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
NOTES
1996 Jan 08
34
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
NOTES
1996 Jan 08
35
Philips Semiconductors – a worldwide company
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Vietnam: see Singapore
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/25/02/pp36
Date of release: 1996 Jan 08
Document order number: 9397 750 02844
相关型号：
TDA1308AUK,027
IC 0.04 W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA8, 0.61 X 0.84 MM, 0.38 MM HEIGHT, WLCSP-8, Audio/Video Amplifier
NXP
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