MC33094DW/R2_技术文档

Document Number: MC33094

Rev. 1.0, 10/2006

Freescale Semiconductor

Advance Information

Ignition Control

33094

Designed for automotive ignition applications in 12 V systems, the

33094 provides outstanding control of the ignition coil when used with

an appropriate Motorola Power Darlington Transistor. Engine control

systems utilizing these devices for ignition coil control exhibit

exceptional fuel efficiency and low exhaust emissions. The device is

designed to be controlled from a single–ended Hall Sensor input. The

circuit is built using high–density Integrated–Injection Logic (IIL)

processing incorporating high current–gain PNP and NPN

transistors.

IGNITION CONTROL

The 33094 is packaged in an economical surface mount package

and specified over an ambient temperature of –40°C to 125°C with a

maximum junction temperature of 150°C.

DW SUFFIX

EG SUFFIX (PB-FREE)

98ASB42567B

Features

• External Capacitors Program the Device’s Timing Characteristics

• Overvoltage Shutdown Protection

16-PIN SOICW

• Auto Start–Up Capability After Overvoltage Condition Ceases

• Allows for Push Start–Up in Automotive Applications

• Ignition Coil Current Limiting

ORDERING INFORMATION

Temperature

Package

Device

Range (T )

A

• Ignition Coil Voltage Limiting

• Band Gap Reference for Enhanced Stability Over Temperature

• Negative Edge Filter for Hall Sensor Input Transient Protection

• Hall Sensor Inputs for RPM and Position Sensing

• Pb-Free Packaging Designated by Suffix Code EG

MC33094DW/R2

MCZ33094EG/R2

-40°C to 125°C

16 SOICW

33094

SUPPLY

ADAPTIVE CAPACITOR

STALL CAPACITOR

RAMP CAPACITOR

DISTRIBUTOR SIGNAL

NEGATIVE INPUT

COIL

MASTER BIAS

GROUND

OUTPUT

CURRENT SENSE

PROCESS TEST

START

Figure 1. 33094 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

MASTER

BIAS (MB)

VCC

9

GND

6

2

V_R

VCC Comparator

and Clamp

V_RZener

Reference

Master Bias

Current Reference

Band Gap

Reference

BG

DISTRIBUTOR

SIGNAL (D)

VCC

V_R

10

12

Dump

Master Bias

Input Voltage

Hi-Bat

Output Current

Driver and Limiter

OUTPUT (O)

Comparator

NEGATIVE

INPUT (INV(-))

ZC

Limit

Stall

7

8

Internal

Logic

11 COIL (CL)

CURRENT

Negative

Edge Filter

14

START (ST)

SENSE (S)

Stall

CR > CA

25%

Reset

25%

PROCESS

TEST (T)

13

3

Master

Bias

Stall BG

Adaptive Capacitor

Charging and Sensing

ADAPTIVE

CAPACITOR

(CA)

CR>CA

Adaptive

Comparator

CR

V_R

Master Bias

Stall Sensing

Charging

and Sensing

BG

V_R

Ramp Capacitor

Charging and Sensing

RAMP

CAPACITOR

(CR)

4

25% Reset

25%

15

STALL

CAPACITOR (CS)

Figure 2. 33094 Simplified Internal Block Diagram

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

NC

STALL CAPACITOR

CURRENT SENSE

PROCESS TEST

OUTPUT

MASTER BIAS

ADAPTIVE CAPACITOR

RAMP CAPACITOR

NC

IC GROUND

COIL

NEGATIVE INPUT

START

DISTRIBUTOR SIGNAL

SUPPLY

Figure 3. 33094 Pin Connections

Table 1. 33094 Pin Definitions

Pin Number

Pin Name

Formal Name

Definition

1, 5, 16

NC

MB

CA

CR

GND

VIN(-)

ST

No Connect

Master Bias

Adaptive Capacitor

Ramp Capacitor

IC Ground

No Connection to the circuit

2

3

Internal bias circuit set pin - ext. resistor

Manages dwell timing - ext. capacitor

Supply ground

4

6

7

Negative Input

Start

Distributor signal from a sensor

8

Start/Run mode input

9

VCC

D

Supply

Supply voltage (battery, ingition ON)

Monitor for the battery side of the spart coil

Sparl coil voltage monitor

10

11

12

13

14

15

Distributor Signal

Coil

CL

O

Output

Supplies base current to the ext. Darlington transnsior

Used to measure internal functions

Spark coil current sensing input

Controls spark coil current - ext. capacitor

T

Process Test

Current Sense

Stall Capacitor

S

CS

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Analog Integrated Circuit Device Data

Freescale Semiconductor

3

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage

Operating Frequency Range

THERMAL RATINGS

Junction Temperature

V_CC

f_OP

28.6

V

1.0 to 400

Hz

T_J

150

°C

Operating Temperature

Continuous

T_A

-30 to 105

-40 to 125

Limited

Storage Temperature

T_STG

-55 to 150

Note 3

°C

Peak Package Reflow Temperature During Reflow ⁽²⁾

,

T_PPRT

(3)

THERMAL RESISTANCE

R_θJA

97

°C/W

Thermal Resistance

Notes

1. ESD data is available upon request.

2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 6.0 V ≤ V_{D =}V_CC≤ 16 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

SUPPLY AND MASTER BIAS

Symbol

Min

Typ

Max

Unit

Supply Current (V_CC= 16V, V_IN(-)= 0V, V_D= 3.0V,

V_CA= V_CR= V_CS= V_ST= Open) ⁽⁴⁾

I_CC

5.0

23.7

8.0

8.4

18

31

–

mA

V

Overvoltage Shutdown (V_IN(-)= 0V, V_CA= Open, V_CS= 3.0V,

V_ST= 28V) ⁽⁵⁾

V_CC3

27.5

16.1

Start-V_CCLatch (V_IN(-)= 0V, V_CA= V_CR= V_CS= Open,

V_ST= 25V, V_D= 14V I_ST= 40mA)

V_CC5

V

Adaptive Dwell High Supply Voltage (V_IN(-)= 11V, V_CA= Open,

V_CR= 3.0V, V_CS= 3.0V, V_ST= 6.0V, V_D= 13V)

V

Threshold ⁽⁶⁾

Hysteresis ⁽⁷⁾

V_CC1

16.5

0.2

18.9

0.5

19.5

0.8

V_{CC2 (HYS)}

Master Bias Voltage (V_CC= 16V, V_IN(-)= 0V, V_D= 3.0V,

V_CA= V_CR= V_CS= V_ST= Open) ⁽⁸⁾

V_MB

1.12

1.2

1.32

V

INPUTS

Input Positive Threshold Voltage (V_CC= 6.0V, V_CA= V_CR= Open,

V_CS= 1.0V, V_ST= 6.0V) ⁽⁹⁾

V_IN(-)(TH)A

50

54

65

%V_CC

Input Positive Threshold Voltage (V_CC= 16V, V_CA= V_CR= Open,

V_CS= 1.0V, V_ST= 10V) ⁽¹⁰⁾

V_IN(-)(TH)B

Input Hysteresis (V_CC= 6.0V, V_CA= V_CR= V_CS= Open,

V_ST= 6.0V) ⁽¹¹⁾

V_IN(-)(HYS)A

V_IN(-)(HYS)B

Z_I

0.6

1.6

70

0.72

2.23

94

1.2

3.2

250

V

Input Hysteresis (V_CC= 16V, V_D= 3.0V,

V_CA= V_CR= V_CS= Open, V_ST= 10V) ⁽¹²⁾

Input Impedance (V_CC= 14V, V_IN(-)= 10V, V_D= 3.0V,

V_CA= V_CR= V_CS= V_ST= Open) ⁽¹³⁾

kΩ

Notes

4. Current sourced into Supply pin.

5. Ramp up V_CCfrom 24 to 31V in 0.1 increments and note the supply voltage, V_CC, which causes V_Oto fall below 1.0V.

6. Ramp up V_CCfrom 14 to 20V in 0.1 increments and measure V_CC, when ICA ≤ 2.0 µΑ.

7. Ramp down V_CCfrom 20 to 14V and measure V_CC, when ICA ≥ 2.0 µΑ and compute hysteresis difference from V_CC1

.

8. Voltage measured at Master Bias pin.

9. Ramp up V_IN(-)from 1.0 to 5.0V in 0.1 increments. Record V_IN(-)when I_CRgoes positive and convert to % of V_CCby dividing by V_CC

10. Ramp up V_IN(-)from 3.0 to 10V in 0.1 increments. Record V_IN(-)when I_CRgoes positive and convert to % of V_CCby dividing by V_CC

.

11. Ramp up V_IN(-)from V_IN(-)(TH)Ain 0.1 increments. Record V_IN(-)when I_CRgoes positive. V_IN(-)(HYS)A= V_{IN(-)(TH)A - (}V_IN(-))

.

12. Ramp up V_IN(-)from V_IN(-)(TH)Bin 0.1 increments. Record V_IN(-)when I_CRgoes positive. V_IN(-)(HYS)B= V_{IN(-)(TH)B - (}V_IN(-))

13. Measure I_IN(-)into Pin 7; Z_I= 10 V/I_IN(-)

.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_{D =}

V_CC≤ 16 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OUTPUT AND DWELL

Output Current (V_IN(-)= 0V, V_CA= V_CR= Open, V_CS= 3.0V, V_ST= 10V,

V

mA

_O= 2.1V) ⁽¹⁴⁾

Normal Condition (V_CC= 14V, V_D= 6.0V)

High Voltage Condition (V_CC= 14V, V_D= 22V)

I_O1

I_O2

40

52

65

Output Leakage Current (V_CC= 14V, V_IN(-)= 10V, V_CA= V_CR= V_CS

Open, V_ST= 10V, V_S= 0V, V_D= 18V, V_O= 0V) ⁽¹⁵⁾

=

I_O3

V_CL

Z_CL

1.0

13.7

10

-1.33

14.52

37

100

15.58

75

µA

V

Output Clamp Voltage (V_CC= 14V, V_IN(-)= 10V, V_CA= V_CR= V_CS

Open, V_ST= 10V, V_D= 14V, V_O= 0V, V_CL= 20V, I_CL= 10mA) ⁽¹⁶⁾

=

Output Clamp Dynamic Impedance (VCC = 14V, V_IN(-)= 10V, V_CA= V_CR

= V_CS= Open, V_ST= 10V, V_D= 14V, V_O= 0V, I_CL= 12mA,

∆I_CL= 2.0mA) ⁽¹⁷⁾

Ω

Dwell ⁽¹⁸⁾

%

Normal Condition: D1 = (I_CA2/I_CA1) x CR

Data from I_CA2, I_CA1, and CR characteristics

D1

D2

14.5

4.1

-60

0

17.6

5.3

0

20.5

5.9

High Voltage Condition: D2 = (I_CA3/I_CA1) x CR

Data from I_CA3, I_CA1, and CR characteristics

Adaptive Dwell Logic, Ramp Threshold (V_CC= 14V, V_IN(-)= 10V,

V_CA= V_CS= Open, V_ST= 0V, V_S= 0V, V_D= 10V) ⁽¹⁴⁾

V_CRO

60

mV

Soft Shutdown Voltage (V_CC= 6.0V, V_IN(-)= 10V, V_CA= V_CR= V_CS

Open, V_ST= 0V) Measure V_S

=

V_SS

1.48

16.7

Notes

14. Capability measured by forcing the Output to 2.0V with the Current Sense pin (S) open while measuring the Output current to ground.

15. Measured by clamping the output voltage with the S pin to ground, then increasing the V_Dfrom 6.0 to 18V and measuring output leakage

current to ground.

16. Output Clamp voltage with reference to ground while forcing 10mA into the Coil pin (CL).

17. Output Clamp impedance measured with I_CL= 11 ±1.0mA into the Coil pin (CL) and noting the corresponding Output Clamp Voltage

change (Z_CL= ∆V_CL/∆I_CL).

18. Dwell is defined as Run Mode Down Current divided by the Run Mode Up Current times the Ramp Control Current Ratio and is

calculated from other measured characteristics as defined above.

19. Set the V_CR(ramp Capacitor) voltage to 1.5V; Ramp V_CRvoltage from 1.8 to 2.2V in 0.02V increments and note the Ramp voltage (V_CR

which causes the Output voltage to go > 1.0V; V_CRO= 2.0V - V_CR.

)

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_{D =}

V_CC≤ 16 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

ADAPTIVE CAPACITOR

Run Mode, Adaptive, Charge Current (VCC = 6.0V, V_IN(-)= 5.0V,

V_CA= Open, V_CR= 3.0V, V_CS= 3.0V, V_ST= 6.0V) ⁽²⁰⁾

I_CA1

-7.91

-6.53

-5.62

µA

Run Mode, Adaptive Capacitor, Discharge Current

(V_CA= Open, V_CR= 3.0V, V_CS= 3.0V, V_ST= 6.0V)

Normal Condition (V_CC= 6.0V, V_IN(-)= 10V)

I_CA2

I_CA3

3.7

4.77

1.43

5.63

1.82

High Voltage Condition (V_CC= 22V, V_IN(-)= 17V, V_D= 13V)

1.05

Start Mode, Adaptive Capacitor Currents

(V_CA= V_CR= V_CS= Open, V_ST= 10V)

µA

Charge Current (V_CC= 5.0V, V_IN(-)= 10V) ⁽²¹⁾

Discharge Current (V_CC= 6.0V, V_IN(-)= 0V) ⁽²²⁾

I_CA4

I_CA5

-112

67.6

-87

-80

89.4

109

Start Mode, Adaptive Capacitor, Clamp Voltage

(V_CC= 6.0V, V_CA= V_CR= V_CS= Open, V_ST= 10V)

V

High Clamp Voltage (V_IN(-)= 10V)

Low clamp Voltage (V_IN(-)= 0V)

V_CA1

V_CA2

2.30

1.1

2,65

1.26

2.23

0.95

Adaptive Gain (V_CC= 14V, V_IN(-)= 11V, V_ST= 6.0V, V_CA= Open, V_CR

3.0V, V_CS= 3.0V, V_D= 13V) ⁽²³⁾

=

AG

0.85

0.99

1.15

Times

STALL CAPACITOR

Start Mode, Stall Control, Charge Current (V_CC= 5.0V, V_IN(-)= 0V,

V_CA= V_CR= Open, V_CS= 1.0V, V_ST= 10V)

I_CS1

-2.7

7.5

-2.33

9.69

-27

-2.13

13.2

-23.5

1.26

2.45

165

µA

V

Run Mode, Stalled, Stall Control, Discharge Current (V_CC= 14V,

V_IN(-)= 0V, V_CA= V_CR= Open, V_CS= 1.0V, V_ST= 0V)

I_CS2

Run Mode, Stall Control, Charge Current (V_CC= 14V,

V_IN(-)= 10V, V_CA= 2.0V, V_CR= 3.0V, V_CS= 1.0V, V_ST= 0V)

ICS3

ICS4

V_CS1

V_CS2

-33.1

0.76

1.95

20

Run Mode, Stall Control, Discharge Current (V_CC= 14V, V_IN(-)= 10V,

1.02

2.06

35.3

V

_CA= 2.0V, V_CR= Open, V_CS= 1.0V, V_ST= 0V, V_MB= 0V)

Stall Control Threshold Voltage (V_CC= 14V, V_IN(-)= 0V, V_CA= V_CR

Open, V_ST= 0V) ⁽²⁴⁾

=

Stall Control Saturation Voltage (V_CC= 14V, V_IN(-)= 0V,

V_CA= V_CR= V_CS= Open, V_ST= 0V)

mV

Notes

20. Open V_CR(Ramp Capacitor) initially then force V_CR= 3.9V and measure ICA1.

21. Start Mode Adaptive Control sourcing current.

22. Start Mode Adaptive Control sink current.

23. Measure I_CA. Calculate: AG = I_CR1/I_CA

.

24. Ramp V_CS(Stall Capacitor) from 1.5 to 2.5V in 20 mV steps. Record V_CSwhen I_CSgoes negative.

25. Set V_ST= 10V, V_CS= 1.0V, Fail if output is on. Set V_CS= 3.0V, Fail if output in off.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ V_{D =}

V_CC≤ 16 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted.

Typical values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

RAMP CAPACITOR

Ramp Control Current Ratio (V_CC= 14V, V_IN(-)= 0V,

V_CR= 3.0V, V_ST= 0V, V_CA= V_CS= Open) ⁽²⁶⁾

CR

22

24.4

28

%

Ramp Capacitor Reset Hysteresis (V_CC= 14V, V_IN(-)= 10V,

V_CA= 2.0V, V_CS= 3.0V, V_ST= 6.0V) ⁽²⁷⁾

V_CR(hyh)

6.0

19.19

180

mV

Notes

26. Set V_CA(Adaptive Capacitor) to 0.5V, then open V_CA. Set V_CR(Ramp Capacitor) to 0.9V Percent ratio of CR UpCurrent as compared

to the CR Down Current; (I_CR1/(I_CR1-I_CR2) x 100).

27. Open V_CR, Force V_CR= 1.3V. Ramp V_CRdown in 30mV steps until I_CRgoes negative, V_CR1. Ramp V_CRup in 3.0mV steps, toggle input

between steps, until I_CRgoes positive, V_CR2. V_CR(hys)-V_CR2- V_cr1

.

VMB

1

NC

16

15

14

13

12

11

10

9

I_CS

15.25kΩ

2

V_S

V_CS

3.0V

+

I_CA

10

Ω

20Ω

3

+

V_CA

I_CR

2.0V

4

200Ω

+

V_CR

3.0V

V_O

NC

5

6

7

8

V_CL

55Ω

I_IN(-)

5.0kΩ

I_D

I_CL

+

V_D

13V

V_IN(-)

10V

27kΩ

250

Ω

I_ST

+

I_CC

+

V_ST

0V

V_CC

13V

Figure 4. Test Circuit

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 7.0 V ≤ V_CC≤ 18 V, -40°C ≤ T_A≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING

Negative Edge Filter, Falling Edge Time Constant (V_CC= 16V, V_IN(-)= 0V,

V_CA= V_CR= V_CS= Open, V_ST= 10V ⁽²⁸⁾

t₁

400

0

613.65

3.45

1000

15

µs

Propagation Delay Time (V_CC= 14V, V_IN(-)= 10V, V_CA= V_CS= Open,

V_CR=3.0V, V_ST= 0V) ⁽²⁹⁾

t₂

(30)

Start Delay, Positive Edge (Data from I_CA4, V_CA1, V_CA2

)

1.15

1.19

71

1.46

2.06

87

1.71

2.8

ms

Hz

ms

t_SDP

t_SDN

t_SOD

t_SSD

t_SST

f_SS

Start Delay, Negative Edge (Data from V_CA4, I_CA5, V_CA2, t₁) ⁽³¹⁾

Start to Output Disable Time ⁽³²⁾

107

8.8

(33)

Stall to Spark Output Propagation Delay (Data from I_CS3, V_CS1, V_CS2

)

4.6

7.48

20.9

2.26

66.65

(34)

Stall Shutdown Time (Data from I_CS2, V_CS1, V_CS2

Stall Frequency ⁽³⁵⁾

)

13.6

1.69

25

26.5

2.8

Battery Interrupt Time (V_CC= V_IN(-)= V_ST= 0V, V_CA= V_CR= Open,

V_CS= 6.0V) ⁽³⁶⁾

200

t_BIT

Notes

28. Measure time until V_O> 0.2V. The Negative Edge Filter prevents multiple output sparks caused by switching transients present at the

input by disabling the once used input for the filter time t.

29. Propagation delay time measurement of input to output response; Step change V_IN(-)from 0 to 10V.

Measure the time required for V_O< 1.5V

30. t_SDP= (V_CA1- V_CA2) x CA/I_CA4; CA = 0.1 µF

31. t_SDN= [(V_CA1- V_CA2) x CA/I_CA5]+t₁; CA = 0.1 µF

32. t_SOD= (V_CA1- V_CA2) x CS/I_CA1; CS = 0.1 µF

33. t_SSD= (V_CA1- V_CA2) x CS/I_CA3; CS = 0.1 µF

34. t_SST= (V_CA1- V_CA2) x CS/I_CA2; CS = 0.1 µF

35. f_SS= 1/[(5.4/V_IN(-)(TH)) + (4.3/I_CS4) + (2/I_CS2)] x CS; CS = 0.1 µF

36. t_BIT= [(V_CS- 0.7V)/I_CS1] x CS; CS = 0.1 µF

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

V_IN(-)

Run Mode ⁽³⁷⁾

V_OUT

V_IN(-)

Start Mode ⁽³⁸⁾

V_OUT

V_IN(-)

V_OUT

Stall Mode ⁽³⁹⁾

Figure 5. Basic Timing Diagrams

Notes

37. The falling edge of the V_IN(-)signals is a charge command, while the rising edge signals a spark command.

38. During start mode. stall conditions are prevented.

39. During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.

ELECTRICAL PERFORMANCE CURVES

7.0

9.0

V

= 16V

= 14V

V

= 16V

CC

V

= 10V

CC

ST

8.0

6.0

5.0

V

= 10V

ST

V

CC

7.0

6.0

5.0

4.0

3.0

V

= 1.0V

CS

= V

V

= 1.0V

ST

= V

V

= Open

CA

CR

4.0

3.0

2.0

V

= V

CR CS

= Open

CA

V

= 6.0V

V

= 6.0V

CC

V

= 6.0V

ST

0

150

50

T, Temperature (°C)

-50

100

0

150

50

T, Temperature (°C)

-50

100

Figure 7. Input Negative Threshold Voltage versus

Temperature

Figure 6. Input positive Threshold Voltage versus

Temperature

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

3.2

3.0

2.8

50

V

I

= 0V

O

= 12mA

= 2.0mA

CL

45

40

35

30

25

∆Ι

CL

= ∆V /∆Ι

V

O from 10 to 22V

Z

CL

CL CL

2.6

2.4

2.2

0

150

50

T, Temperature (°C)

-50

100

0

150

50

-50

100

T, Temperature (°C)

Figure 8. Output Current Change versus Temperature

Figure 11. Output Clamp Dynamic Impedance versus

Temperature

160

8.7

V

= Open

140

IN(-)

= 16V

V

= 0V

CC

8.6

IN(-)

= 6.0V

Pin 6 = 10V

120

100

80

CC

= 3.0V

Z = 10 V/I

I

IN(-)

D

8.5

8.4

8.3

8.2

8.1

60

40

-50

0

150

50

100

0

150

50

T, Temperature (°C)

-50

100

T, Temperature (°C)

Figure 9. Input Impedance versus Temperature

Figure 12. Supply Drain Current versus Temperature

15.2

15

V

I

- 0V

= 10mA

O

CL

14.8

14.6

14.4

14.2

14

0

150

50

-50

100

T, Temperature (°C)

Figure 10. Output Clamp Voltage versus Temperature

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The MC33094DW is designed for engine compartment

use in 12 V automotive ignition applications to provide high

performance control of the ignition coil when used with an

appropriate Freescale Power Darlington Transistor. Engine

control systems utilizing these devices for ignition coil control

exhibit superior fuel efficiency and lower exhaust emissions

over predecessor systems. The device is designed for single

input control from a Hall sensor to determine crankshaft

position.

transistor to provide control of the ignition coil. The output

drive is carefully synchronized with the output from the

distributor. The charging and discharging of three capacitors,

external to the device, provide timing signals which program

the dwell and charge time control of the ignition coil over a

wide rpm range.

The timing and charge/discharge rates of the three

external capacitors are accurately controlled by internal

circuitry acted upon by sensor and distributor signal detection

of the device.

The device, a bipolar linear integrated circuit, is built using

high–density Integrated–Injection Logic (IIL) processing

incorporating high current–gain PNP and NPN transistors. All

module inputs are transient voltage protected through the

use of resistors, capacitors, and/or zener diodes working in

conjunction with internal protection elements. These

elements provide protection of critical circuitry from externally

induced high–voltage transients which may degrade the

devices operational performance. At the module level, it is

recommended that the VCC pin of the device be transient

decoupled using an external resistor and capacitor to work in

conjunction with the on–chip internal zener string to provide

robust module protection of the device power pin. The D

(Distributor Signal) input of module should be protected from

transients through the use of an external resistor and zener

diode. The Start input (ST) of the module should be

decoupled through the use of two resistors and a capacitor to

work in conjunction with the on–chip internal clamp

(Figure 13).

A feedback path from the emitter of the external power

Darlington transistor to the device provide monitoring of the

ignition coil current. An internal comparator of the device

senses and limits the maximum ignition coil current to

approximately 6.5 amps. Other circuitry within the device

provides an interruption of the coil current so as to generate

the spark, or slowly discharges the coil in a controlled manner

so as to prevent a spark and limit the total module energy

dissipation.

When the external Darlington is switched off, the

Darlington collector will instantly experience a dramatic

increase in voltage as a result of the collapsing field of the

ignition coil (inductive kick). The external voltage divider

working in conjunction with the internal device zener string

and power PNP form a dynamic clamp which limits the

inductive kick voltage to less than 350 V. This feature

protects the Darlington transistor from damaging stress or

breakdown.

The output of the device incorporates a high current–gain

PNP designed to drive an external power Darlington

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

The V_RZener Reference block contains a 6.75 V zener

regulator, which also exhibits a very low temperature

coefficient.

BLOCK DIAGRAM DESCRIPTION (Figure 2)

The Band–Gap Reference generates a nominal 1.2V

having very good stability with temperature variations. The

Band–Gap Reference conceptually provides a low

temperature drift voltage by summing a strongly negative

Temperature Coefficient (TC) voltage with an equally strong

positive TC voltage. The negative TC voltage element is a

result of a transistor emitter–to–base voltage while the

positive TC voltage is developed as a result of a positive TC

current imposed across a resistor. The positive TC current

relies on the matching of currents in different sizes of

transistors. The result is a very stable reference voltage

independent of temperature variations. The Band–Gap

Reference voltage provides a thermally stable voltage

reference for critically sensitive circuits within the IC. It also

sets the master bias current for all precision currents on the

IC.

The V_CCComparator and Clamp block limits the V_CC

voltage to one V_BEplus three zener drops in addition to

comparing the V_CCvoltage to 15 and 22V. When the V_CC

voltage is greater than either of these two values, the IC

changes the adaptive capacitor discharge rate and when

above 22V the IC forces the coil current to shutdown. The

minimum V_CCvalue the IC will operate at is 4.0V and V_BATof

5.0V. Below 7.5V, the V_Rreference is no longer maintained,

and the IC consumes excess power and excess voltage is

dropped in the external VCC resistor.

The Master Bias Current Reference block generates

precise currents used throughout the IC. The MB pin is held

at 1.2V by a differential amplifier with feedback. Capacitive

loading on the MB pin reduces the effectiveness of the

internal dominant pole, and loading as modest as 200pF may

cause the differential amplifier to oscillate.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

The Input Voltage Comparator block requires an input

signal between ground and V_BATand detects the swing in the

input signal (V_IN(-)). The thresholds for the input comparator

are approximately 56.2% of V_BATfor rising signals and 36%

of V_BATfor falling signals. The input signal may come from a

Hall effect sensor or reluctance sensor on the distributor.

current to be proportional to the stall capacitor voltage when

the stall capacitor voltage is less than 2.0V.

The Ramp Capacitor Charging and Sensing block charges

the ramp capacitor at approximately 8.4µA and discharges it

at about 33.6µA. The charging circuit is always on and

sources current during the “not 25%” part of the engine cycle.

The discharging circuit is only on and sinking current during

the “25%” part of the engine cycle. The positive edge of the

distributor input signal sets the 25% mode, and the ramp

comparator output clears this mode.

The Negative Edge Filter block is an inverting buffer for the

signal from the Input Voltage Comparator and has a time

constant of approximately 0.1µs for rising edges and 500µs

for falling edges.

The Adaptive Capacitor Charging and Sensing block

charges, discharges, and senses the adaptive capacitor

voltage. The adaptive capacitor has a single charge rate of

8.4µA and two discharge rates. The 1.688µA slow discharge

rate is used only during very high V_CCoperation and

represents an effort to reduce excess dwell and therefore

power dissipation during high voltage operation. The 5.88µA

discharge rate is used under normal V_CCoperating

conditions. Under a start mode, this block will discharge the

adaptive capacitor forcing an enhanced start mode dwell.

The start/run modes are set internally by detecting the engine

frequency, which corresponds to the ramp capacitor voltage.

The CR > CA Adaptive Comparator block signals the point

where the ramp capacitor voltage is greater than the adaptive

capacitor voltage. The point at which the two capacitor

voltages are equal is the point where charging of the coil is

begun. The adaptive algorithm used in the IC maintains the

required excess dwell throughout all reasonable

accelerations and decelerations without causing excess coil

power dissipation, in addition, it insures that more than

adequate spark energy is available for very high engine

speeds, when excess dwell is impossible.

The Output Current Driver and Limiter block sources a

limited supply current of about 50mA to the base of the

Darlington power transistor. The Darlington will cause the coil

to conduct to about 6.5 amps and the voltage drop on the S

pin of the IC will rise to the threshold of the current limiter. The

current limiter will then hold the coil current at that level until

either a spark is commanded by the logic block, or the engine

begins to stall (causing the coil to slowly discharge).

The Stall Capacitor Charging and Sensing block controls

the charging and discharging rates of the stall capacitor. The

charging rate is 31.5µA, and the two discharging rates are

1.0µA and 7.0µA. The stall capacitor potential commands the

IC to maintain or reduce the coil current. When the engine is

turning very slowly (or stalled), the stall capacitor will have

enough time to discharge below threshold and thereby

reduce coil current. The output current limiter forces the coil

The Internal Logic block performs the required memory

and gating functions on the IC to implement the adaptive

ignition control algorithm.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DEVICE OPERATION

IC will provide a spark timing with a maximum retardation of

about 6.5ms.

IGNITION CIRCUIT OPERATION DESCRIPTION

When initially powered up, all module capacitors start

discharged (0V). The V_CCcapacitor will power up first, and

the IC’s internal logic latches are indeterminate. The following

conditions will hold: STALL = 1, because the stall capacitor

voltage is less than 2.0 V; 25% = 0, because the ramp

capacitor is less than the Band Gap Reference voltage (V_BG);

and I_COIL= 0 amps, because the stall capacitor is at 0V.

After the start mode operation is exited, the normal

operation algorithm is entered and a different sequence of

events dominate the IC’s performance. See Figures 16, 17,

and 18. At point A, the spark from the previous cycle occurs

and the 25% part of the cycle begins. During this part of the

cycle, the stall capacitor will charge and the ramp and

adaptive capacitors will discharge. At point B, the “not 25%”

part of the cycle, also called the 75% part of the cycle, begins.

The stall capacitor discharges, while the ramp capacitor

charges. During this part of the cycle the adaptive capacitor

floats. At point C, the ramp capacitor voltage equals the

voltage on the adaptive capacitor. At this time, the coil turns

on and the coil current ramps to the point where it is limited.

When the coil current reaches the limit, point D, the adaptive

capacitor begins to charge, until zero cross

Because 25% = 0, the ramp capacitor charges towards Vr.

At cranking frequencies, the ramp capacitor always exceeds

the start mode threshold at the input (ZC or V_IN-1), and

therefore the stall signal resets the start mode latch upon the

first ac signal (this causes the adaptive capacitor to be

discharged). With the adaptive capacitor held low, very high

rates of acceleration are possible. If the adaptive capacitor

were allowed to adapt the dwell at low frequencies, severe

limitations to engine acceleration would occur.

(ZC = 1logic(high)), point E. This turns the coil off and

induces a spark. The 75% part of the cycle lasts until point E,

at which time the cycle begins again.

See Figure 15. At point A, a spark from the previous cycle

occurs as the field around the coil collapses rapidly. At the

same time ZC (V_IN- > 10V) will set the 25% clock signal which

commands the adaptive and ramp capacitors to discharge

and the stall capacitor to charge. At point B, as the ramp

capacitor voltage crosses the 1.2V (V_BG) level, the 25% clock

is cleared and the polarities and amplitude of the ramp and

stall capacitor currents change to their appropriate levels. At

this point the adaptive capacitor is discharged and begins to

float. At point C, the coil turns on and ramps until the coil

current is limited to 6.5 amps. The adaptive capacitor, at point

D, remains discharged and the dwell is maximized to 6.5

amps because the start/run latch has yet to be set. At point

E, ZC (V_IN- > 10V, ZC = high) turns the coil off causing a

spark to occur and at which point a new cycle begins. As the

engine frequency increases, the peak voltage on the ramp

capacitor at the ac signal will fall below the start mode enable

threshold level. The start mode enable detector then sets the

start/run latch to the run mode (CA_DUMP= 0) by clocking a

zero into the start/run latch at the zero cross. At this time the

adaptive algorithm is evoked and the adaptive capacitor is

allowed to charge and discharge according to it’s other logical

inputs. After normal run mode operation is entered, the start

mode may not be reentered even though the ramp capacitor

voltage again exceeds the start mode enable threshold. A

start mode may only be evoked by a STALL signal transition

from logic 1 to 0. The STALL signal transition occurs at a V_IN-

frequency of approximately 2.0 Hz.

The adaptive dwell algorithm causes the engine to

maintain a fixed percent of excess dwell time (if possible).

The mechanism that permits this involves the floating nature

of the adaptive capacitor. During engine deceleration, the

initial coil turn–on might occur early, but the next coil turn–on

will be retarded to it’s correct location due to the % adjusted

adaptive capacitor charge time. During acceleration, the coil

may not charge up as early as desired the first time, however,

the spark will still be correctly slaved to the distributor. The

side effect of this is that the adaptive capacitor will not receive

as much charge time for that cycle and will have a lower

average value the next cycle, thus starting the coil charging

sooner, as can be seen in Figure 17. In this figure, the output

voltage rises before the adaptive capacitor charge signal

occurs.

See Figure 13. In the Stall mode the output is slaved by the

stall capacitor. The stall capacitor can discharge completely,

but starting at point X it charges during the 25% of the engine

cycle (duration of when ZC is logic high = 1). At the same time

a spark from the previous cycle occurs. The DWELL signal

will be high as long as the engine is in stall, but falls gradually

preventing a spark at point Y when the STALL goes low

starting at 2.4V. The coil will be slaved to the stall capacitor,

and at point Z the coil will charge to 6.5 amps as the stall

capacitor charges to 2.0V. At that time the STALL comparator

will trip (STALL = 0) and the DWELL signal will fall, triggering

a reduced spark with some retardation (6.5ms). At this point

a new cycle begins.

The IC and circuit provides for other than normal starting

procedures such as push starting the engine. Since the stall

capacitor will be discharged in this low frequency mode, the

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DEVICE OPERATION

Each of the three different modes (Stall, Start, and Run)

have their own differences. The Stall capacitor controls the

output in the stall mode, however is disabled in both the start

and run modes. The output is clamped longer in the start

mode as compared to the run mode due to the more energy/

current in the coil causing a longer/bigger spark.

Other less likely operating sequences are possible. For

example, there is a possibility of V_CCexceeding 15V during

engine operation (High battery = logic 1). Above about 17V

on V_BAT, the excess current limit percentage falls to 5% to

conserve IC and circuit power dissipation. Above 25V,

current to the coil is disabled. Care was placed in this design

to account for all possible operating modes.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

TYPICAL APPLICATIONS

INTRODUCTION

TYPICAL APPLICATIONS

+V_OUT

Ignition

330

55

15.3k

0.1µ

18V

200

2

MB 6

9

G

VCC

4.0k

Band-Gap

Reference

VCC Clamp and

Zener Ref.

Master

Bias

10

D

BU931,

MJE5742

or

Input

11

Comp. and

Negative

Edge Filter

Output Current

Driver and Limiter

V_IN(-)

10k

CL

7

MJH10012

Internal

Logic

VIN(-)

12

O

SW

27k

8

200

ST

13

14

CR > CA

Comparator

0.1µ

S

T

Adaptive

Capacitor

Stall

Capacitor

Ramp

Capacitor

0.05

5.0W

56

CA

3

CS

15

CR

4

0.1µ

Figure 13. Typical Ignition Circuit Application

INTRODUCTION

The MC33094 is designed for engine compartment use in

12V automotive ignition applications to provide high

performance control of the ignition coil when used with an

appropriate Motorola Power Darlington Transistor. Engine

control systems utilizing these devices for ignition coil control

exhibit superior fuel efficiency and lower exhaust emissions

over predecessor systems. The device is designed for single

input control from a Hall sensor to determine crankshaft

position.

robust module protection of the device power pin. The D

(Distributor input) input of module should be protected from

transients through the use of an external resistor and zener

diode. The Start input of the module should be decoupled

through the use of two resistors and a capacitor to work in

conjunction with the on–chip internal clamp (Figure 13).

The output of the device incorporates a high current–gain

PNP designed to drive an external power Darlington

transistor to provide control of the ignition coil. The output

drive is carefully synchronized with the output from the

distributor. The charging and discharging of three capacitors,

external to the device, provide timing signals which program

the dwell and charge time control of the ignition coil over a

wide RPM range.

The device, a bipolar linear integrated circuit, is built using

high–density Integrated–Injection Logic (IIL) processing

incorporating high current–gain PNP and NPN transistors. All

module inputs are transient voltage protected through the

use of resistors, capacitors, and/or zener diodes working in

conjunction with internal protection elements. These

elements provide protection of critical circuitry from externally

induced high–voltage transients which may degrade the

devices operational performance. At the module level, it is

recommended the VCC pin of the device be transient

decoupled using an external resistor and capacitor to work in

conjunction with the on–chip internal zener string to provide

The timing and charge/discharge rates of the three

external capacitors are accurately controlled by internal

circuitry acted upon by sensor and distributor signal detection

of the device.

A feedback path from the emitter of the external power

Darlington transistor to the device provide monitoring of the

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

TYPICAL APPLICATIONS

ignition coil current. An internal comparator of the device

senses and limits the maximum ignition coil current to

approximately 6.5 amps. Other circuitry within the device

provides an interruption of the coil current so as to generate

the spark, or slowly discharges the coil in a controlled manner

so as to prevent a spark and limit the total module energy

dissipation.

When the external Darlington is switched off, the

Darlington collector will instantly experience a dramatic

increase in voltage as a result of the collapsing field of the

ignition coil (inductive kick). The external voltage divider

working in conjunction with the internal device zener string

and power PNP form a dynamic clamp which limits the

inductive kick voltage to less than 350V. This feature protects

the Darlington transistor from damaging stress or breakdown.

capacitor will be discharged in this low frequency mode, the

IC will provide a spark timing with a maximum retardation of

about 6.5 ms.

IGNITION CIRCUIT OPERATION DESCRIPTION

When initially powered up, all module capacitors start

discharged (0V). The VCC capacitor will power up first, and

the IC’s internal logic latches are indeterminate. The following

conditions will hold: STALL = 1, because the stall capacitor

voltage is less than 2.0 V; 25% = 0, because the ramp

capacitor is less than the Band Gap Reference voltage (V_BG);

and I_COIL= 0 amps, because the stall capacitor is at 0V.

After the start mode operation is exited, the normal

operation algorithm is entered and a different sequence of

events dominate the IC’s performance. See Figures 16,

Figures 17 and Figures 18. At point A, the spark from the

previous cycle occurs and the 25% part of the cycle begins.

During this part of the cycle, the stall capacitor will charge and

the ramp and adaptive capacitors will discharge. At point B,

the “not 25%” part of the cycle, also called the 75% part of the

cycle, begins. The stall capacitor discharges, while the ramp

capacitor charges. During this part of the cycle the adaptive

capacitor floats. At point C, the ramp capacitor voltage equals

the voltage on the adaptive capacitor. At this time, the coil

turns on and the coil current ramps to the point where it is

limited. When the coil current reaches the limit, point D, the

adaptive capacitor begins to charge, until zero cross (ZC =

1logic(high)), point E. This turns the coil off and induces a

spark. The 75% part of the cycle lasts until point E, at which

time the cycle begins again.

Because 25% = 0, the ramp capacitor charges towards

V_R. At cranking frequencies, the ramp capacitor always

exceeds the start mode threshold at the input (ZC), and

therefore the stall signal resets the start mode latch upon the

first ac signal (this causes the adaptive capacitor to be

discharged). With the adaptive capacitor held low, very high

rates of acceleration are possible. If the adaptive capacitor

were allowed to adapt the dwell at low frequencies, severe

limitations to engine acceleration would occur.

See Figure 14. At point A, a spark from the previous cycle

occurs as the field around the coil collapses rapidly. At the

same time ZC (ZC (input) = high(1)) will set the 25% clock

signal which commands the adaptive and ramp capacitors to

discharge and the stall capacitor to charge. At point B, as the

ramp capacitor voltage crosses the 1.2V (V_BG) level, the 25%

clock is cleared and the polarities and amplitude of the ramp

and stall capacitor currents change to their appropriate

levels. At this point the adaptive capacitor is discharged and

begins to float. At point C, the coil turns on and ramps until

the coil current is limited to 6.5 amps. The adaptive capacitor,

at point D, remains discharged and the dwell is maximized to

6.5 amps because the start/run latch has yet to be set. At

point E, ZC (ZC = high) turns the coil off causing a spark to

occur and at which point a new cycle begins. As the engine

frequency increases, the peak voltage on the ramp capacitor

at the ac signal will fall below the start mode enable threshold

level. The start mode enable detector then sets the start/run

latch to the run mode (CADUMP = 0) by clocking a zero into

the start/run latch at the zero cross. At this time the adaptive

algorithm is evoked and the adaptive capacitor is allowed to

charge and discharge according to it’s other logical inputs.

After normal run mode operation is entered, the start mode

may not be reentered even though the ramp capacitor

voltage again exceeds the start mode enable threshold. A

start mode may only be evoked by a STALL signal transition

from logic 1 to 0. The STALL signal transition occurs at a ZC

frequency of approximately 2.0 Hz.

The adaptive dwell algorithm causes the engine to

maintain a fixed percent of excess dwell time (if possible).

The mechanism that permits this involves the floating nature

of the adaptive capacitor. During engine deceleration, the

initial coil turn–on might occur early, but the next coil turn–on

will be retarded to it’s correct location due to the % adjusted

adaptive capacitor charge time. During acceleration, the coil

may not charge up as early as desired the first time, however,

the spark will still be correctly slaved to the distributor. The

side effect of this is that the adaptive capacitor will not receive

as much charge time for that cycle and will have a lower

average value the next cycle, thus starting the coil charging

sooner, as can be seen in Figure 18. In this figure, the output

voltage rises before the adaptive capacitor charge signal

occurs.

See Figure 14. In the Stall mode the output is slaved by the

stall capacitor. The stall capacitor can discharge completely,

but starting at point X it charges during the 25% of the engine

cycle (duration of when ZC is logic high = 1). At the same time

a spark from the previous cycle occurs. The DWELL signal

will be high as long as the engine is in stall, but falls gradually

preventing a spark at point Y when the STALL goes low

starting at 2.4V. The coil will be slaved to the stall capacitor,

and at point Z the coil will charge to 6.5 amps as the stall

capacitor charges to 2.0V. At that time the STALL comparator

will trip (STALL = 0) and the DWELL signal will fall, triggering

The IC and circuit provides for other than normal starting

procedures such as push starting the engine. Since the stall

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

TYPICAL APPLICATIONS

a reduced spark with some retardation (6.5 ms). At this point

a new cycle begins.

Other less likely operating sequences are possible. For

example, there is a possibility of VCC exceeding 15V during

engine operation (High battery = logic 1). Above about 17V

on Vbat, the excess current limit percentage falls to 5% to

conserve IC and circuit power dissipation. Above 25V,

current to the coil is disabled. Care was placed in this design

to account for all possible operating modes.

Each of the three different modes (Stall, Start, and Run)

have their own differences. The Stall capacitor controls the

output in the stall mode, however is disabled in both the start

and run modes. The output is clamped longer in the start

mode as compared to the run mode due to the more energy/

current in the coil causing a longer/bigger spark.

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

TYPICAL APPLICATIONS

Engine Cycle

11.68V

V_IN(-)

(Pin 7)

(ZC)

1.08V

0V

1.7V

Gradual

Fall

V_OUT

(Pin 12)

300mV

0V

6.78V

6.09V

V_CA

(Pin 3)

4.9V

6.8V

V_CR

(Pin 4)

1.2V

6.56V

V_CS

(Pin 15)

2.4V

2.0V

80mV

Linear

Charge

X

Y

Z

Figure 14. Stall Mode 60 RPM (Frequency: 2.0 Hz @ 100 ms)

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

TYPICAL APPLICATIONS

11.68V

V_IN(-)

(Pin 7)

(ZC)

1.12V

0V

1.8V

1.36V

V_OUT

(Pin 12)

0V

5.9V

V_CA

(Pin 3)

Floats

4.3V

6.1V

V_CA= V_CR

V_CR

(Pin 4)

1.1V

6.5V

V_CS

(Pin 15)

5.1V

A

B

C D

E

Figure 15. Start Mode 300 RPM (Frequency: 10 Hz @ 20 ms)

11.68V

V_IN(-)

(Pin 7)

(ZC)

1.8V

0V

1.86V

1.34V

V_OUT

(Pin 12)

0V

2.2V

V_CA

(Pin 3)

2.18V

2.98V

V_CR

(Pin 4)

1.1V

6.4V

V_CS

(Pin 15)

5.82V

A

B

C D E

25%

Cycle

75%

Cycle

Figure 16. Run Mode 900 RPM (Frequency: 30 Hz @10 ms)

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

TYPICAL APPLICATIONS

11.68V

V_IN(-)

(Pin 7)

(ZC)

1.8V

0V

1.84V

1.36V

V_OUT

(Pin 12)

0V

1.724V

V_CA

(Pin 3)

1.5V

1.46V

V

_CA= V_CR

2.0V

V_CR

(Pin 4)

1.08V

6.42V

6.36V

V_CS

(Pin 15)

6.06V

A

B

C

D

E

Figure 17. Run Mode 2000 RPM (Frequency: 66.67 Hz @ 5.0 ms)

12.2V

V_IN(-)

(Pin 7)

(ZC)

1.8V

0V

1.86V

V_OUT

(Pin 12)

0V

1.31V

V_CA

(Pin 3)

1.17V

1.13V

1.48V

V_CA= V_CR

V_CR

(Pin 4)

1.12V

6.53V

6.51V

V_CS

(Pin 15)

6.46V

A

B

C

D

E

Figure 18. Run Mode 5000 RPM (Frequency: 166.67 Hz @ 2.0 ms)

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

DW SUFFIX

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33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Initial Release

Converted to Freescale format

Added MCZ33094EG/R2 to the Ordering Information

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

Maximum Ratings on page 4.

10/2006

1.0

•

Added note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC

standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels

(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter

the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on

page 4

33094

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

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MC33094

Rev. 1.0

10/2006


型号：	MC33094DW/R2
厂家：	NXP
描述：	SPECIALTY CONSUMER CIRCUIT, PDSO16, 1.27 MM PITCH, PLASTIC, MS-013AA, SOIC-16 光电二极管商用集成电路
文件：	总24页 (文件大小：449K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33094DW/R2 [NXP]

相关型号：

MC33095

MC33095D

MC33095DR2

MC33099

MC33099CDW

MC33099CDW/R2

MC33099CDWR2

MC33099DW

MC33099DW/R2

MC33099DWR1

MC33099DWR2

MC33099DWR2