BUK9504-40A [PHILIPS]
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET;
| 型号： | BUK9504-40A |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET 局域网 开关 脉冲 晶体管 |
| 文件： | 总15页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUK95/96/9E04-40A
TrenchMOS™ logic level FET
Rev. 01 — 24 October 2001
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9504-40A in SOT78 (TO-220AB); BUK9604-40A in SOT404 (D 2-PAK);
BUK9E04-40A in SOT226 (I2-PAK).
2. Features
■ TrenchMOS™ technology
■ Q101 compliant
■ 175 °C rated
■ Logic level compatible.
3. Applications
■ Automotive and general purpose power switching:
◆ 12 V loads
◆ Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pinning - SOT78, SOT404, SOT226 simplified outline and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
mb
mb
[1]
mb
2
drain (d)
3
source (s)
d
s
mb
mounting base,
connected to
drain (d)
g
2
MBB076
1
3
MBK116
1
2 3
MBK112
MBK106
1
2 3
SOT226 (I2-PAK)
SOT78 (TO-220AB) SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
-
Max
40
Unit
V
VDS
ID
drain-source voltage (DC)
[1]
drain current (DC)
Tmb = 25 °C; VGS = 5 V
Tmb = 25 °C
-
198
300
175
4.4
5.9
4
A
Ptot
Tj
total power dissipation
junction temperature
-
W
-
°C
RDSon
drain-source on-state resistance
Tj = 25 °C; VGS = 5 V; ID = 25 A
Tj = 25 °C; VGS = 4.3 V; ID = 25 A
Tj = 25 °C; VGS = 10 V; ID = 25 A
3.5
3.7
2.9
mΩ
mΩ
mΩ
6. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
40
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
-
-
-
-
-
-
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 kΩ
40
V
±15
198
75
V
[1]
[2]
[2]
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
A
A
Tmb = 100 °C; VGS = 5 V; Figure 2
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
794
A
Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
Tmb = 25 °C; Figure 1
-
300
W
−55
−55
+175
+175
°C
°C
operating junction temperature
Source-drain diode
[1]
[2]
IDR
reverse drain current (DC)
Tmb = 25 °C
-
-
-
198
75
A
A
A
IDRM
pulsed reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
unclamped inductive load; ID = 75 A;
794
Avalanche ruggedness
WDSS
non-repetitive avalanche energy
-
1.6
J
VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω;
starting Tmb = 25 °C
[1] Current is limited by power dissipation chip rating
[2] Continuous current is limited by package
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
2 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
03na19
120
200
P
der
I
(%)
D
(A)
100
150
80
60
40
20
0
100
50
0
Capped at 75 A due to package
25
50
75
100
125
150
175
T
200
(ºC)
0
25
50
75 100 125 150 175 200
T
mb
mb (ºC)
V
GS ≥ 4.5 V
Ptot
Pder
=
× 100%
-----------------------
ID
P
°
tot(25 C)
Ider
=
× 100%
-------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
03ne68
3
10
R
= V
/ I
DS D
DSon
I
D
(A)
t
= 10 µs
p
100 µs
1 ms
2
10
Capped at 75 A due to package
10 ms
DC
10
100 ms
1
2
10
1
10
V
(V)
DS
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
3 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Value
Unit
thermal resistance from junction to ambient
vertical in still air; SOT78 and
SOT226 packages
60
K/W
mounted on printed circuit board;
minimum footprint; SOT404
package
50
K/W
K/W
Rth(j-mb)
thermal resistance from junction to mounting Figure 4
base
0.5
7.1 Transient thermal impedance
1
Z
th(j-mb)
(K/W)
δ = 0.5
-1
0.2
10
10
10
0.1
0.05
0.02
-2
-3
t
p
P
δ =
T
Single Shot
t
t
p
T
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
4 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
8. Characteristics
Table 5:
Tj = 25 °C unless otherwise specified
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown
voltage
Characteristics
Conditions
Min
Typ
Max
Unit
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
40
36
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS
Figure 9
Tj = 25 °C
;
1
1.5
2
V
V
V
Tj = 175 °C
Tj = −55 °C
0.5
-
-
-
-
2.3
IDSS
drain-source leakage current VDS = 40 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
-
-
-
0.05
10
µA
µA
nA
-
500
100
IGSS
gate-source leakage current VGS = ±10 V; VDS = 0 V
2
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 25 A;
Figure 7 and 8
Tj = 25 °C
-
-
-
-
3.5
-
4.4
8.3
5.9
4
mΩ
mΩ
mΩ
mΩ
Tj = 175 °C
VGS = 4.3 V; ID = 25 A
VGS = 10 V; ID = 25 A
3.7
2.9
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
VGS = 5 V; VDD = 32 V;
ID = 25 A; Figure 14
-
-
-
-
-
-
-
-
-
-
-
128
13
-
nC
nC
nC
pF
pF
pF
ns
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
-
56
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
6200
1040
680
62
8260
1250
940
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
-
-
-
-
-
309
365
306
4.5
ns
td(off)
tf
turn-off delay time
fall time
ns
ns
Ld
internal drain inductance
from drain lead 6 mm from
package to centre of die
nH
from contact screw on
mounting base to centre of
die SOT78
-
-
-
3.5
2.5
7.5
-
-
-
nH
nH
nH
from upper edge of drain
mounting base to centre of
die SOT404 / SOT226
Ls
internal source inductance
from source lead to source
bond pad
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
5 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
Table 5:
Tj = 25 °C unless otherwise specified
Symbol Parameter
Source-drain diode
Characteristics…continued
Conditions
Min
Typ
Max
Unit
VSD
source-drain (diode forward) IS = 40 A; VGS = 0 V;
-
0.85
1.2
V
voltage
Figure 15
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs
VGS = −10 V; VDS = 30 V
-
-
260
531
-
-
ns
Qr
nC
5
V
= 5 V
GS
400
R
I
8
10
7
6
DSon
(mΩ)
D
(A)
350
300
250
200
150
100
50
4
3
2
4
3
2.2
0
3
6
9
12
15
0
2
4
6
8
10
(V)
V
(V)
GS
V
DS
Tj = 25 °C; tp = 300 µs
Tj = 25 °C; ID = 25 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
03aa27
2
10
R
a
DSon
(mΩ)
V
= 3 V 3.2 3.4 3.6 3.8
4
GS
1.6
8
6
4
2
0
1.2
0.8
0.4
0
5
10
-60
0
60
120
180
0
100
200
300
400
T (oC)
I
(A)
j
D
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
6 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
03aa33
03aa36
2.5
-1
10
I
V
GS(th)
D
(V)
(A)
max
2
-2
10
10
10
10
10
typ
-3
-4
-5
-6
1.5
min
typ
max
min
1
0.5
0
-60
0
60
120
180
0
0.5
1
1.5
2
2.5
V
3
(V)
T (oC)
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
100
14000
C (pF)
g
fs
(S)
12000
80
10000
8000
60
40
20
0
6000
Ciss
4000
2000
Coss
Crss
0
-2
-1
10
2
0
20
40
60
80
10
1
10
10
(V)
I
(A)
V
D
DS
Tj = 25 °C; VDS = 25 V
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
7 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
100
5
4
3
2
1
0
V
(V)
I
GS
D
(A)
80
60
40
V
= 14 V
DD
V
= 32 V
DD
T = 175 ºC
j
T = 25 ºC
j
20
0
0
1
2
3
4
0
20
40
60
80
100
120
Q
140
(nC)
V
(V)
G
GS
VDS = 25 V
Tj = 25 °C; ID = 25 A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 14. Gate-source voltage as a function of turn-on
gate charge; typical values.
03nd90
100
I
S
(A)
80
60
40
T = 175 ºC
j
20
0
T = 25 ºC
j
0.0
0.2
0.4
0.6
0.8
V
1.0
(V)
SD
VGS = 0 V
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
8 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
9. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
c
UNIT
p
q
Q
1
1
1
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-46
00-09-07
01-02-16
SOT78
3-lead TO-220AB
Fig 16. SOT78 (TO-220AB).
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
9 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
99-06-25
01-02-12
SOT404
Fig 17. SOT404 (D2-PAK).
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
10 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
Plastic single-ended package; low-profile 3 lead TO-220AB
SOT226
A
A
1
E
D
1
mounting
base
D
L
1
L
2
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
2
max
L
L
D
D
1
A
1
b
c
E
UNIT
A
b
e
L
Q
1
1
4.5
4.1
1.40
1.27
0.9
0.7
1.3
1.0
0.7
0.4
9.65
8.65
1.5
1.1
10.3
9.7
15.0
13.5
3.30
2.79
2.6
2.2
mm
2.54
3.0
Note
1. Terminals in this zone are not tinned.
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
low-profile
3-lead TO-220AB
99-05-27
99-09-13
SOT226
Fig 18. SOT226 (I2-PAK).
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
11 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
10. Soldering
10.85
10.60
10.50
1.50
7.50
7.40
1.70
2.15
1.50
2.25
8.275
8.35
8.15
4.60
0.30
4.85
5.40
7.95
8.075
3.00
0.20
1.20
1.30
1.55
solder lands
solder resist
occupied area
solder paste
5.08
MSD057
Dimensions in mm.
Fig 19. Reflow soldering footprint for SOT404.
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
12 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
11. Revision history
Table 6:
Revision history
CPCN
Rev Date
Description
01 20011024
-
Product Specification; initial version
9397 750 08649
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 01 — 24 October 2001
13 of 15
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
12. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
13. Definitions
14. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
15. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
14 of 15
9397 750 08649
Product data
Rev. 01 — 24 October 2001
BUK95/96/9E04-40A
Philips Semiconductors
TrenchMOS™ logic level FET
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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© Koninklijke Philips Electronics N.V. 2001.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
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liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 24 October 2001
Document order number: 9397 750 08649
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