935325828528 [NXP]
RISC Microcontroller;
| 型号： | 935325828528 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总96页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5606B
Rev. 5, 11/2017
MPC5606BK
144 LQFP
100 LQFP
20 mm x 20 mm
14 mm x 14 mm
MPC5606BK Microcontroller
Data Sheet
176 LQFP
24 mm x 24 mm
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . 4
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Recommended operating conditions . . . . . . . . . . . . . . . 28
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . 33
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . 45
3.8 Power management electrical characteristics . . . . . . . . 48
3.9 Power consumption in different application modes . . . . 53
3.10 Flash memory electrical characteristics . . . . . . . . . . . . . 54
3.11 Electromagnetic compatibility (EMC) characteristics . . . 56
3.12 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.13 Slow external crystal oscillator (32 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.14 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . 63
3.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.17 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . . 66
3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . 85
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1
Introduction
1.1
Document overview
2
3
This document describes the features of the family and
options available within the family members, and highlights
important electrical and physical characteristics of the device.
1.2
Description
This family of 32-bit system-on-chip (SoC) microcontrollers
is the latest achievement in integrated automotive application
controllers. It belongs to an expanding family of
automotive-focused products designed to address the next
wave of body electronics applications within the vehicle.
The advanced and cost-efficient e200z0 host processor core of
this automotive controller family complies with the Power
Architecture technology and only implements the VLE
®
(variable-length encoding) APU (Auxiliary Processor Unit),
providing improved code density. It operates at speeds of up
to 64 MHz and offers high performance processing optimized
for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture
devices and is supported with software drivers, operating
systems and configuration code to assist with users
implementations.
4
5
6
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
1.3
Device comparison
Table 1 summarizes the functions of the blocks present on the MPC5606BK.
1
Table 1. MPC5606BK family comparison
Feature
MPC5605BK
MPC5606BK
Package
CPU
100 LQFP
144 LQFP
176 LQFP
100 LQFP
144 LQFP
176 LQFP
e200z0h
Execution speed2
Code flash memory
Data flash memory
SRAM
Up to 64 MHz
768 KB
64 KB
1 MB
64 (4 x 16) KB
80 KB
MPU
8-entry
16 ch
Yes
eDMA
10-bit ADC
dedicated3
7 ch
15 ch
29 ch
7 ch
15 ch
29 ch
shared with 12-bit ADC
19 ch
Yes
12-bit ADC
dedicated4
5 ch
shared with 10-bit ADC
19 ch
Total timer I/O5
eMIOS
37 ch,
16-bit
64 ch,
16-bit
37 ch,
16-bit
64 ch,
16-bit
Counter / OPWM / ICOC6
O(I)PWM / OPWFMB / OPWMCB / ICOC7
10 ch
7 ch
O(I)PWM / ICOC8
OPWM / ICOC9
7 ch
13 ch
4
14 ch
33 ch
4
SCI (LINFlex)
SPI (DSPI)
CAN (FlexCAN)
I2C
6
5
8
6
6
5
8
6
3
3
6
1
32 KHz oscillator
GPIO10
Yes
77
121
149
77
121
149
Debug
JTAG
1
2
3
4
5
6
7
8
Feature set dependent on selected peripheral multiplexing; table shows example.
Based on 125 °C ambient operating temperature.
Not shared with 12-bit ADC, but possibly shared with other alternate functions.
Not shared with 10-bit ADC, but possibly shared with other alternate functions.
Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.
Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width
measurement.
9
Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10 Maximum I/O count based on multiplexing with peripherals.
MPC5606BK Microcontroller Data Sheet, Rev. 5
2
NXP Semiconductors
1.4
Block diagram
Figure 1 shows a top-level block diagram of the MPC5606BK.
SRAM
80 KB
Code Flash Data Flash
1.0 MB 64 KB
JTAG
eDMA
(Master)
JTAG Port
Instructions
SRAM
Controller
Flash memory
controller
e200z0h
(Master)
Data
NMI
(Slave)
(Master)
SIUL
Voltage
Regulator
(Slave)
Interrupt
request with
wakeup
functionality
Interrupt requests
from peripheral
(Slave)
NMI
blocks
MPU
Registers
INTC
WKPU
Clocks
CMU
FMPLL
RTC
MC_RGM MC_CGM MC_ME MC_PCU
Peripheral Bridge
SSCM
STM
PIT
BAM
SWT
ECSM
SIUL
8 x
LINFlex
6 x
DSPI
6 x
FlexCAN
64 ch
eMIOS
29 ch 10-bit
ADC
19 ch 10-bit/12-bit
ADC
CTU
I2
C
Reset Control
Interrupt
Request
External
Interrupt
Request
5 ch 12-bit
ADC
IMUX
GPIO &
Pad Control
. . .
. . .
. . .
. . .
. . .
I/O
Legend:
ADC
BAM
Analog-to-Digital Converter
Boot Assist Module
LINFlex
Serial Communication Interface (LIN support)
MC_CGM Clock Generation Module
MC_ME
FlexCAN Controller Area Network
Mode Entry Module
CFlash
CMU
CTU
DFlash
DSPI
Code flash memory
Clock Monitor Unit
Cross Triggering Unit
Data flash memory
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
MPU
NMI
Memory Protection Unit
Non-Maskable Interrupt
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
eDMA
eMIOS
FMPLL
2
I C
IMUX
INTC
JTAG
Interrupt Controller
JTAG controller
Software Watchdog Timer
Wakeup Unit
Figure 1. MPC5606BK block diagram
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
3
2
Package pinouts and signal descriptions
2.1
Package pinouts
The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please see Table 2.
Figure 2 shows the MPC5606BK in the 176 LQFP package.
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
1
2
3
4
5
6
7
8
PA[11]
PA[10]
PA[9]
PA[8]
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
PI[10]
PI[9]
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
176 LQFP
Top view
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
98
97
96
95
94
93
92
91
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
90
89
VSS_HV_ADC0
Figure 2. 176 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
4
NXP Semiconductors
Figure 3 shows the MPC5606BK in the 144 LQFP package.
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
Top view
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
Figure 3. 144 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
5
Figure 4 shows the MPC5606BK in the 100 LQFP package.
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
9
PE[9]
PE[10]
PA[0]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
Top view
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PB[1]
PC[6]
Figure 4. 100 LQFP pinout
MPC5606BK Microcontroller Data Sheet, Rev. 5
6
NXP Semiconductors
2.2
Pin muxing
Table 2 defines the pin list and muxing for this device.
Each entry of Table 2 shows all the possible configurations for each pin, via the alternate functions. The default function
assigned to each pin after reset is indicated by AF0.
Table 2. Functional port pins
Pin number
Port
pin
PCR
Alternate
Function
register function1
100
144
176
LQFP LQFP LQFP
Port A
PA[0]
PA[1]
PA[2]
PA[3]
PCR[0]
PCR[1]
PCR[2]
PCR[3]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKUP[19]4
SIUL
I/O
I/O
O
I/O
I
M
S
S
J
Tristate
Tristate
Tristate
Tristate
12
7
16
11
9
24
19
eMIOS_0
MC_CGM
eMIOS_0
WKUP
AF0
AF1
AF2
AF3
—
GPIO[1]
E0UC[1]
NMI5
SIUL
eMIOS_0
WKUP
—
I/O
I/O
I
—
I
—
WKUP[2]4
WKUP
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
SIUL
eMIOS_0
—
ADC_0
WKUP
I/O
I/O
—
O
5
17
MA[2]
WKUP[3]4
I
AF0
AF1
AF2
AF3
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlex_5
DSPI_1
SIUL
I/O
I/O
O
O
I
68
90
114
—
ADC_1
I
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKUP[9]4
SIUL
eMIOS_0
—
DSPI_1
LINFlex_5
WKUP
I/O
I/O
—
I/O
I
S
Tristate
29
43
51
—
I
PA[5]
PA[6]
PCR[5]
PCR[6]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
LIN4TX
—
SIUL
eMIOS_0
LINFlex_4
—
I/O
I/O
O
M
S
Tristate
Tristate
79
80
118
119
146
147
—
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
LIN4RX
SIUL
eMIOS_0
—
DSPI_1
SIUL
I/O
I/O
—
O
I
—
LINFlex_4
I
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
7
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PA[7]
PCR[7]
PCR[8]
AF0
AF1
AF2
AF3
—
GPIO[7]
E0UC[7]
LIN3TX
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
LINFlex_3
—
SIUL
ADC_1
I/O
I/O
O
—
I
J
Tristate
71
104
128
—
I
PA[8]
AF0
AF1
AF2
AF3
—
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
I/O
I/O
I/O
—
I
S
Input,
weak
pull-up
72
105
129
N/A6
—
I
I
LINFlex_3
PA[9]
PCR[9]
AF0
AF1
AF2
AF3
N/A6
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
O
S
J
Pull-
down
73
74
75
106
107
108
130
131
132
I
PA[10] PCR[10]
PA[11] PCR[11]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
SDA
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
I2C_0
LINFlex_2
ADC_1
I/O
I/O
I/O
O
Tristate
Tristate
I
AF0
AF1
AF2
AF3
—
GPIO[11]
E0UC[11]
SCL
SIUL
eMIOS_0
I2C_0
—
SIUL
I/O
I/O
I/O
—
I
J
—
EIRQ[16]
LIN2RX
ADC1_S[3]
—
—
LINFlex_2
ADC_1
I
I
PA[12] PCR[12]
AF0
AF1
AF2
AF3
—
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
SIUL
—
eMIOS_0
DSPI_1
SIUL
I/O
—
I/O
O
I
S
Tristate
31
45
53
—
DSPI_0
I
PA[13] PCR[13]
PA[14] PCR[14]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
M
M
Tristate
Tristate
30
28
44
42
52
50
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
MPC5606BK Microcontroller Data Sheet, Rev. 5
8
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PA[15] PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKUP
I/O
I/O
I/O
I/O
I
M
Tristate
27
40
48
E0UC[1]
WKUP[10]4
Port B
PB[0] PCR[16]
PB[1] PCR[17]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
I/O
O
I/O
O
M
S
Tristate
Tristate
23
24
31
32
39
40
FlexCAN_0
eMIOS_0
LINFlex_0
AF0
AF1
AF2
AF3
—
GPIO[17]
—
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_0
LINFlex_0
I/O
—
I/O
—
I
E0UC[31]
—
WKUP[4]4
CAN0RX
LIN0RX
—
—
I
I
PB[2] PCR[18]
PB[3] PCR[19]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
SIUL
LINFlex_0
I2C_0
I/O
O
I/O
I/O
M
S
Tristate 100
144
1
176
1
E0UC[30]
eMIOS_0
AF0
AF1
AF2
AF3
—
GPIO[19]
E0UC[31]
SCL
SIUL
eMIOS_0
I2C_0
I/O
I/O
I/O
—
I
Tristate
Tristate
1
—
—
WKUP[11]4
LIN0RX
WKUP
LINFlex_0
—
I
PB[4] PCR[20]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
—
—
—
—
I
I
I
50
72
75
88
91
—
—
ADC0_P[0]
ADC1_P[0]
GPIO[20]
ADC_0
ADC_1
SIUL
—
—
I
I
PB[5] PCR[21]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
—
—
—
—
I
Tristate
53
—
—
ADC0_P[1]
ADC1_P[1]
GPIO[21]
ADC_0
ADC_1
SIUL
—
—
I
I
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
9
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PB[6] PCR[22]
PB[7] PCR[23]
PB[8] PCR[24]
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
Tristate
Tristate
—
54
55
39
76
77
53
92
93
61
—
—
ADC0_P[2]
ADC1_P[2]
GPIO[22]
ADC_0
ADC_1
SIUL
—
—
I
I
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
—
—
—
—
I
—
—
ADC0_P[3]
ADC1_P[3]
GPIO[23]
ADC_0
ADC_1
SIUL
—
—
I
I
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[24]
SIUL
—
—
I
—
—
—
—
I
—
—
—
—
OSC32K_XTAL7 OSC32K
WKUP[25]
ADC0_S[0]
ADC1_S[4]
WKUP
ADC_0
ADC_1
I
I
PB[9] PCR[25]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[25]
SIUL
—
—
I
—
—
—
—
I
I
—
38
52
60
—
—
—
—
OSC32K_EXTAL7 OSC32K
WKUP[26]
ADC0_S[1]
ADC1_S[5]
WKUP
ADC_0
ADC_1
I
I
PB[10] PCR[26]
AF0
AF1
AF2
AF3
—
GPIO[26]
—
SIUL
—
—
I/O
—
—
—
I
J
Tristate
40
54
62
—
—
—
WKUP[8]4
ADC0_S[2]
ADC1_S[6]
WKUP
ADC_0
ADC_1
—
—
I
I
PB[11] PCR[27]
PB[12] PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I
J
J
Tristate
Tristate
—
—
97
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
61
83
101
I
MPC5606BK Microcontroller Data Sheet, Rev. 5
10
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PB[13] PCR[29]
PB[14] PCR[30]
PB[15] PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
J
J
J
Tristate
Tristate
Tristate
63
65
67
85
87
89
103
105
107
I
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
Port C
PC[0]8 PCR[32]
PC[1]8 PCR[33]
PC[2] PCR[34]
AF0
AF1
AF2
AF3
GPIO[32]
SIUL
—
JTAGC
—
I/O
—
I
M
Input,
weak
pull-up
87
82
78
126
121
117
154
149
145
—
TDI
—
—
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
F9 Tristate
—
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
DEBUG[0]
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
SSCM
I/O
I/O
O
O
I
M
S
Tristate
Tristate
SIUL
PC[3] PCR[35]
AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
DEBUG[1]
EIRQ[6]
CAN1RX
CAN4RX
SIUL
DSPI_1
ADC_0
SSCM
SIUL
I/O
I/O
O
O
I
77
92
116
131
144
159
—
—
FlexCAN_1
FlexCAN_4
I
I
PC[4] PCR[36]
AF0
AF1
AF2
AF3
—
GPIO[36]
E1UC[31]
—
DEBUG[2]
EIRQ[18]
SIN_1
SIUL
eMIOS_1
—
SSCM
SIUL
I/O
I/O
—
O
I
M
Tristate
—
—
DSPI_1
FlexCAN_3
I
I
CAN3RX
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
11
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PC[5] PCR[37]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
CAN3TX
DEBUG[3]
EIRQ[7]
SIUL
DSPI_1
FlexCAN_3
SSCM
I/O
O
O
O
I
M
Tristate
91
130
158
SIUL
PC[6] PCR[38]
PC[7] PCR[39]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
E1UC[28]
DEBUG[4]
SIUL
I/O
O
I/O
O
S
S
Tristate
Tristate
25
26
36
37
44
45
LINFlex_1
eMIOS_1
SSCM
AF0
AF1
AF2
AF3
—
GPIO[39]
—
SIUL
—
eMIOS_1
SSCM
LINFlex_1
WKUP
I/O
—
I/O
O
I
E1UC[29]
DEBUG[5]
LIN1RX
—
WKUP[12]4
I
PC[8] PCR[40]
PC[9] PCR[41]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
DEBUG[6]
SIUL
I/O
O
I/O
O
S
S
Tristate
Tristate
99
2
143
2
175
2
LINFlex_2
eMIOS_0
SSCM
AF0
AF1
AF2
AF3
—
GPIO[41]
—
E0UC[7]
DEBUG[7]
WKUP[13]4
LIN2RX
SIUL
—
eMIOS_0
SSCM
WKUP
LINFlex_2
I/O
—
I/O
O
I
—
I
PC[10] PCR[42]
PC[11] PCR[43]
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
I/O
O
O
M
S
Tristate
Tristate
22
21
28
27
36
35
FlexCAN_1
FlexCAN_4
ADC_0
O
AF0
AF1
AF2
AF3
—
GPIO[43]
—
SIUL
—
—
I/O
—
—
O
I
—
MA[2]
ADC_0
WKUP
FlexCAN_1
FlexCAN_4
WKUP[5]4
CAN1RX
CAN4RX
—
—
I
I
PC[12] PCR[44]
PC[13] PCR[45]
AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
S
Tristate
Tristate
97
98
141
142
173
174
—
EIRQ[19]
SIN_2
—
DSPI_2
I
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
12
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PC[14] PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
SCK_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
I
S
Tristate
3
3
3
EIRQ[8]
SIUL
PC[15] PCR[47]
AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
CS0_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
I/O
—
I
M
Tristate
4
4
4
EIRQ[20]
SIUL
Port D
PD[0] PCR[48]
AF0
AF1
AF2
AF3
—
GPIO[48]
—
SIUL
—
—
I
—
—
—
I
I
I
Tristate
Tristate
41
42
63
64
77
78
—
—
—
WKUP[27]
ADC0_P[4]
ADC1_P[4]
WKUP
ADC_0
ADC_1
—
—
I
I
PD[1] PCR[49]
AF0
AF1
AF2
AF3
—
GPIO[49]
—
SIUL
—
—
I
—
—
—
I
—
—
—
WKUP[28]
ADC0_P[5]
ADC1_P[5]
WKUP
ADC_0
ADC_1
—
—
I
I
PD[2] PCR[50]
PD[3] PCR[51]
PD[4] PCR[52]
AF0
AF1
AF2
AF3
—
GPIO[50]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
I
Tristate
Tristate
Tristate
43
44
45
65
66
67
79
80
81
—
—
—
ADC0_P[6]
ADC1_P[6]
—
I
AF0
AF1
AF2
AF3
—
GPIO[51]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
—
—
—
ADC0_P[7]
ADC1_P[7]
—
I
AF0
AF1
AF2
AF3
—
GPIO[52]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
—
—
—
ADC0_P[8]
ADC1_P[8]
—
I
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
13
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PD[5] PCR[53]
PD[6] PCR[54]
PD[7] PCR[55]
PD[8] PCR[56]
PD[9] PCR[57]
PD[10] PCR[58]
PD[11] PCR[59]
PD[12] PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[53]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
46
47
48
49
56
57
58
—
68
69
70
71
78
79
80
—
82
83
84
87
94
95
96
100
—
—
—
ADC0_P[9]
ADC1_P[9]
—
I
AF0
AF1
AF2
AF3
—
GPIO[54]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[10]
ADC1_P[10]
—
I
AF0
AF1
AF2
AF3
—
GPIO[55]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[11]
ADC1_P[11]
—
I
AF0
AF1
AF2
AF3
—
GPIO[56]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[12]
ADC1_P[12]
—
I
AF0
AF1
AF2
AF3
—
GPIO[57]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[13]
ADC1_P[13]
—
I
AF0
AF1
AF2
AF3
—
GPIO[58]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[14]
ADC1_P[14]
—
I
AF0
AF1
AF2
AF3
—
GPIO[59]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
—
—
—
ADC0_P[15]
ADC1_P[15]
—
I
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
I
J
ADC0_S[4]
ADC_0
MPC5606BK Microcontroller Data Sheet, Rev. 5
14
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PD[13] PCR[61]
PD[14] PCR[62]
PD[15] PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
I/O
I/O
—
I
J
J
J
Tristate
Tristate
Tristate
62
64
66
84
86
88
102
104
106
ADC0_S[5]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
O
I/O
—
I
ADC0_S[6]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
O
I/O
—
I
ADC0_S[7]
ADC_0
Port E
PE[0] PCR[64]
AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
SIUL
eMIOS_0
—
I/O
I/O
—
—
I
S
Tristate
6
10
18
—
—
WKUP[6]4
CAN5RX
WKUP
FlexCAN_5
—
I
PE[1] PCR[65]
PE[2] PCR[66]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
M
M
Tristate
Tristate
8
12
20
—
AF0
AF1
AF2
AF3
—
GPIO[66]
E0UC[18]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
89
128
156
—
EIRQ[21]
SIN_1
—
DSPI_1
I
PE[3] PCR[67]
PE[4] PCR[68]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
M
M
Tristate
Tristate
90
93
129
132
157
160
—
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
I/O
—
I
EIRQ[9]
SIUL
PE[5] PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
SIUL
eMIOS_0
DSPI_1
ADC_0
I/O
I/O
I/O
O
M
Tristate
94
133
161
MA[2]
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
15
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PE[6] PCR[70]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M
Tristate
95
139
167
PE[7] PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M
Tristate
96
140
168
PE[8] PCR[72]
PE[9] PCR[73]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
I/O
O
I/O
O
M
S
Tristate
Tristate
9
13
14
21
22
FlexCAN_2
eMIOS_0
FlexCAN_3
AF0
AF1
AF2
AF3
—
GPIO[73]
—
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_2
FlexCAN_3
I/O
—
I/O
—
I
10
E0UC[23]
—
WKUP[7]4
CAN2RX
CAN3RX
—
—
I
I
PE[10] PCR[74]
PE[11] PCR[75]
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
SIUL
LINFlex_3
DSPI_1
eMIOS_1
SIUL
I/O
O
O
I/O
I
S
S
Tristate
Tristate
11
13
15
17
23
25
AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
SIUL
eMIOS_0
DSPI_1
—
LINFlex_3
WKUP
I/O
I/O
O
—
I
—
LIN3RX
—
WKUP[14]4
I
PE[12] PCR[76]
AF0
AF1
AF2
AF3
—
GPIO[76]
—
SIUL
—
eMIOS_1
—
SIUL
DSPI_2
ADC_1
I/O
—
I/O
—
I
J
Tristate
Tristate
76
—
109
103
133
127
E1UC[19]10
—
EIRQ[11]
SIN_2
ADC1_S[7]
—
—
I
I
PE[13] PCR[77]
AF0
AF1
AF2
AF3
GPIO[77]
SOUT_2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
O
I/O
—
S
MPC5606BK Microcontroller Data Sheet, Rev. 5
16
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PE[14] PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
I/O
—
I
S
Tristate
—
112
136
EIRQ[12]
SIUL
PE[15] PCR[79]
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
I/O
—
M
Tristate
—
113
137
Port F
PF[0] PCR[80]
PF[1] PCR[81]
PF[2] PCR[82]
PF[3] PCR[83]
PF[4] PCR[84]
PF[5] PCR[85]
PF[6] PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
J
J
J
J
J
J
J
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
55
56
57
58
59
60
61
63
64
65
66
67
68
69
—
ADC0_S[8]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
—
ADC0_S[9]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
I
—
ADC0_S[10]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
I
—
ADC0_S[11]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
I
—
ADC0_S[12]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
I
—
ADC0_S[13]
ADC_0
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
—
ADC0_S[14]
ADC_0
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
17
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PF[7] PCR[87]
AF0
AF1
AF2
AF3
—
GPIO[87]
—
CS2_1
—
SIUL
—
DSPI_1
—
I/O
—
O
—
I
J
Tristate
—
62
70
ADC0_S[15]
ADC_0
PF[8] PCR[88]
PF[9] PCR[89]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
SIUL
FlexCAN_3
DSPI_0
I/O
O
O
M
S
Tristate
Tristate
—
—
34
33
42
41
CAN2TX
FlexCAN_2
O
AF0
AF1
AF2
AF3
—
GPIO[89]
E1UC[1]
CS5_0
SIUL
eMIOS_1
DSPI_0
—
WKUP
FlexCAN_2
FlexCAN_3
I/O
I/O
O
—
I
—
WKUP[22]4
CAN2RX
CAN3RX
—
—
I
I
PF[10] PCR[90]
PF[11] PCR[91]
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
SIUL
DSPI_0
LINFlex_4
eMIOS_1
I/O
O
O
M
S
Tristate
Tristate
—
—
38
39
46
47
I/O
AF0
AF1
AF2
AF3
—
GPIO[91]
CS2_0
SIUL
DSPI_0
eMIOS_1
—
WKUP
LINFlex_4
I/O
O
I/O
—
I
E1UC[3]
—
WKUP[15]4
LIN4RX
—
I
PF[12] PCR[92]
PF[13] PCR[93]
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlex_5
—
I/O
I/O
O
M
S
Tristate
Tristate
—
—
35
41
43
49
—
AF0
AF1
AF2
AF3
—
GPIO[93]
E1UC[26]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
I
—
—
WKUP[16]4
LIN5RX
WKUP
LINFlex_5
—
I
PF[14] PCR[94]
AF0
AF1
AF2
AF3
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
SIUL
I/O
O
I/O
O
M
Tristate
—
102
126
FlexCAN_4
eMIOS_1
FlexCAN_1
MPC5606BK Microcontroller Data Sheet, Rev. 5
18
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PF[15] PCR[95]
AF0
AF1
AF2
AF3
—
GPIO[95]
E1UC[4]
—
SIUL
eMIOS_1
—
—
SIUL
I/O
I/O
—
—
I
S
Tristate
—
101
125
—
EIRQ[13]
CAN1RX
CAN4RX
—
—
FlexCAN_1
FlexCAN_4
I
I
Port G
PG[0] PCR[96]
PG[1] PCR[97]
AF0
AF1
AF2
AF3
GPIO[96]
CAN5TX
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
I/O
—
M
S
Tristate
Tristate
—
—
98
97
122
121
AF0
AF1
AF2
AF3
—
GPIO[97]
—
E1UC[24]
—
EIRQ[14]
CAN5RX
SIUL
—
eMIOS_1
—
SIUL
FlexCAN_5
I/O
—
I/O
—
I
—
I
PG[2] PCR[98]
PG[3] PCR[99]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
M
S
Tristate
Tristate
—
—
8
7
16
15
—
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
—
I
—
WKUP[17]4
WKUP
PG[4] PCR[100]
PG[5] PCR[101]
AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
M
S
Tristate
Tristate
—
—
6
5
14
13
AF0
AF1
AF2
AF3
—
GPIO[101]
E1UC[14]
—
SIUL
eMIOS_1
—
—
WKUP
DSPI_3
I/O
I/O
—
—
I
—
WKUP[18]4
SIN_3
—
I
PG[6] PCR[102]
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlex_6
—
I/O
I/O
O
M
Tristate
—
30
38
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
19
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PG[7] PCR[103]
AF0
AF1
AF2
AF3
—
GPIO[103]
E1UC[16]
E1UC[30]
—
SIUL
eMIOS_1
eMIOS_1
—
WKUP
LINFlex_6
I/O
I/O
I/O
—
I
S
Tristate
—
29
37
WKUP[20]4
LIN6RX
—
I
PG[8] PCR[104]
PG[9] PCR[105]
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
SIUL
eMIOS_1
LINFlex_7
DSPI_2
SIUL
I/O
I/O
O
I/O
I
S
S
Tristate
Tristate
—
—
26
25
34
33
AF0
AF1
AF2
AF3
—
GPIO[105]
E1UC[18]
—
SIUL
eMIOS_1
—
DSPI_2
WKUP
LINFlex_7
I/O
I/O
—
I/O
I
SCK_2
WKUP[21]4
LIN7RX
—
I
PG[10] PCR[106]
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIUL
eMIOS_0
eMIOS_1
—
I/O
I/O
I/O
—
I
S
Tristate
—
114
138
SIN_4
DSPI_4
PG[11] PCR[107]
PG[12] PCR[108]
PG[13] PCR[109]
PG[14] PCR[110]
PG[15] PCR[111]
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
M
M
M
S
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
115
92
139
116
115
134
135
—
AF0
AF1
AF2
AF3
GPIO[108]
E0UC[26]
SOUT_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
AF0
AF1
AF2
AF3
GPIO[109]
E0UC[27]
SCK_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
I/O
—
91
AF0
AF1
AF2
AF3
GPIO[110]
E1UC[0]
—
SIUL
eMIOS_1
—
I/O
I/O
—
110
111
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
SIUL
eMIOS_1
I/O
I/O
—
—
—
M
—
—
—
—
—
—
Port H
MPC5606BK Microcontroller Data Sheet, Rev. 5
20
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PH[0] PCR[112]
AF0
AF1
AF2
AF3
—
GPIO[112]
E1UC[2]
—
—
SIN_1
SIUL
eMIOS_1
—
—
DSPI_1
I/O
I/O
—
—
I
M
Tristate
—
93
117
PH[1] PCR[113]
PH[2] PCR[114]
PH[3] PCR[115]
PH[4] PCR[116]
PH[5] PCR[117]
PH[6] PCR[118]
PH[7] PCR[119]
PH[8] PCR[120]
PH[9]8 PCR[121]
PH[10]8 PCR[122]
AF0
AF1
AF2
AF3
GPIO[113]
E1UC[3]
SOUT_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
O
M
M
M
M
S
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
88
81
94
118
119
120
162
163
164
165
166
155
148
—
AF0
AF1
AF2
AF3
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
95
AF0
AF1
AF2
AF3
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
96
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
—
SIUL
eMIOS_1
—
I/O
I/O
—
134
135
136
137
138
127
120
—
—
—
AF0
AF1
AF2
AF3
GPIO[117]
E1UC[7]
—
SIUL
eMIOS_1
—
I/O
I/O
—
—
—
—
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
—
SIUL
eMIOS_1
—
I/O
I/O
—
M
M
M
S
MA[2]
ADC_0
O
AF0
AF1
AF2
AF3
GPIO[119]
E1UC[9]
CS3_2
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
MA[1]
O
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
MA[0]
O
AF0
AF1
AF2
AF3
GPIO[121]
SIUL
—
JTAGC
—
I/O
—
I
Input,
weak
pull-up
—
TCK
—
—
AF0
AF1
AF2
AF3
GPIO[122]
SIUL
—
JTAGC
—
I/O
—
I
M
Input,
weak
pull-up
—
TMS
—
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
21
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PH[11] PCR[123]
PH[12] PCR[124]
PH[13] PCR[125]
PH[14] PCR[126]
PH[15] PCR[127]
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
SIUL
I/O
O
I/O
I/O
M
M
M
M
M
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
—
—
140
141
9
DSPI_3
DSPI_4
eMIOS_1
E1UC[5]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
CS1_4
SIUL
I/O
I/O
I/O
—
DSPI_3
DSPI_4
eMIOS_1
E1UC[25]
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
SIUL
I/O
O
I/O
—
DSPI_4
DSPI_3
eMIOS_1
E1UC[26]
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
CS1_3
SIUL
I/O
I/O
I/O
—
10
8
DSPI_4
DSPI_3
eMIOS_1
E1UC[27]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
SIUL
DSPI_5
—
I/O
O
—
—
E1UC[17]
eMIOS_1
Port I
PI[0] PCR[128]
PI[1] PCR[129]
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
—
SIUL
eMIOS_0
—
I/O
I/O
—
S
S
Tristate
Tristate
—
—
—
—
172
171
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[129]
E0UC[29]
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
—
WKUP[24]4
—
—
—
PI[2] PCR[130]
PI[3] PCR[131]
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
—
SIUL
eMIOS_0
—
I/O
I/O
—
S
S
Tristate
Tristate
—
—
—
—
170
169
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[131]
E0UC[31]
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
—
WKUP[23]4
—
—
—
PI[4] PCR[132]
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
S
Tristate
—
—
143
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
22
NXP Semiconductors
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PI[5] PCR[133]
PI[6] PCR[134]
PI[7] PCR[135]
PI[8] PCR[136]
AF0
AF1
AF2
AF3
GPIO[133]
E1UC[29]
SCK_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
S
S
J
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
142
AF0
AF1
AF2
AF3
GPIO[134]
E1UC[30]
CS0_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
11
AF0
AF1
AF2
AF3
GPIO[135]
E1UC[31]
CS1_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
12
AF0
AF1
AF2
AF3
—
GPIO[136]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
108
—
—
—
ADC0_S[16]
PI[9] PCR[137]
PI[10] PCR[138]
PI[11] PCR[139]
AF0
AF1
AF2
AF3
—
GPIO[137]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
J
J
Tristate
Tristate
Tristate
—
—
—
—
—
—
109
110
111
—
—
—
ADC0_S[17]
AF0
AF1
AF2
AF3
—
GPIO[138]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
—
—
—
ADC0_S[18]
AF0
AF1
AF2
AF3
—
GPIO[139]
SIUL
—
—
—
ADC_0
DSPI_3
I/O
—
—
—
I
—
—
—
ADC0_S[19]
SIN_3
—
I
PI[12] PCR[140]
PI[13] PCR[141]
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
—
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
J
J
Tristate
Tristate
—
—
—
—
112
113
—
ADC0_S[20]
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
—
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
—
ADC0_S[21]
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
23
Table 2. Functional port pins (continued)
Function
Pin number
144
Port
pin
PCR
Alternate
register function1
100
176
LQFP LQFP LQFP
PI[14] PCR[142]
AF0
AF1
AF2
AF3
—
GPIO[142]
SIUL
—
—
—
ADC_0
DSPI_4
I/O
—
—
—
I
J
Tristate
—
—
76
—
—
—
ADC0_S[22]
SIN_4
—
I
PI[15] PCR[143]
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
—
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
75
—
ADC0_S[23]
Port J
PJ[0] PCR[144]
PJ[1] PCR[145]
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
—
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
J
Tristate
Tristate
—
—
—
—
74
73
—
ADC0_S[24]
AF0
AF1
AF2
AF3
—
GPIO[145]
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
I
—
—
—
ADC0_S[25]
SIN_5
—
I
PJ[2] PCR[146]
PJ[3] PCR[147]
PJ[4] PCR[148]
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
—
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
J
J
Tristate
Tristate
Tristate
—
—
—
—
—
—
72
71
5
—
ADC0_S[26]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
—
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
—
ADC0_S[27]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
—
M
—
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF3. This is intended to
select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function
is reported as “—”.
2
3
See Table 3.
The RESET configuration applies during and after reset.
MPC5606BK Microcontroller Data Sheet, Rev. 5
24
NXP Semiconductors
4
All WKUP pins also support external interrupt capability. See the WKPU chapter of the MPC5606BK
Microcontroller Reference Manual for further details.
5
6
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
“Not applicable” because these functions are available only while the device is booting. See the BAM chapter
of the MPC5606BK Microcontroller Reference Manual for details.
7
8
Value of PCR.IBE bit must be 0.
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
9
PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode
after reset which has TDO functionality. The reset value of PCR.OBE is 1, but this setting has no impact as long
as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as
reset value of PCR.OBE = 1.
10 Not available in 100LQFP package.
Table 3. Pad types
Description
Type
F
I
Fast
Input only with analog feature
J
Input/output with analog feature
M
S
Medium
Slow
3
Electrical characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by
DD
SS
the internal pull-up and pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where
appropriate.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
25
Table 4. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are
controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the MPC5606BK Microcontroller Reference Manual.
3.2.1
NVUSRO[PAD3V5V] field description
Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration.
1
Table 5. PAD3V5V field description
Value2
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1
2
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.2.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
1
Table 6. OSCILLATOR_MARGIN field description
Value2
Description
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
0
1
1
2
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
MPC5606BK Microcontroller Data Sheet, Rev. 5
26
NXP Semiconductors
3.2.3
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value.
Table 7 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.
1
Table 7. WATCHDOG_EN field description
Value2
Description
0
1
Disable after reset
Enable after reset
1
2
See the MPC5606BK Microcontroller Reference Manual for more information on the NVUSRO register.
The default manufacturing value is ‘1’. This value can be programmed by the customer in Shadow Flash.
3.3
Absolute maximum ratings
Table 8. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
VDD
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
SR Voltage on VDD_HV pins with respect to
–0.3
6.0
ground (VSS
)
VSS_LV SR Voltage on VSS_LV (low voltage digital supply)
—
V
SS – 0.1 VSS + 0.1
V
V
pins with respect to ground (VSS
)
VDD_BV SR Voltage on VDD_BV pin (regulator supply) with
—
Relative to VDD
—
–0.3
–0.3
6.0
respect to ground (VSS
)
VDD + 0.3
VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1
(ADC reference) pin with respect to ground
VSS – 0.1 VSS + 0.1
V
(VSS
)
VDD_ADC SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1
—
Relative to VDD
—
–0.3
6.0
V
V
(ADC reference) with respect to ground (VSS
)
VDD − 0.3 VDD + 0.3
VIN
SR Voltage on any GPIO pin with respect to
–0.3
—
6.0
VDD + 0.3
10
ground (VSS
)
Relative to VDD
—
IINJPAD SR Injected input current on any pin during
overload condition
–10
mA
IINJSUM SR Absolute sum of all injected input currents
during overload condition
—
–50
—
50
70
IAVGSEG SR Sum of all the static I/O current within a supply VDD = 5.0 V 10ꢀ,
segment PAD3V5V = 0
mA
°C
V
DD = 3.3 V 10ꢀ,
—
64
PAD3V5V = 1
TSTORAGE SR Storage temperature
—
–55
150
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
27
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
3.4
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect
3.0
3.6
to ground (VSS
)
2
VSS_LV
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground
—
—
VSS − 0.1 VSS + 0.1
V
(VSS
)
3
VDD_BV
SR Voltage on VDD_BV pin (regulator
supply) with respect to ground (VSS
3.0
3.6
V
V
)
Relative to VDD
VDD − 0.1 VDD + 0.1
VSS − 0.1 VSS + 0.1
VSS_ADC SR Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference) pin
with respect to ground (VSS
—
—
)
4
VDD_ADC
SR Voltage on VDD_HV_ADC0,
3.05
VDD − 0.1 VDD + 0.1
3.6
V
VDD_HV_ADC1 (ADC reference) with
Relative to VDD
respect to ground (VSS
)
VIN
SR Voltage on any GPIO pin with respect
—
VSS − 0.1
—
VDD + 0.1
5
V
to ground (VSS
)
Relative to VDD
—
IINJPAD
IINJSUM
TVDD
SR Injected input current on any pin during
overload condition
—
—
—
−5
mA
SR Absolute sum of all injected input
currents during overload condition
−50
50
SR VDD slope to ensure correct power up6
3.07
0.25 V/µs V/s
MPC5606BK Microcontroller Data Sheet, Rev. 5
28
NXP Semiconductors
Table 9. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
Parameter
Conditions
fCPU < 64 MHz8
Unit
Min
Max
TA C-Grade SR Ambient temperature under bias
−40
85
°C
Part
TJ C-Grade SR Junction temperature under bias
—
−40
−40
−40
−40
−40
110
105
130
125
150
Part
TA V-Grade SR Ambient temperature under bias
fCPU < 64 MHz8
Part
TJ V-Grade SR Junction temperature under bias
—
Part
TA M-Grade SR Ambient temperature under bias
fCPU < 64 MHz8
Part
TJ M-Grade SR Junction temperature under bias
—
Part
1
2
3
100 nF capacitance needs to be provided between each VDD/VSS pair.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal
to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
4
5
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/O DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, the
device is reset.
6
7
8
Guaranteed by device validation
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
This frequency includes the 4ꢀ frequency modulation guard band.
Table 10. Recommended operating conditions (5.0 V)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
0
V
V
1
VDD
SR Voltage on VDD_HV pins with respect to ground
—
Voltage drop2
—
4.5
3.0
5.5
5.5
(VSS
)
3
VSS_LV
SR Voltage on VSS_LV (low voltage digital supply) pins
with respect to ground (VSS
VSS − 0.1 VSS + 0.1
V
V
)
4
VDD_BV
SR Voltage on VDD_BV pin (regulator supply) with
respect to ground (VSS
—
Voltage drop2
Relative to VDD
—
4.5
3.0
3.0
5.5
5.5
)
VDD + 0.1
VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
reference) pin with respect to ground (VSS
VSS − 0.1 VSS + 0.1
V
)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
29
Table 10. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
5
VDD_ADC SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1
—
4.5
3.0
5.5
5.5
V
(ADC reference) with respect to ground (VSS
)
Voltage drop2
Relative to VDD VDD − 0.1 VDD + 0.1
VIN
SR Voltage on any GPIO pin with respect to ground
(VSS
—
Relative to VDD
—
VSS − 0.1
—
VDD + 0.1
5
V
)
—
IINJPAD
SR Injected input current on any pin during overload
condition
−5
mA
IINJSUM SR Absolute sum of all injected input currents during
overload condition
—
−50
50
TVDD
SR VDD slope to ensure correct power up6
—
3.07
0.25 V/µs V/s
TA C-Grade SR Ambient temperature under bias
fCPU < 64 MHz8
−40
85
°C
Part
TJ C-Grade SR Junction temperature under bias
—
−40
−40
−40
−40
−40
110
105
130
125
150
Part
TA V-Grade SR Ambient temperature under bias
fCPU < 64 MHz8
Part
TJ V-Grade SR Junction temperature under bias
—
fCPU < 64 MHz8
—
Part
TA M-Grade SR Ambient temperature under bias
Part
TJ M-Grade SR Junction temperature under bias
Part
1
2
100 nF capacitance needs to be provided between each VDD/VSS pair.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3
4
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should
be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.
5
6
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation. Please refer to Section 3.5.1, External ballast resistor recommendations for
minimum VDD slope to be guaranteed to ensure correct power up in case of external resistor usage.
7
8
Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).
This frequency includes the 4ꢀ frequency modulation guard band.
NOTE
RAM data retention is guaranteed with V
not below 1.08 V.
DD_LV
MPC5606BK Microcontroller Data Sheet, Rev. 5
30
NXP Semiconductors
3.5
Thermal characteristics
3.5.1
External ballast resistor recommendations
External ballast resistor on V
pin helps in reducing the overall power dissipation inside the device. This resistor is
DD_BV
required only when maximum power consumption exceeds the limit imposed by package thermal characteristics.
As stated in Table 11 LQFP thermal characteristics, considering a thermal resistance of 144 LQFP as 48.3 °C/W, at ambient
temperature T = 125 °C, the junction temperature T will cross 150 °C if the total power dissipation is greater than
A
j
(150 – 125)/48.3 = 517 mW. Therefore, the total device current I
at 125 °C/5.5 V must not exceed 94.1 mA (i.e.,
DDMAX
PD/VDD). Assuming an average I (V
) of 15–20 mA consumption typically during device RUN mode, the LV domain
DD DD_HV
consumption I (V
) is thus limited to I
– I (V
), i.e., 80 mA.
DD DD_BV
DDMAX
DD DD_HV
Therefore, respecting the maximum power allowed as explained in Section 3.5.2, Package thermal characteristics, it is
recommended to use this resistor only in the 125 °C/5.5 V operating corner as per the following guidelines:
•
•
•
If I (V
) < 80 mA, then no resistor is required.
DD DD_BV
If 80 mA < I (V
) < 90 mA, then 4 Ω resistor can be used.
DD DD_BV
If I (V
) > 90 mA, then 8 Ω resistor can be used.
DD DD_BV
Using resistance in the range of 4–8 Ω, the gain will be around 10–20% of total consumption on V
. For example, if 8 Ω
DD_BV
resistor is used, then power consumption when I (V
) is 110 mA is equivalent to power consumption when
DD DD_BV
I
(V
) is 90 mA (approximately) when resistor not used.
DD DD_BV
In order to ensure correct power up, the minimum V
to be guaranteed is 30 ms/V. If the supply ramp is slower than this
pin gets triggered leading to device reset. Until the supply reaches
DD_BV
value, then LVDHV3B monitoring ballast supply V
DD_BV
certain threshold, this low voltage monitor generates destructive reset event in the system. This threshold depends on the
maximum I (V
) possible across the external resistor.
DD DD_BV
3.5.2
Package thermal characteristics
1
Table 11. LQFP thermal characteristics
Value
Symbol
C
Parameter
Conditions2
Pin count
Unit
Min Typ Max
RθJA CC D Thermal resistance,
Single-layer board — 1s
100
144
176
100
144
176
100
144
176
100
144
176
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
64 °C/W
64
junction-to-ambient natural
convection3
64
Four-layer board — 2s2p
Single-layer board — 1s
Four-layer board — 2s2p
49.7
48.3
47.3
36 °C/W
38
RθJB CC
Thermal resistance,
junction-to-board4
38
33.6
33.4
33.4
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
31
1
Table 11. LQFP thermal characteristics (continued)
Value
Symbol
C
Parameter
Conditions2
Pin count
Unit
Min Typ Max
RθJC CC
Thermal resistance,
junction-to-case5
Single-layer board — 1s
100
144
176
100
144
176
—
—
—
—
—
—
—
—
—
—
—
—
23 °C/W
23
23
Four-layer board — 2s2p
19.8
19.2
18.8
1
2
3
Thermal characteristics are targets based on simulation.
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C.
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA
and RthJMA
.
4
5
Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB
.
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer. When Greek letters are not available, the symbols are typed as RthJC
.
3.5.3
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:
J
T = T + (P x R )
θJA
Eqn. 1
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
θJA
P is the sum of P
and P (P = P
+ P ).
D
INT
I/O
D
INT I/O
P
P
is the product of I and V , expressed in watts. This is the chip internal power.
DD DD
INT
I/O
represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, P < P
and may be neglected. On the other hand, P may be significant, if the device
I/O
INT
I/O
is configured to continuously drive external modules and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273 °C)
Eqn. 2
Eqn. 3
D
J
Therefore, solving equations 1 and 2:
Where:
2
K = P x (T + 273 °C) + R
x P
D
D
A
θJA
MPC5606BK Microcontroller Data Sheet, Rev. 5
32
NXP Semiconductors
K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2
A.
D
J
iteratively for any value of T .
A
3.6
I/O pad electrical characteristics
I/O pad types
3.6.1
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
Slow pads — are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads — provide transition fast enough for the serial communication channels with controlled current to
reduce electromagnetic emission.
•
•
Fast pads — provide maximum speed. These are used for improved debugging capability.
Input only pads — are associated with ADC channels and 32 kHz low power external crystal oscillator providing low
input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 5.
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
33
Table 12. I/O input DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
—
—
0.65VDD
—
VDD + 0.4
V
VIL SR P Input low level CMOS (Schmitt
Trigger)
−0.4
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
0.1VDD
ILKG CC P Digital input leakage
No injection
on adjacent
pin
TA = −40 °C
TA = 25 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
—
—
2
2
—
—
nA
P
D
D
P
—
5
300
500
1000
40
—
12
70
—
—
—
2
WFI SR P Wakeup input filtered pulse
—
—
—
ns
ns
2
WNFI SR P Wakeup input not filtered pulse
1000
—
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
2
3.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 14 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 16 provides output driver characteristics for I/O pads when in FAST configuration.
Table 13. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current
VIN = VIL, VDD = 5.0 V 10ꢀ PAD3V5V = 0
10
—
—
—
—
—
—
150 µA
250
absolute value
C
PAD3V5V = 12 10
P
VIN = VIL, VDD = 3.3 V 10ꢀ PAD3V5V = 1
10
10
10
10
150
|IWPD| CC P Weak pull-down current
VIN = VIH, VDD = 5.0 V 10ꢀ PAD3V5V = 0
PAD3V5V = 1
150 µA
250
absolute value
C
P
VIN = VIH, VDD = 3.3 V 10ꢀ PAD3V5V = 1
150
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
2
MPC5606BK Microcontroller Data Sheet, Rev. 5
34
NXP Semiconductors
Table 14. SLOW configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level
SLOW configuration
Push Pull IOH = −2 mA,
0.8VDD
—
—
V
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
(recommended)
C
C
I
V
OH = −2 mA,
DD = 5.0 V 10ꢀ,
PAD3V5V = 12
0.8VDD
—
—
—
—
I
V
OH = −1 mA,
VDD − 0.8
DD = 3.3 V 10ꢀ,
PAD3V5V = 1
(recommended)
VOL CC P Output low level
SLOW configuration
Push Pull IOL = 2 mA,
—
—
0.1VDD
V
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
(recommended)
C
C
IOL = 2 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10ꢀ,
PAD3V5V = 12
IOL = 1 mA,
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
(recommended)
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
Table 15. MEDIUM configuration output buffer electrical characteristics
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ Max
VOH CC C Output high level
MEDIUM configuration
Push Pull IOH = −3.8 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
0.8VDD
—
—
V
P
I
OH = −2 mA,
0.8VDD
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
C
C
I
OH = −1 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10ꢀ, PAD3V5V = 12
IOH = −1 mA,
VDD − 0.8
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
C
IOH = −100 µA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
0.8VDD
—
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
35
Table 15. MEDIUM configuration output buffer electrical characteristics (continued)
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ Max
VOL CC C Output low level
MEDIUM configuration
Push Pull IOL = 3.8 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
0.2VDD
V
P
I
V
OL = 2 mA,
DD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
0.1VDD
(recommended)
C
C
IOL = 1 mA,
V
—
—
—
—
0.1VDD
0.5
DD = 5.0 V 10ꢀ, PAD3V5V = 12
IOL = 1 mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
C
I
OL = 100 µA,
—
—
0.1VDD
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
Table 16. FAST configuration output buffer electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VOH CC P Output high level Push Pull IOH = −14 mA,
FAST configuration VDD = 5.0 V 10ꢀ,
0.8VDD
—
—
V
PAD3V5V = 0
(recommended)
C
C
I
OH = −7 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V 10ꢀ,
PAD3V5V = 12
I
OH = −11 mA,
VDD − 0.8
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
(recommended)
VOL CC P Output low level
FAST configuration
Push Pull IOL = 14 mA,
—
—
0.1VDD
V
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
(recommended)
C
C
I
V
OL = 7 mA,
DD = 5.0 V 10ꢀ,
—
—
—
—
0.1VDD
0.5
PAD3V5V = 12
IOL = 11 mA,
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
(recommended)
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
MPC5606BK Microcontroller Data Sheet, Rev. 5
36
NXP Semiconductors
2
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
3.6.4
Output pin transition times
Table 17. Output pin transition times
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
Ttr CC D Output transition time output pin2 CL = 25 pF
SLOW configuration
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
125
50
100
125
10
20
40
12
25
40
4
ns
T
D
D
T
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
D
Ttr CC D Output transition time output pin2 CL = 25 pF
MEDIUM configuration
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
ns
T
D
D
T
CL = 50 pF
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
D
Ttr CC D Output transition time output pin2 CL = 25 pF
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
ns
FAST configuration
CL = 50 pF
6
CL = 100 pF
CL = 25 pF
CL = 50 pF
CL = 100 pF
12
4
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
7
12
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
CL includes device and package capacitances (CPKG < 5 pF).
3.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 18.
Table 19 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
37
Table 18. I/O supply segments
Supply segment
Package
1
2
3
4
5
6
7
8
176 LQFP
144 LQFP
100 LQFP
pin7 –
pin27
pin28 –
pin57
pin59 –
pin85
pin86 –
pin123
pin124 –
pin150
pin151 –
pin6
—
—
pin20 –
pin49
pin51 –
pin99
pin100 –
pin122
pin 123 –
pin19
—
—
—
—
—
—
pin16 –
pin35
pin37 –
pin69
pin70 –
pin83
pin84 –
pin15
—
—
Table 19. I/O consumption
Conditions1
Value
Min Typ Max
Symbol
C
Parameter
Unit
,2
ISWTSLW CC D Dynamic I/O current for
SLOW configuration
CL = 25 pF
CL = 25 pF
CL = 25 pF
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
20 mA
VDD = 3.3 V 10ꢀ,
16
PAD3V5V = 1
2
ISWTMED CC D Dynamic I/O current for
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
29 mA
17
MEDIUM configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
2
ISWTFST CC D Dynamic I/O current for
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
110 mA
50
FAST configuration
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
IRMSSLW CC D Root medium square I/O CL = 25 pF, 2 MHz
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.3 mA
3.2
current for SLOW
CL = 25 pF, 4 MHz
configuration
CL = 100 pF, 2 MHz
6.6
CL = 25 pF, 2 MHz
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
1.6
CL = 25 pF, 4 MHz
2.3
CL = 100 pF, 2 MHz
4.7
IRMSMED CC D Root medium square I/O CL = 25 pF, 13 MHz
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
6.6 mA
13.4
18.3
5
current for MEDIUM
CL = 25 pF, 40 MHz
configuration
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 100 pF, 13 MHz
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
8.5
11
MPC5606BK Microcontroller Data Sheet, Rev. 5
38
NXP Semiconductors
Table 19. I/O consumption (continued)
Conditions1
Value
Symbol
C
Parameter
Unit
Min Typ Max
IRMSFST CC D Root medium square I/O CL = 25 pF, 40 MHz
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22 mA
current for FAST
CL = 25 pF, 64 MHz
configuration
33
CL = 100 pF, 40 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
CL = 100 pF, 40 MHz
56
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
14
20
35
IAVGSEG SR D Sum of all the static I/O
current within a supply
segment
V
DD = 5.0 V 10ꢀ, PAD3V5V = 0
DD = 3.3 V 10ꢀ, PAD3V5V = 1
70 mA
65
V
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 20 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below the 100%.
1
Table 20. I/O weight
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
6
4
4
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
5ꢀ
4ꢀ
4ꢀ
3ꢀ
3ꢀ
—
—
6ꢀ
5ꢀ
4ꢀ
4ꢀ
3ꢀ
—
—
13ꢀ
13ꢀ
13ꢀ
12ꢀ
—
—
—
15ꢀ
15ꢀ
15ꢀ
15ꢀ
—
—
—
—
—
—
—
4ꢀ
4ꢀ
4ꢀ
3ꢀ
18ꢀ
—
16ꢀ
—
—
—
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
39
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
1
—
—
—
—
—
4
—
—
—
—
—
—
—
—
—
4
PH[15]
PH[13]
PH[14]
PI[6]
2ꢀ
3ꢀ
3ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
4ꢀ
3ꢀ
4ꢀ
4ꢀ
—
3ꢀ
3ꢀ
4ꢀ
4ꢀ
4ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
3ꢀ
4ꢀ
4ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PI[7]
—
—
—
—
—
—
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
—
—
10ꢀ
9ꢀ
9ꢀ
9ꢀ
8ꢀ
8ꢀ
8ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
6ꢀ
5ꢀ
—
12ꢀ
11ꢀ
11ꢀ
10ꢀ
10ꢀ
9ꢀ
9ꢀ
9ꢀ
8ꢀ
8ꢀ
7ꢀ
7ꢀ
6ꢀ
—
6ꢀ
—
5ꢀ
—
13ꢀ
—
12ꢀ
—
6ꢀ
—
5ꢀ
—
12ꢀ
—
11ꢀ
—
PE[0]
PA[1]
—
—
—
—
—
—
—
—
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
6ꢀ
6ꢀ
—
6ꢀ
6ꢀ
—
10ꢀ
10ꢀ
—
9ꢀ
9ꢀ
—
—
—
—
—
6ꢀ
—
5ꢀ
—
8ꢀ
—
7ꢀ
—
PE[11]
MPC5606BK Microcontroller Data Sheet, Rev. 5
40
NXP Semiconductors
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
2
1
—
—
1
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
9ꢀ
9ꢀ
—
—
10ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
11ꢀ
11ꢀ
10ꢀ
10ꢀ
9ꢀ
—
—
9ꢀ
9ꢀ
—
—
10ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
11ꢀ
11ꢀ
10ꢀ
10ꢀ
9ꢀ
—
—
9ꢀ
—
—
9ꢀ
—
—
9ꢀ
13ꢀ
—
12ꢀ
—
9ꢀ
13ꢀ
—
12ꢀ
—
—
—
1
9ꢀ
9ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
9ꢀ
14ꢀ
14ꢀ
—
12ꢀ
12ꢀ
—
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
9ꢀ
14ꢀ
14ꢀ
—
12ꢀ
12ꢀ
—
PB[1]
—
—
—
1
PF[9]
—
—
—
—
PF[8]
14ꢀ
15ꢀ
—
13ꢀ
13ꢀ
—
14ꢀ
15ꢀ
—
13ꢀ
13ꢀ
—
PF[12]
PC[6]
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
—
—
—
—
—
—
1
14ꢀ
—
12ꢀ
—
14ꢀ
—
12ꢀ
—
8ꢀ
12ꢀ
—
10ꢀ
—
8ꢀ
12ꢀ
—
10ꢀ
—
—
1
8ꢀ
8ꢀ
8ꢀ
11ꢀ
—
10ꢀ
—
8ꢀ
11ꢀ
—
10ꢀ
—
7ꢀ
9ꢀ
7ꢀ
9ꢀ
PA[13]
PA[12]
7ꢀ
10ꢀ
—
8ꢀ
9ꢀ
—
7ꢀ
10ꢀ
—
8ꢀ
9ꢀ
—
7ꢀ
8ꢀ
7ꢀ
8ꢀ
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
41
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
3
2
2
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
1ꢀ
1ꢀ
5ꢀ
5ꢀ
5ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1ꢀ
1ꢀ
6ꢀ
6ꢀ
6ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1ꢀ
1ꢀ
6ꢀ
6ꢀ
7ꢀ
7ꢀ
8ꢀ
8ꢀ
9ꢀ
9ꢀ
9ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1ꢀ
1ꢀ
7ꢀ
8ꢀ
8ꢀ
9ꢀ
9ꢀ
10ꢀ
10ꢀ
11ꢀ
11ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
2
—
—
—
—
—
—
—
—
—
—
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
MPC5606BK Microcontroller Data Sheet, Rev. 5
42
NXP Semiconductors
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
4
2
2
PD[8]
PB[4]
1ꢀ
1ꢀ
—
—
1ꢀ
1ꢀ
—
—
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
—
—
—
2ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
—
—
—
PB[5]
1ꢀ
—
1ꢀ
—
—
—
PB[6]
1ꢀ
—
1ꢀ
—
—
—
PB[7]
1ꢀ
—
1ꢀ
—
—
—
PD[9]
PD[10]
PD[11]
PB[11]
PD[12]
PB[12]
PD[13]
PB[13]
PD[14]
PB[14]
PD[15]
PB[15]
PI[8]
1ꢀ
—
1ꢀ
—
—
—
1ꢀ
—
1ꢀ
—
—
—
1ꢀ
—
1ꢀ
—
—
—
4
—
—
2
—
—
2
1ꢀ
—
1ꢀ
—
—
—
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
9ꢀ
—
13ꢀ
13ꢀ
13ꢀ
13ꢀ
13ꢀ
13ꢀ
13ꢀ
13ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
11ꢀ
11ꢀ
11ꢀ
10ꢀ
7ꢀ
—
—
—
—
—
—
—
15ꢀ
14ꢀ
14ꢀ
14ꢀ
14ꢀ
13ꢀ
13ꢀ
—
—
17ꢀ
17ꢀ
17ꢀ
17ꢀ
16ꢀ
16ꢀ
15ꢀ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
2
—
—
—
—
PI[9]
—
—
—
—
—
—
PI[10]
PI[11]
PI[12]
PI[13]
PA[3]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11ꢀ
10ꢀ
10ꢀ
6ꢀ
6ꢀ
5ꢀ
5ꢀ
4ꢀ
4ꢀ
—
13ꢀ
12ꢀ
12ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
5ꢀ
4ꢀ
—
—
—
—
—
—
—
—
—
PG[13]
PG[12]
PH[0]
PH[1]
PH[2]
PH[3]
PG[1]
PG[0]
9ꢀ
13ꢀ
13ꢀ
8ꢀ
8ꢀ
7ꢀ
7ꢀ
—
11ꢀ
11ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
—
14ꢀ
14ꢀ
9ꢀ
8ꢀ
7ꢀ
7ꢀ
—
13ꢀ
12ꢀ
8ꢀ
7ꢀ
7ꢀ
6ꢀ
—
9ꢀ
6ꢀ
6ꢀ
7ꢀ
5ꢀ
6ꢀ
5ꢀ
5ꢀ
4ꢀ
5ꢀ
4ꢀ
5ꢀ
4ꢀ
5ꢀ
5ꢀ
5ꢀ
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
43
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
5
3
—
—
—
3
PF[15]
PF[14]
PE[13]
PA[7]
4ꢀ
4ꢀ
4ꢀ
5ꢀ
5ꢀ
6ꢀ
6ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
6ꢀ
5ꢀ
5ꢀ
5ꢀ
—
6ꢀ
—
4ꢀ
5ꢀ
5ꢀ
6ꢀ
6ꢀ
7ꢀ
8ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
5ꢀ
—
5ꢀ
—
4ꢀ
4ꢀ
4ꢀ
5ꢀ
5ꢀ
6ꢀ
6ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
7ꢀ
—
—
6ꢀ
—
4ꢀ
5ꢀ
5ꢀ
6ꢀ
6ꢀ
7ꢀ
8ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
—
—
5ꢀ
—
—
—
—
—
PA[8]
—
—
—
—
PA[9]
—
—
—
—
PA[10]
PA[11]
PE[12]
PG[14]
PG[15]
PE[14]
PE[15]
PG[10]
PG[11]
PH[11]
PH[12]
PI[5]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
—
—
—
—
11ꢀ
—
10ꢀ
—
11ꢀ
—
10ꢀ
—
11ꢀ
—
10ꢀ
—
11ꢀ
—
10ꢀ
—
11ꢀ
10ꢀ
10ꢀ
—
9ꢀ
9ꢀ
9ꢀ
—
11ꢀ
—
9ꢀ
—
—
—
—
—
3
—
—
—
—
—
—
—
—
PI[4]
—
—
—
—
—
—
PC[3]
PC[2]
PA[5]
—
—
6ꢀ
6ꢀ
6ꢀ
5ꢀ
5ꢀ
5ꢀ
—
8ꢀ
7ꢀ
7ꢀ
6ꢀ
6ꢀ
5ꢀ
—
8ꢀ
8ꢀ
—
7ꢀ
7ꢀ
—
8ꢀ
8ꢀ
—
7ꢀ
7ꢀ
—
PA[6]
PH[10]
PC[1]
7ꢀ
19ꢀ
6ꢀ
13ꢀ
7ꢀ
19ꢀ
6ꢀ
13ꢀ
MPC5606BK Microcontroller Data Sheet, Rev. 5
44
NXP Semiconductors
1
Table 20. I/O weight (continued)
176 LQFP
144/100 LQFP
Supply segment
Pad
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
176 LQFP 144 LQFP 100 LQFP
SRC2 = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
6
4
4
PC[0]
PH[9]
PE[2]
PE[3]
PC[5]
PC[4]
PE[4]
PE[5]
PH[4]
PH[5]
PH[6]
PH[7]
PH[8]
PE[6]
PE[7]
PI[3]
6ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
8ꢀ
8ꢀ
8ꢀ
8ꢀ
9ꢀ
—
7ꢀ
8ꢀ
8ꢀ
—
7ꢀ
7ꢀ
10ꢀ
—
8ꢀ
9ꢀ
8ꢀ
—
10ꢀ
10ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
12ꢀ
—
8ꢀ
9ꢀ
9ꢀ
9ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
—
8ꢀ
11ꢀ
12ꢀ
12ꢀ
13ꢀ
13ꢀ
14ꢀ
14ꢀ
—
9ꢀ
10ꢀ
10ꢀ
11ꢀ
11ꢀ
12ꢀ
12ꢀ
12ꢀ
—
9ꢀ
8ꢀ
10ꢀ
10ꢀ
10ꢀ
11ꢀ
11ꢀ
12ꢀ
12ꢀ
12ꢀ
13ꢀ
13ꢀ
13ꢀ
14ꢀ
—
9ꢀ
8ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
10ꢀ
9ꢀ
9ꢀ
—
—
—
—
—
4
10ꢀ
10ꢀ
10ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
—
12ꢀ
12ꢀ
12ꢀ
12ꢀ
12ꢀ
—
11ꢀ
11ꢀ
11ꢀ
11ꢀ
11ꢀ
—
15ꢀ
15ꢀ
16ꢀ
16ꢀ
16ꢀ
—
13ꢀ
13ꢀ
14ꢀ
14ꢀ
14ꢀ
—
—
—
—
—
4
—
—
—
—
4
PI[2]
—
—
—
—
—
—
PI[1]
—
—
—
—
—
—
PI[0]
—
—
—
—
—
—
PC[12]
PC[13]
PC[8]
PB[2]
12ꢀ
—
11ꢀ
—
12ꢀ
13ꢀ
13ꢀ
13ꢀ
18ꢀ
—
15ꢀ
15ꢀ
15ꢀ
15ꢀ
16ꢀ
—
—
—
—
—
11ꢀ
10ꢀ
18ꢀ
16ꢀ
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
SRC is the Slew Rate Control bit in SIU_PCRx
3.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
45
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 6. Start-up reset requirements
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 7. Noise filtering on reset signal
Table 21. Reset electrical characteristics
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
VDD + 0.4
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
V
MPC5606BK Microcontroller Data Sheet, Rev. 5
46
NXP Semiconductors
Table 21. Reset electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
—
−0.4
—
0.35VDD
V
V
V
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
0.1VDD
—
—
—
—
VOL
CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
(recommended)
0.1VDD
Push Pull, IOL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V 10ꢀ, PAD3V5V = 12
Push Pull, IOL = 1 mA,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
(recommended)
Ttr
CC D Output transition time output CL = 25 pF,
pin3 MEDIUM configuration
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
10
20
40
12
25
40
ns
CL = 50 pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
CL = 25 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
CL = 50 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
CL = 100 pF,
VDD = 3.3 V 10ꢀ, PAD3V5V = 1
WFRST SR P RESET input filtered pulse
—
—
—
1000
10
—
—
—
—
—
40
—
ns
ns
µA
WNFRST SR P RESET input not filtered pulse
|IWPU
|
CC P Weak pull-up current absolute VDD = 3.3 V 10ꢀ, PAD3V5V = 1
150
150
250
value
VDD = 5.0 V 10ꢀ, PAD3V5V = 0
10
V
DD = 5.0 V 10ꢀ, PAD3V5V = 14
10
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the MC_RGM chapter of
the MPC5606BK Microcontroller Reference Manual).
3
4
CL includes device and package capacitance (CPKG < 5 pF).
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
are configured in input or in high impedance state.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
47
3.8
Power management electrical characteristics
Voltage regulator electrical characteristics
3.8.1
The device implements an internal voltage regulator to generate the low voltage core supply V
from the high voltage
DD_LV
ballast supply V
. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:
DD_BV
DD
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through V
power pin.
DD
BV: High voltage external power supply for internal ballast module. This must be provided externally through V
DD_BV
power pin. Voltage values should be aligned with V
.
DD
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
C
(LV_COR/LV_CFLA)
REG2
GND
V
DD
V
V
DD_LV
SS_LV
V
DD_BV
DD_LVn
SS_LVn
V
REF
V
DD_BV
V
DD_LV
DEVICE
V
Voltage Regulator
I
V
SS_LV
GND
V
V
V
V
V
DD
SS_LV
DD_LV
SS
DEVICE
GND
(LV_COR/LV_PLL)
GND
C
(supply/IO decoupling)
C
DEC2
REG3
Figure 8. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (C ) to be connected to the device in order to provide a stable
REGn
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5606BK Microcontroller Data Sheet, Rev. 5
48
NXP Semiconductors
Each decoupling capacitor must be placed between each of the three V
/V
supply pairs to ensure stable voltage (see
DD_LV SS_LV
Section 3.4, Recommended operating conditions).
The internal voltage regulator requires controlled slew rate of V /V
as described in Figure 9.
DD DD_BV
VDD_HV
V
(MAX)
DD_HV
V
(MIN)
DD_HV
POWER UP
FUNCTIONAL RANGE
POWER DOWN
Figure 9. V and V
maximum slope
DD_BV
DD
When STANDBY mode is used, further constraints apply to the V /V
in order to guarantee correct regulator
DD DD_BV
functionality during STANDBY exit. This is described in Figure 10.
STANDBY regulator constraints should normally be guaranteed by implementing equivalent of C
capacitance on
STDBY
application board (capacitance and ESR typical values), but would actually depend on the exact characteristics of the
application’s external regulator.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
49
VDD_HV
VDD_HV
V
(MAX)
DD_HV
d
dt
VDD(STDBY)
ΔVDD(STDBY)
ΔVDD(STDBY)
V
(MIN)
DD_HV
d
dt
VDD(STDBY)
VDD_LV
VDD_LV(NOMINAL)
0V
Figure 10. V and V
supply constraints during STANDBY mode exit
DD_BV
DD
Table 22. Voltage regulator electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CREGn
RREG
SR — Internal voltage regulator external
capacitance
—
—
200
—
500
nF
Ω
SR — Stability capacitor equivalent serial
resistance
—
—
0.2
—
CDEC1
SR — Decoupling capacitance2 ballast
VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to
5.5 V
1003
4704
nF
V
DD_BV/VSS_LV pair:
400
10
—
—
—
VDD_BV = 3 V to 3.6 V
CDEC2
VMREG
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
100
nF
V
CC P Main regulator output voltage
Before exiting from
reset
—
1.32
After trimming
—
1.15
—
1.28
—
1.32
150
IMREG
SR — Main regulator current provided to
VDD_LV domain
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
50
NXP Semiconductors
Table 22. Voltage regulator electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
IMREGINT
CC D Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
2
1
mA
VLPREG
ILPREG
CC P Low power regulator output voltage After trimming
1.15
—
1.23
—
1.32
15
V
SR — Low power regulator current provided
to VDD_LV domain
—
mA
ILPREGINT
CC D Low power regulator module current ILPREG = 15 mA;
—
—
—
5
600
—
µA
consumption
TA = 55 °C
—
ILPREG = 0 mA;
TA = 55 °C
VULPREG
IULPREG
CC P Ultra low power regulator output
voltage
After trimming
1.15
—
1.23
—
—
2
1.32
5
V
SR — Ultra low power regulator current
provided to VDD_LV domain
—
mA
µA
IULPREGINT
CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
—
100
—
IULPREG = 0 mA;
TA = 55 °C
—
IDD_BV
CC D Inrush average current on VDD_BV
during power-up5
—
—
—
—
3006
250
mA
SR — Maximum slope on VDD
—
—
mV/µs
d
VDD
dt
SR — Maximum instant variation on VDD
during STANDBY exit
—
—
—
—
—
—
30
15
mV
ΔVDD(STDBY ))
SR — Maximum slope on VDD during
STANDBY exit
mV/µs
d
VDD(STDBY)
dt
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
3
4
This value is acceptable to guarantee operation from 4.5 V to 5.5 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating
range.
5
6
Inrush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external capacitances
to be load).
The duration of the inrush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
3.8.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the V and the V
voltage while device is supplied:
DD
DD_LV
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
51
•
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state
DD
LVDHV3 monitors V to ensure device reset below minimum functional supply
DD
LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range
DD
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
NOTE
When enabled, power domain No. 2 is monitored through LVDLVBKP.
V
DD
V
V
LVDHVxH
LVDHVxL
RESET
Figure 11. Low voltage monitor vs. reset
Table 23. Low voltage monitor electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
VPORUP
VPORH
SR D Supply for functional POR module
CC P Power-on reset threshold
TA = 25 °C,
after trimming
1.0
1.5
—
—
—
—
—
—
—
—
—
—
—
5.5
2.6
V
VLVDHV3H CC T LVDHV3 low voltage detector high threshold
VLVDHV3L CC P LVDHV3 low voltage detector low threshold
2.95
2.9
2.6
—
VLVDHV3BH CC T LVDHV3B low voltage detector high threshold
VLVDHV3BL CC P LVDHV3BL low voltage detector low threshold
VLVDHV5H CC T LVDHV5 low voltage detector high threshold
2.95
2.9
2.6
—
4.5
VLVDHV5L
CC P LVDHV5 low voltage detector low threshold
3.8
1.08
1.08
4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
—
1.14
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
MPC5606BK Microcontroller Data Sheet, Rev. 5
52
NXP Semiconductors
3.9
Power consumption in different application modes
Table 24 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
1
Table 24. Electrical characteristics in different application modes
Value
Symbol
C
Parameter
Conditions2
Unit
Min Typ Max
3
IDDMAX CC C RUN mode maximum average
current
—
—
81 1304 mA
5
IDDRUN CC T RUN mode typical average
fCPU = 8 MHz
fCPU = 16 MHz
CPU = 32 MHz
—
—
—
—
—
—
—
12
27
40
54
67
10
15
—
—
mA
current6
T
C
f
—
P
fCPU = 48 MHz
fCPU = 64 MHz
95
P
120
IDDHALT CC C HALT mode current7
Slow internal RC
oscillator (128 kHz)
running
TA = 25 °C
15 mA
28
P
TA = 125 °C
IDDSTOP CC P STOP mode current8
Slow internal RC
oscillator (128 kHz)
running
TA = 25 °C
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = 25 °C
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = 25 °C
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
130 500 µA
D
180
1
—
5
D
mA
µA
D
3
9
P
5
14
80
—
—
IDDSTDBY2 CC P STANDBY2 mode current9
Slow internal RC
oscillator (128 kHz)
running
17
30
110
C
C
C
280 950
460 1700
C
IDDSTDBY1 CC C STANDBY1 mode current10
Slow internal RC
oscillator (128 kHz)
running
12
24
48
50
—
—
µA
C
C
C
C
150 500
260
—
1
Except for IDDMAX, all consumptions in this table apply to VDD_BV only and do not include VDD_HV
.
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components:
IDDMAX = IDD(VDD_BV) + IDD(VDD_HV) + IDD(VDD_HV_ADC). It does not include a fourth component linked to I/Os
toggling which is highly dependent on the application. The given value is thought to be a worst case value
(64 MHz at 125 °C) with all peripherals running, and code fetched from code flash while modify operation on-going
on data flash. Note that this value can be significantly reduced by the application: switch off unused peripherals
(default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low
power mode when possible.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
53
4
5
6
Higher current may be sunk by device during power-up and standby exit. Please refer to inrush current in Table 22.
RUN current measured with typical application with accesses on both Flash and RAM.
Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and
LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and
running at max frequency, periodic SW/WDG timer reset enabled.
7
Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance:
0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI:
instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1
OFF. ADC0 ON but no conversion except two analog watchdogs.
8
9
Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum
consumption, all possible modules switched off.
10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules
switched off.
3.10 Flash memory electrical characteristics
3.10.1 Program/erase characteristics
Table 25 shows the program and erase characteristics.
Table 25. Program and erase specifications
Value
Symbol
C
Parameter
Conditions
Unit
µs
Initial
max2
Min Typ1
Max3
Tdwprogram CC C Double word (64 bits) program time4
Code Flash
Data Flash
Code Flash
Data Flash
Code Flash
Data Flash
Code Flash
—
—
—
—
—
—
—
18
22
50
500
T16Kpperase
T32Kpperase
T32Kpperase
T128Kpperase
T128Kpperase
16 KB block preprogram and erase time
32 KB block preprogram and erase time
200 500
300
5000
5000
ms
ms
300 600
400
32 KB block preprogram and erase time for
sector B0F4
600 1200 10000 ms
128 KB block preprogram and erase time
Code Flash
Data Flash
600 1300 7500
800
ms
128 KB block preprogram and erase time for Code Flash
sector B0F5
1200 2600 15000 ms
Teslat
D Erase Suspend Latency
—
—
—
—
30
—
—
30
—
—
µs
TESRT
C Erase Suspend Request Rate
Code Flash 20
Data Flash 10
ms
MPC5606BK Microcontroller Data Sheet, Rev. 5
54
NXP Semiconductors
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 26. Flash module life
Value
Symbol
C
Parameter
Conditions
Unit
Min
Typ
Max
P/E
CC C Number of program/erase
cycles per block for 16 KB
blocks over the operating
temperature range (TJ)
—
100000
—
—
cycles
P/E
P/E
CC C Number of program/erase
cycles per block for 32 KB
blocks over the operating
temperature range (TJ)
—
—
10000
1000
100000
100000
—
—
cycles
cycles
CC C Number of program/erase
cycles per block for 128 KB
blocks over the operating
temperature range (TJ)
Retention CC C Minimum data retention at 85 Blocks with
20
10
—
—
—
—
years
years
°C average ambient
0–1,000 P/E cycles
temperature1
Blocks with
1,001–10,000 P/E
cycles
Blocks with
5
—
—
years
10,001–100,000 P/E
cycles
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 27. Flash read access timing
Symbol
fREAD
C
Parameter
Conditions1
Max
Unit
CC P Maximum frequency for Flash reading
2 wait states
1 wait state
0 wait states
64
40
20
MHz
C
C
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
3.10.2 Flash power supply DC characteristics
Table 28 shows the power supply DC characteristics on external supply.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
55
Table 28. Flash power supply DC electrical characteristics
Conditions1
Value
Symbol
Parameter
Unit
Min Typ Max
ICFREAD CC Sum of the current consumption on Flash module read
VDDHV and VDDBV on read access
fCPU = 64 MHz2
Code Flash
Data Flash
Code Flash
Data Flash
—
—
—
—
—
—
—
—
33 mA
33
IDFREAD
ICFMOD CC Sum of the current consumption on Program
52 mA
33
VDDHV and VDDBV on matrix
modification (program/erase)
/Erase on-going while
IDFMOD
reading Flash registers
f
CPU = 64 MHz2
—
ICFLPW CC Sum of the current consumption on
Code Flash
Data Flash
—
—
—
—
1.1 mA
900 µA
VDDHV and VDDBV during Flash low
power mode
IDFLPW
ICFPWD CC Sum of the current consumption on
—
Code Flash
Data Flash
—
—
—
—
150 µA
150
VDDHV and VDDBV during Flash power
IDFPWD
down mode
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = –40 to 125 °C, unless otherwise specified.
fCPU 64 MHz can be achieved at up to 125 °C.
3.10.3 Start-up/Switch-off timings
Table 29. Start-up time/Switch-off time
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
TFLARSTEXIT
TFLALPEXIT
TFLAPDEXIT
CC T Delay for Flash module to exit reset mode
—
—
—
—
—
—
—
—
—
125 µs
0.5
CC T Delay for Flash module to exit low-power mode
CC T Delay for Flash module to exit power-down
mode
30
TFLALPENTRY CC T Delay for Flash module to enter low-power
mode
—
—
—
—
—
—
0.5
1.5
TFLAPDENTRY CC T
Delay for Flash module to enter power-down
mode
1
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
3.11 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.11.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
MPC5606BK Microcontroller Data Sheet, Rev. 5
56
NXP Semiconductors
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for the application.
•
Software recommendations − The software flowchart must include the management of runaway conditions such as:
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials − Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
3.11.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1
standard, which specifies the general conditions for EMI measurements.
1,2
Table 30. EMI radiated emission measurement
Value
Symbol
C
Parameter
Conditions
Unit
Min Typ Max
—
SR — Scan range
—
0.150
—
1000 MHz
fCPU
SR — Operating frequency
—
64
1.28
—
—
—
MHz
V
VDD_LV SR — LV operating voltages
SEMI CC T Peak level
—
—
VDD = 5 V, TA = 25 °C, No PLL frequency
—
18 dBµV
LQFP144 package
Test conforming to IEC
61967-2,
modulation
2ꢀ PLL frequency
modulation
—
—
14 dBµV
fOSC = 8 MHz/fCPU
64 MHz
=
1
2
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
3.11.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
3.11.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts×(n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
57
1,2
Table 31. ESD absolute maximum ratings
Symbol
Ratings
Conditions
TA = 25 °C
Class
Max value3
Unit
VESD(HBM) Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production
3.11.3.2 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 32. Latch-up results
Symbol
Parameter
Static latch-up class
Conditions
Class
LU
TA = 125 °C
II level A
conforming to JESD 78
3.12 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 12 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 33 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
MPC5606BK Microcontroller Data Sheet, Rev. 5
58
NXP Semiconductors
EXTAL
C1
C2
EXTAL
XTAL
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
Table 33. Crystal description
Shunt
capacitance
between
xtalout
Crystal
equivalent
series
resistance
ESR Ω
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
Nominal
frequency
(MHz)
NDK crystal
reference
(pF)1
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
1
2
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
59
S_MTRANS bit (ME_GS register)
1
0
V
XTAL
1/f
MXOSC
V
MXOSC
90ꢀ
10ꢀ
V
MXOSCOP
T
valid internal clock
MXOSCSU
Figure 13. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
oscillator
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
OSCILLATOR_MARGIN = 0
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
transconductance
CC P
CC C
CC C
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
VDD = 3.3 V 10ꢀ,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
VDD = 5.0 V 10ꢀ,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
VFXOSC
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC P Oscillation operating point
—
—
—
—
0.95
2
V
2
IFXOSC
CC T Fast external crystal
oscillator consumption
3
mA
MPC5606BK Microcontroller Data Sheet, Rev. 5
60
NXP Semiconductors
Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
TFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6
ms
f
OSC = 16 MHz,
—
—
—
—
1.8
OSCILLATOR_MARGIN = 1
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
0.65VDD
−0.4
VDD + 0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
Oscillator bypass mode
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals).
3.13 Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL
OSC32K_EXTAL
C1
C2
R
P
OSC32K_XTAL
OSC32K_XTAL
DEVICE
DEVICE
Figure 14. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
61
l
C0
Crystal
Rm
Lm
Cm
C1
C2
C1
C2
Figure 15. Equivalent circuit of a quartz crystal
1
Table 35. Crystal motional characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
Motional capacitance
—
—
—
—
—
18
11.796
—
—
28
KH
fF
Cm
2
C1/C2 Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground2
—
pF
AC coupled at C0 = 2.85 pF4
AC coupled at C0 = 4.9 pF4
AC coupled at C0 = 7.0 pF4
AC coupled at C0 = 9.0 pF4
—
—
—
—
—
—
—
—
65
50
35
30
kΩ
3
Rm
Motional resistance
1
2
The crystal used is Epson Toyocom MC306.
This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to
ground. It includes all the parasitics due to board traces, crystal and package.
3
4
Maximum ESR (Rm) of the crystal is 50 kΩ
C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
MPC5606BK Microcontroller Data Sheet, Rev. 5
62
NXP Semiconductors
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
1/f
LPXOSC32K
V
LPXOSC32K
90ꢀ
10ꢀ
T
valid internal clock
LPXOSC32KSU
Figure 16. Slow external crystal oscillator (32 kHz) electrical characteristics
Table 36. Slow external crystal oscillator (32 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fSXOSC
SR — Slow external crystal oscillator
frequency
—
32
32.768
40
kHz
VSXOSC
CC T Oscillation amplitude
—
—
—
—
2.1
2.5
—
—
V
ISXOSCBIAS CC T Oscillation bias current
µA
µA
ISXOSC
CC T Slow external crystal oscillator
consumption
—
—
8
TSXOSCSU CC T Slow external crystal oscillator
start-up time
—
—
22
s
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
3.14 FMPLL electrical characteristics
The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system clock from the
FXOSC or FIRC sources.
Table 37. FMPLL electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fPLLIN SR — FMPLL reference clock2
—
—
4
—
—
64
60
MHz
ꢀ
ΔPLLIN SR — FMPLL reference clock duty
40
cycle2
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
63
Table 37. FMPLL electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
fPLLOUT CC P FMPLL output clock frequency
—
—
16
—
—
64
MHz
3
fVCO
CC P VCO frequency without
frequency modulation
256
512 MHz
P VCO frequency with frequency
modulation
—
245.76
—
532.48
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
tLOCK CC P FMPLL lock time
—
—
—
—
—
40
—
—
—
644 MHz
150 MHz
20
Stable oscillator (fPLLIN = 16 MHz)
fsys maximum
100
4
µs
ꢀ
ΔtSTJIT CC — FMPLL short term jitter5
ΔtLTJIT CC — FMPLL long term jitter
–4
—
—
fPLLCLK at 64 MHz, 4000 cycles
TA = 25 °C
10
4
ns
IPLL
CC C FMPLL consumption
mA
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN
Frequency modulation is considered 4ꢀ.
.
3
4
5
fCPU 64 MHz can be achieved only at up to 105 °C.
Short term jitter is measured on the clock rising edge at cycle n and n + 4.
3.15 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics
Value
Symbol
fFIRC
2,
C
Parameter
Conditions1
Unit
Min
Typ
Max
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
—
12
—
16
—
20
MHz
SR —
—
IFIRCRUN
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
—
—
200
µA
µA
µA
frequency current in running
mode
IFIRCPWD CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
10
down mode
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C sysclk = off
frequency and system clock
—
—
—
—
—
500
600
700
900
1250
—
—
—
—
—
sysclk = 2 MHz
current in stop mode
sysclk = 4 MHz
sysclk = 8 MHz
sysclk = 16 MHz
MPC5606BK Microcontroller Data Sheet, Rev. 5
64
NXP Semiconductors
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
TFIRCSU CC C Fast internal RC oscillator
start-up time
VDD = 5.0 V 10ꢀ
—
1.1
2.0
µs
ꢀ
ΔFIRCPRE CC C Fast internal RC oscillator
precision after software
TA = 25 °C
TA = 25 °C
−1
—
1
5
trimming of fFIRC
ΔFIRCTRIM CC C Fast internal RC oscillator
—
1.6
—
ꢀ
ꢀ
trimming step
ΔFIRCVAR CC C Fast internal RC oscillator
variation over temperature and
supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
—
−5
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
3.16 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
—
100
—
128
—
—
150
5
kHz
frequency
SR —
2,
ISIRC
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
µA
µs
ꢀ
TSIRCSU CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V 10ꢀ
time
—
−2
8
12
2
ΔSIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C
—
2.7
—
after software trimming of fSIRC
ΔSIRCTRIM CC C Slow internal RC oscillator trimming
—
—
—
10
step
ΔSIRCVAR CC C Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
−10
ꢀ
respect to fSIRC at TA = 55 °C in high
frequency configuration
1
2
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
65
3.17 ADC electrical characteristics
3.17.1 Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error OSE
Figure 17. ADC_0 characteristic and error definitions
3.17.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
MPC5606BK Microcontroller Data Sheet, Rev. 5
66
NXP Semiconductors
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being
S
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 kΩ is obtained (R
S
EQ
= 1 / (fc × C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
S
partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit
S
S
F
L
SW
AD
must be designed to respect the Equation 4:
Eqn. 4
R + R + R + R
+ R
S
F
L
SW
AD
1
2
V • -------------------------------------------------------------------------- < -- LSB
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R
SW
and R ) can be neglected with respect to external resistances.
AD
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 18. Input equivalent circuit (precise channels)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
67
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R
R
C
R
R
R
C
C
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions R
Sampling Switch Impedance
S
F
F
L
and R
)
SW2
SW
AD
P
SW1
Pin Capacitance (three contributions, C , C and C )
Sampling Capacitance
P1
P2
P3
S
Figure 19. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 18): A charge sharing phenomenon
A
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
V
CS
V
A
ΔV < 0.5 LSB
V
A2
1
2
τ1 < (RSW + RAD) CS << TS
V
A1
τ
2 = RL (CS + CP1 + CP2)
T
t
S
Figure 20. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
MPC5606BK Microcontroller Data Sheet, Rev. 5
68
NXP Semiconductors
Eqn. 5
C • C
P
S
τ
= (R
+ R
) • --------------------
AD
1
SW
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T
is always much longer than the internal time constant:
S
Eqn. 6
τ < (R
+ R
) • C « T
AD S S
1
SW
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
Eqn. 7
V
• (C + C + C ) = V • (C + C
)
P2
A1
S
P1
P2
A
P1
2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 8
τ < R • (C + C + C )
P1 P2
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time T , a constraints on R sizing is obtained:
S
L
Eqn. 9
10 • τ = 10 • R • (C + C + C ) < T
P1 P2 S
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 10
V
• (C + C + C + C ) = V • C + V • (C + C + C )
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as antialiasing.
S
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
69
Analog source bandwidth (VA)
Noise
T
C < 2 RFCF (Conversion rate vs. filter pole)
fF = f0 (Anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = Conversion rate)
fF
f0
fC
f
f
Figure 21. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the antialiasing filter, f ), according
0
F
to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater than or
C
0
at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T , which
C
C
S
is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific
channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the sampling time
F
F
T , so the charge level on C cannot be modified by the analog signal source during the time in which the sampling switch is
S
S
closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A2
P1
F
V
C
+ C + C + C
A
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
ADC_0 (10-bit)
> 2048 • C
Eqn. 12
Eqn. 13
C
F
S
ADC_1 (12-bit)
> 8192 • C
C
F
S
MPC5606BK Microcontroller Data Sheet, Rev. 5
70
NXP Semiconductors
3.17.3 ADC electrical characteristics
Table 40. ADC input leakage current
Value
Typ
Symbol C
Parameter
Conditions
Unit
Min
Max
ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin
—
—
1
1
—
—
nA
C
D
C
P
TA = 25 °C
TA = 85°C
3
100
200
400
TA = 105 °C
TA = 125 °C
—
—
8
45
Table 41. ADC_0 conversion characteristics (10-bit ADC_0)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VSS_ADC0 SR — Voltage on VSS_HV_ADC0
—
−0.1
—
0.1
V
(ADC_0 reference) pin with
2
respect to ground (VSS
)
VDD_ADC0 SR — Voltage on VDD_HV_ADC pin
(ADC reference) with respect
—
VDD − 0.1
—
VDD + 0.1
V
to ground (VSS
)
VAINx
SR — Analog input voltage3
—
—
—
—
VSS_ADC0
− 0.1
—
—
—
VDD_ADC0
+ 0.1
V
IADC0pwd SR — ADC_0 consumption in power
down mode
—
—
50
µA
mA
IADC0run SR — ADC_0 consumption in
running mode
5
fADC0 SR — ADC_0 analog frequency
6
—
—
32 + 4ꢀ MHz
Δ
ADC0_SYS SR — ADC_0 digital clock duty cycle ADCLKSEL = 14
45
55
ꢀ
(ipg_clk)
tADC0_PU SR — ADC_0 power up delay
tADC0_S CC T Sample time5
—
—
—
—
1.5
µs
µs
fADC = 32 MHz,
0.5
ADC0_conf_sample_input = 17
fADC = 6 MHz,
INPSAMP = 255
—
0.625
—
—
—
—
42
—
3
tADC0_C CC P Conversion time6
fADC = 32 MHz,
ADC_conf_comp = 2
µs
pF
CS
CC D ADC_0 input sampling
capacitance
—
CP1
CP2
CP3
CC D ADC_0 input pin capacitance 1
CC D ADC_0 input pin capacitance 2
CC D ADC_0 input pin capacitance 3
—
—
—
—
—
—
—
—
—
3
1
1
pF
pF
pF
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
71
Table 41. ADC_0 conversion characteristics (10-bit ADC_0) (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
RSW1 CC D Internal resistance of analog
source
—
—
—
3
kΩ
kΩ
kΩ
mA
RSW2 CC D Internal resistance of analog
source
—
—
—
—
−5
−5
—
—
—
—
2
2
5
5
RAD
CC D Internal resistance of analog
source
IINJ
SR — Input current Injection
Current injection VDD =
on one ADC_0 3.3 V 10ꢀ
input, different
VDD
5.0 V 10ꢀ
=
from the
converted one
| INL | CC T Absolute value for integral
nonlinearity
No overload
No overload
—
—
0.5
0.5
1.5
1.0
LSB
LSB
| DNL | CC T Absolute differential
nonlinearity
| OFS | CC T Absolute offset error
| GNE | CC T Absolute gain error
TUEP CC P Total unadjusted error7 for
—
—
—
—
−2
−3
0.5
0.6
0.6
—
—
—
2
LSB
LSB
LSB
Without current injection
With current injection
precise channels, input only
T
3
pins
TUEX CC T Total unadjusted error7 for
Without current injection
With current injection
−3
−4
1
3
4
LSB
extended channel
T
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = −40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4
5
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the
end of the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC0_S depend on programming.
6
7
This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5606BK Microcontroller Data Sheet, Rev. 5
72
NXP Semiconductors
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
V
(LSB
)
in(A)
ideal
Offset Error OSE
Figure 22. ADC_1 characteristic and error definitions
Table 42. ADC_1 conversion characteristics (12-bit ADC_1)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VSS_ADC1 SR — Voltage on VSS_HV_ADC1
—
–0.1
—
0.1
V
(ADC_1 reference) pin with
2
respect to ground (VSS
)
VDD_ADC1 SR — VoltageonVDD_HV_ADC1pin
(ADC_1 reference) with
—
VDD – 0.1
—
VDD + 0.1
V
respect to ground (VSS
)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
73
Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VAINx
SR — Analog input voltage3
—
—
—
VSS_ADC1
– 0.1
—
VDD_ADC1
+ 0.1
V
IADC1pwd SR — ADC_1 consumption in power
down mode
—
—
—
50
µA
mA
IADC1run SR — ADC_1consumptioninrunning
mode
—
6
fADC1
SR — ADC_1 analog frequency
VDD = 3.3 V
VDD = 5 V
—
3.33
3.33
—
—
—
—
—
20 + 4ꢀ MHz
32 + 4ꢀ
tADC1_PU SR — ADC_1 power up delay
1.5
—
µs
ns
tADC1_S CC T Sample time4
VDD = 3.3 V
f
ADC1 = 20 MHz,
ADC1_conf_sample_input = 12
600
Sample time4
VDD = 5.0 V
f
ADC1= 32 MHz,
500
—
—
—
—
—
—
—
—
—
76.2
76.2
—
ADC1_conf_sample_input = 17
Sample time4
VDD = 3.3 V
fADC1= 3.33 MHz,
ADC1_conf_sample_input = 255
µs
Sample time4
VDD = 5.0 V
f
ADC1= 3.33 MHz,
—
ADC1_conf_sample_input = 255
tADC1_C CC P Conversion time5
VDD = 3.3 V
f
ADC1 = 20MHz,
2.4
1.5
—
µs
µs
µs
µs
ADC1_conf_comp = 0
Conversion time5
VDD = 5.0 V
fADC 1 = 32 MHz,
ADC1_conf_comp = 0
—
Conversion time5
VDD = 3.3 V
f
ADC 1 = 13.33 MHz,
3.6
3.6
ADC1_conf_comp = 0
Conversion time5
VDD = 5.0 V
f
ADC1 = 13.33 MHz,
—
ADC1_conf_comp = 0
ΔADC1_SYS SR — ADC_1 digital clock duty cycle ADCLKSEL = 16
45
—
—
—
55
5
ꢀ
CS
CC D ADC_1 input sampling
capacitance
—
pF
CP1
CP2
CC D ADC_1 input pin capacitance 1
CC D ADC_1 input pin capacitance 2
CC D ADC_1 input pin capacitance 3
—
—
—
—
—
—
—
—
—
—
—
—
3
1
pF
pF
pF
kΩ
CP3
1.5
1
RSW1
CC D Internal resistance of analog
source
RSW2
RAD
CC D Internal resistance of analog
source
—
—
—
—
—
—
2
kΩ
kΩ
CC D Internal resistance of analog
source
0.3
MPC5606BK Microcontroller Data Sheet, Rev. 5
74
NXP Semiconductors
Table 42. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
IINJ
SR — Input current Injection
Current
VDD = 3.3 V 10ꢀ
VDD = 5.0 V 10ꢀ
–5
–5
—
—
5
5
mA
injection on
one ADC_1
input, different
from the
converted one
INLP
INLX
CC T Absolute Integral
No overload
No overload
—
—
1
3
5
LSB
LSB
non-linearity-Precise channels
CC T Absolute Integral
1.5
non-linearity-Extended
channels
DNL
CC T Absolute Differential
non-linearity
No overload
—
0.5
1
LSB
OFS
GNE
CC T Absolute Offset error
CC T Absolute Gain error
—
—
—
—
–6
–8
2
2
—
—
6
LSB
LSB
LSB
TUEP7 CC P Total Unadjusted Error for
Without current injection
With current injection
—
—
precise channels, input only
T
8
pins
TUEX7 CC T Total Unadjusted Error for
Without current injection
With current injection
–10
–12
—
—
10
12
LSB
extended channel
T
1
2
3
VDD = 3.3 V 10ꢀ / 5.0 V 10ꢀ, TA = –40 to 125 °C, unless otherwise specified
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end
of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
5
6
7
This parameter does not include the sample time tADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by
internal divider by 2.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
75
3.18 On-chip peripherals
3.18.1 Current consumption
1
Table 43. On-chip peripherals current consumption
Value
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_BV(CAN)
CC T CAN
(FlexCAN)
Bit rate = Total (static + dynamic)
8 * fperiph + 85
µA
500 KB/s
consumption:
supply current
on VDD_BV
• FlexCAN in loop-back
mode
• XTAL at 8 MHz used as
CAN engine clock
source
Bit rate =
125 KB/s
8 * fperiph + 27
• Message sending
period is 580 µs
IDD_BV(eMIOS) CC T eMIOS supply Static consumption:
29 * fperiph
current on
VDD_BV
• eMIOS channel OFF
• Global prescaler enabled
Dynamic consumption:
3
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) Total (static + dynamic) consumption:
supply current • LIN mode
5 * fperiph + 31
on VDD_BV
• Baud rate: 20 KB/s
IDD_BV(SPI)
CC T SPI (DSPI)
Ballast static consumption (only
1
supply current clocked)
on VDD_BV
Ballast dynamic consumption
(continuous communication):
• Baud rate: 2 Mb/s
16 * fperiph
• Transmission every 8 µs
• Frame: 16 bits
IDD_BV
CC T ADC_0/ADC_1 VDD = 5.5 V Ballast static consumption
41 * fperiph
46 * fperiph
µA
supply current
on VDD_BV
(no conversion)
(ADC_0/ADC_1)
V
DD = 5.5 V Ballast dynamic
consumption (continuous
conversion)
IDD_HV_ADC0 CC T ADC_0 supply VDD = 5.5 V Analog static consumption
200
3
current on
(no conversion)
VDD_HV_ADC0
VDD = 5.5 V Analog dynamic
mA
consumption (continuous
conversion)
MPC5606BK Microcontroller Data Sheet, Rev. 5
76
NXP Semiconductors
1
Table 43. On-chip peripherals current consumption (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Typ
IDD_HV_ADC1 CC T ADC_1 supply VDD = 5.5 V Analog static consumption
300 * fperiph
µA
current on
(no conversion)
VDD_HV_ADC1
VDD = 5.5 V Analog dynamic
4
mA
consumption (continuous
conversion)
IDD_HV(FLASH) CC T CFlash +
VDD = 5.5 V
—
12
mA
mA
DFlash supply
current on
VDD_HV
IDD_BV(PLL)
CC T PLL supply
current on
VDD = 5.5 V
—
2.5
VDD_BV
1
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
77
3.18.2 DSPI characteristics
1
Table 44. DSPI characteristics
DSPI0/DSPI1/DSPI5/DSPI6
DSPI2/DSPI4
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
Min
Typ
Max
1
tSCK
SR D SCK cycle time
Master mode
(MTFE = 0)
125
—
—
3332
—
—
ns
D
D
D
Slave mode
(MTFE = 0)
125
83
—
—
—
—
—
—
333
145
145
—
—
—
—
—
—
Master mode
(MTFE = 1)
Slave mode
(MTFE = 1)
83
—
2
fDSPI
SR D DSPI digital controller frequency
—
—
—
fCPU
—
—
—
fCPU
—
MHz
ns
3
tCSCext SR D CS to SCK delay
Slave mode
Slave mode
Master mode
Slave mode
Slave mode
32
—
32
4
3
tASCext SR D After SCK delay
1/fDSPI + 5
—
—
1/fDSPI + 5
—
—
ns
4
tSDC
CC D SCK duty cycle
SR
SR D Slave access time
—
tSCK/2
—
tSCK/2
—
—
—
tSCK/2
—
tSCK/2
—
—
ns
D
—
—
5
6
7
8
9
tA
—
1/fDSPI + 70
—
—
—
—
—
—
—
—
—
—
—
—
1/fDSPI + 130 ns
tDI
SR D Slave SOUT disable time Slave mode
7
—
—
—
—
—
—
—
—
32
52
—
—
7
—
—
—
—
—
—
—
50
160
—
—
ns
tPCSC CC D PCSx to PCSS time
tPASC CC D PCSS to PCSx time
—
—
135
135
43
5
—
135
135
145
5
—
tSUI
SR D Data setup time for
inputs
Master mode
Slave mode
—
ns
ns
ns
ns
—
10
11
12
tHI
SR D Data hold time for inputs Master mode
Slave mode
0
—
0
26
—
26
7
tSUO
CC D Data valid after SCK
edge
Master mode
Slave mode
Master mode
Slave mode
—
—
—
—
—
—
7
tHO
CC D Data hold time for
outputs
0
—
0
8
—
13
1
2
Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
For DSPI4, if SOUT is mapped to a SLOW pad while SCK is mapped to a MEDIUM pad (or vice versa), the minimum cycle time for SCK
should be calculated based on the rise and fall times of the SLOW pad. For MTFE=1, SOUT must not be mapped to a SLOW pad while SCK
is mapped to a MEDIUM pad.
3
4
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers),
delay between internal CS and internal SCK must be higher than ΔtCSC to ensure positive tCSCext
.
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than ΔtASC to ensure positive tASCext
For DSPIx_CTARn[PCSSCK] = 11.
.
5
6
7
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
SCK and SOUT are configured as MEDIUM pad.
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 44.
Figure 23. DSPI classic SPI timing — master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 44.
Figure 24. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
11
12
Data
6
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 44.
Figure 25. DSPI classic SPI timing — slave, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
80
NXP Semiconductors
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 44.
Figure 26. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Note: Numbers shown reference Table 44.
Figure 27. DSPI modified transfer format timing — master, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
81
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 44.
Figure 28. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 44.
Figure 29. DSPI modified transfer format timing — slave, CPHA = 0
MPC5606BK Microcontroller Data Sheet, Rev. 5
82
NXP Semiconductors
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 44.
Figure 30. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 44.
Figure 31. DSPI PCS strobe (PCSS) timing
3.18.3 JTAG characteristics
Table 45. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
tJCYC
tTDIS
tTDIH
CC D TCK cycle time
CC D TDI setup time
CC D TDI hold time
64
15
5
—
—
—
—
—
—
ns
ns
ns
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
83
Table 45. JTAG characteristics (continued)
Value
Typ
No.
Symbol
C
Parameter
Min
Unit
Max
4
5
6
7
tTMSS
tTMSH
tTDOV
tTDOI
CC D TMS setup time
15
5
—
—
—
—
—
—
33
—
ns
ns
ns
ns
CC D TMS hold time
CC D TCK low to TDO valid
CC D TCK low to TDO invalid
—
6
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
7
Note: Numbers shown reference Table 45.
Figure 32. Timing diagram — JTAG boundary scan
MPC5606BK Microcontroller Data Sheet, Rev. 5
84
NXP Semiconductors
4
Package characteristics
Package mechanical data
176 LQFP
4.1
4.1.1
Figure 33. 176 LQFP package mechanical drawing (Part 1 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
85
Figure 34. 176 LQFP package mechanical drawing (Part 2 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
86
NXP Semiconductors
Figure 35. 176 LQFP package mechanical drawing (Part 3 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
87
4.1.2
144 LQFP
Figure 36. 144 LQFP package mechanical drawing (Part 1 of 2)
MPC5606BK Microcontroller Data Sheet, Rev. 5
88
NXP Semiconductors
Figure 37. 144 LQFP package mechanical drawing (Part 2 of 2)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
89
4.1.3
100 LQFP
Figure 38. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
90
NXP Semiconductors
Figure 39. 100 LQFP package mechanical drawing (Part 2 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
91
Figure 40. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5606BK Microcontroller Data Sheet, Rev. 5
92
NXP Semiconductors
5
Ordering information
Example code:
M
PC
56
0
6
B
K0A
M
LL
6
R
Qualification status
Power Architecture Core
Automotive platform
Core version
Flash memory size (core dependent)
Product
Fab and mask Indicator
Temperature spec.
Package code
Frequency
R = Tape & Reel (blank if Tray)
Qualification status
Flash memory size (for z0 core)
5 = 768 KB
6 = 1024 KB
Temperature spec.
C = –40 to 85 °C
V = –40 to 105 °C
M = –40 to 125 °C
M = General market qualified
S = Automotive qualified
P = Engineering samples
Product
B = Body
Automotive Platform
56 = Power Architecture in 90nm
Package code
LL = 100 LQFP
LQ = 144 LQFP
LU = 176 LQFP
Fab and mask Indicator
K = TSMC Fab
Core version
0 = e200z0
0 = Version of the maskset
A = Mask set indicator (Blank = 1st
production maskset, A = 2nd,
B = 3rd, etc)
Frequency
4 = Up to 48 MHz
6 = Up to 64 MHz
Note: Not all options are available on all devices.
Figure 41. Commercial product code structure
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
93
6
Revision history
Table 46. Revision history
Description of changes
Revision
Date
1
2
22 Apr 2011 Initial release.
15 May 2013 Changed device number to MPC5606BK.
In Table 2 (Functional port pins), updated PA[11] AF2, PD[13] AF2, and PH[11] AF3 I/O
direction to “I/O”.
In Table 3 (Pad types), corrected “Fast” in the “S” row to “Slow.”
In Table 5 (PAD3V5V field description), updated footnote 2.
In Table 6 (OSCILLATOR_MARGIN field description), updated footnote 2.
Inserted Section 3.2.3, NVUSRO[WATCHDOG_EN] field description.
In Table 8 (Absolute maximum ratings), Table 9 (Recommended operating conditions (3.3 V)),
and Table 10 (Recommended operating conditions (5.0 V)), corrected the parameter
description for VDD_ADC to “Voltage on VDD_HV_ADC0, VDD_HV_ADC1 (ADC reference)
with respect to ground (VSS)”
In Section 3.6.1, I/O pad types bullet item, removed Nexus reference.
In Table 12 (I/O input DC electrical characteristics), added specifications for 85 °C.
In Table 13 (I/O pull-up/pull-down DC electrical characteristics), Table 14 (SLOW configuration
output buffer electrical characteristics), Table 15 (MEDIUM configuration output buffer
electrical characteristics), and Table 16 (FAST configuration output buffer electrical
characteristics), changed sentence in footnote 2 to “All pads but RESET are configured in
input or in high impedance state.”
In Table 15 (MEDIUM configuration output buffer electrical characteristics), for VOL, changed
IOH to IOL
.
Updated Table 20 (I/O weight).
In Table 21 (Reset electrical characteristics) changed sentence in footnote 4 to “All pads but
RESET are configured in input or in high impedance state.”
in Table 22 (Voltage regulator electrical characteristics), corrected the maximum value for
IDD_BV in Table 22 (Voltage regulator electrical characteristics) to 300 mA.
In Table 23 (Low voltage monitor electrical characteristics), changed VPORUP classification tag
from “P” (Production testing guaranteed) to “D” (Design simulation). Changed VLVDHV3BH
classification tag from “P” (Production testing guaranteed) to “T” (Design characterization).
In Table 23 (Low voltage monitor electrical characteristics), changed VLVDHV3L, VLVDHV3BL
minimums from 2.7 V to 2.6 V.
MPC5606BK Microcontroller Data Sheet, Rev. 5
94
NXP Semiconductors
Table 46. Revision history (continued)
Description of changes
Revision
Date
2
15 May 2013 In Table 24 (Electrical characteristics in different application modes),
— Changed IDDMAX Typ to 81 mA and IDDMAX Typ to 130 mA.
(cont.)
— Changed IDDRUN Typ for fCPU = 32 MHz to 40 mA.
— Changed IDDRUN Typ for fCPU = 48 MHz to 54 mA. Added IDDRUN Max of 96 mA.
— Changed IDDRUN Typ for fCPU = 64 MHz to 67 mA. Added IDDRUN Max of 120 mA.
— Changed IDDHALT at TA = 25 °C Typ to 10 mA and IDDHALT Max to 15 mA.
— Changed IDDHALT at TA = 125 °C Typ to 15 mA and IDDHALT Max to 28 mA.
— Changed IDDSTOP TA temperature from –40 °C to 25 °C.
— Changed IDDSTOP at TA = 25 °C Typ to 130 µA and IDDSTOP Max to 500 µA.
— Changed IDDSTOP at TA = 55 °C Typ to 180 µA.
— Changed IDDSTOP at TA = 85 °C Typ to 1 mA and IDDSTOP Max to 5 mA.
— Changed IDDSTOP at TA = 105 °C Typ to 3 mA and IDDSTOP Max to 9 mA.
— Changed IDDSTOP at TA = 125 °C Typ to 5 mA and IDDSTOP Max to 14 mA.
— Changed IDDSTDBY2 at TA = 25 °C Typ to 17 µA and Max to 80 µA.
— Changed IDDSTDBY2 at TA = 55 °C Typ to 30 µA.
— Changed IDDSTDBY2 at TA = 85 °C Typ to 100 µA.
— Changed IDDSTDBY2 at TA = 105 °C Typ to 280 µA and Max to 950 µA.
— Changed IDDSTDBY2 at TA = 125 °C Typ to 460 µA and Max to 1700 µA.
— Changed the parameter classification for IDDSTANDBY2 (TA = 125 °C)
— Changed IDDSTDBY1 at TA = 25 °C Typ to 12 µA and Max to 50 µA.
— Changed IDDSTDBY1 at TA = 55 °C Typ to 24 µA.
— Changed IDDSTDBY1 at TA = 85 °C Typ to 48 µA.
— Changed IDDSTDBY1 at TA = 105 °C Typ to 150 µA and Max to 500 µA.
— Changed IDDSTDBY1 at TA = 125 °C Typ to 260 µA.
— Changed the third sentence of Footnote 3 to begin with “The given value is thought to be
a worst case value (64 MHz at 125 °C) with all peripherals running.”
— Removed footnotes 8 and 9 regarding IDDHALT and IDDSTOP
.
— Corrected “C” characteristics to reflect testing status.
In Section 3.10, Flash memory electrical characteristics, removed the "FLASH_BIU settings
vs. frequency of operation" table.
In Table 28 (Flash power supply DC electrical characteristics), corrected Footnote 2 to specify
125 °C.
In Section 3.14, FMPLL electrical characteristics, changed the text “the main oscillator driver”
to “the FXOSC or FIRC sources.”
In Table 40 (ADC input leakage current), added specifications for 85 °C.
In Table 44 (DSPI characteristics), added tSCK specifications for MTFE=1.
In Table 44 (DSPI characteristics), updated specifications 7 and 8 to 13 ns, all DSPIs.
in ADC section, corrected Equation 11.
In Figure 41 (Commercial product code structure), added “Note: Not all options are available
on all devices.”
Removed Section 6, Abbreviations.
3
4
5
11 Sep 2013 Updated the temperature in table note 2 in Table 1 (MPC5606BK family comparison) from 105
oC to 125 oC.
25 Nov2015 Updated the Max value current for IADC0run from 40 mA to 5 mA in Table 41 (ADC_0 conversion
characteristics (10-bit ADC_0)).
7 Nov 2017 In Table 9 (Recommended operating conditions (3.3 V)) added Min value for TVDD.
In Table 10 (Recommended operating conditions (5.0 V)) added Min value for TVDD.
In Table 44 (DSPI characteristics) changed the for DSPI 2 and 4, in MTFE=1 mode from 125
to 145.
MPC5606BK Microcontroller Data Sheet, Rev. 5
NXP Semiconductors
95
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MPC5606B
Rev. 5
11/2017
相关型号：
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