74AHC377PW-T [NXP]
IC AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20, FF/Latch;
| 型号： | 74AHC377PW-T |
| 厂家： | 
NXP |
| 描述： | IC AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC377; 74AHCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 02 — 12 June 2008
Product data sheet
1. General description
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D
inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when
the data enable input (E) is LOW. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. The E input is only required to be stable one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
For versions associated with the 74AHC377; 74AHCT377, refer to the following:
• For the master reset version, see 74AHC273; 74AHCT273
• For the transparent latch version, see 74AHC373; 74AHCT373
• For the 3-state version, see 74AHC374; 74AHCT374
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Ideal for addressable register applications
I Data enable for address and data synchronization
I Eight positive-edge triggered D-type flip-flops
I Input levels:
N For 74AHC377: CMOS level
N For 74AHCT377: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC377
74AHC377D
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
SOT360-1
74AHC377PW
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74AHCT377
74AHCT377D
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
SOT360-1
74AHCT377PW −40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
4. Functional diagram
3
4
7
8
D0
D1
D2
D3
Q0
Q1
Q2
Q3
2
5
6
9
FF1
to
FF8
OUTPUTS
13 D4
14 D5
17 D6
18 D7
Q4 12
Q5 15
Q6 16
19
Q7
1
E
11 CP
mna606
Fig 1. Functional diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
2 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
11
1C2
1
G1
11
CP
3
2
2D
3
4
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
E
1
mna919
mna918
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
E
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
FF2
CP
CP
CP
CP
CP
CP
FF1
FF3
FF4
FF5
FF6
FF7
FF8
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna610
Fig 4. Logic diagram
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
3 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
377
GND 10
mna917
Fig 5. Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
E
Pin description
Pin
1
Description
data enable input (active LOW)
flip-flop output
data input
Q0
2
D0
3
D1
4
data input
Q1
5
flip-flop output
flip-flop output
data input
Q2
6
D2
7
D3
8
data input
Q3
9
flip-flop output
ground (0 V)
GND
CP
10
11
12
13
14
15
16
17
18
19
20
clock input (LOW-to-HIGH, edge triggered)
flip-flop output
data input
Q4
D4
D5
data input
Q5
flip-flop output
flip-flop output
data input
Q6
D6
D7
data input
Q7
flip-flop output
supply voltage
VCC
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
4 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Output
E
l
CP
↑
Dn
h
Qn
Load 1
H
Load 0
l
↑
l
L
Hold (do nothing)
h
H
↑
X
X
no change
no change
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
5 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
8. Recommended operating conditions
Table 5.
Operating conditions
Symbol Parameter
74AHC377
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
ns/V
ns/V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT377
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
-
+25
-
°C
ns/V
VCC = 4.5 V to 5.5 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ
−40 °C to +85 °C −40 °C to +125 °C Unit
Max
Min
Max
Min
Max
74AHC377
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
output voltage
VI = VIH or VIL
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
1.9
2.9
4.4
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
IO = −4.0 mA; VCC = 3.0 V 2.58
IO = −8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.44
0.44
0.55
0.55
-
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
6 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
-
-
-
0.1
-
1.0
-
2.0
µA
µA
pF
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
4.0
10
-
-
40
10
-
-
80
10
V
input
VI = VCC or GND
3
capacitance
74AHCT377
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
4.0
-
-
40
-
-
80
µA
V
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC − 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
CI
input
VI = VCC or GND
-
3
10
-
10
-
10
pF
capacitance
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
7 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
74AHC377
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
[2]
tpd
propagation CP to Qn; see Figure 6
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.6 12.8
8.0 16.0
1.0
1.0
15.0
18.0
1.0
1.0
16.0
20.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.9
9.0
1.0
1.0
10.5
12.0
1.0
1.0
11.5
13.5
ns
ns
CL = 50 pF
5.6 10.5
fmax
maximum
frequency
see Figure 6
VCC = 3.0 V to 3.6 V
CL = 15 pF
80
50
125
75
-
-
70
45
-
-
70
45
-
-
MHz
MHz
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
125
85
175
120
-
-
110
75
-
-
110
75
-
-
MHz
MHz
CL = 50 pF
tW
pulse width CP HIGH or LOW;
see Figure 6
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
tsu
set-up time Dn, E to CP; see Figure 7
VCC = 3.0 V to 3.6 V
5.0
4.5
-
-
-
-
5.0
4.5
-
-
5.0
4.5
-
-
ns
ns
VCC = 4.5 V to 5.5 V
th
hold time
Dn, E to CP; see Figure 7
VCC = 3.0 V to 3.6 V
1.5
2.0
-
-
-
-
-
-
1.5
2.0
-
-
-
-
1.5
2.0
-
-
-
-
ns
ns
pF
VCC = 4.5 V to 5.5 V
[3]
CPD
power
fi = 1 MHz; VI = GND to VCC
20
dissipation
capacitance
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
8 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHCT377; VCC = 4.5 V to 5.5 V
[2]
tpd
propagation CP to Qn; see Figure 6
delay
CL = 15 pF
CL = 50 pF
see Figure 6
CL = 15 pF
CL = 50 pF
-
-
4.0
9.0
1.0
1.0
10.5
12.0
1.0
1.0
11.5
13.5
ns
ns
5.7 10.5
fmax
maximum
frequency
90
85
140
130
-
-
-
-
80
75
-
-
-
80
75
-
-
-
MHz
MHz
ns
tW
pulse width CP HIGH or LOW;
see Figure 6
5.0
5.0
5.0
tsu
th
set-up time Dn, E to CP; see Figure 7
4.5
2.0
-
-
-
-
-
-
4.5
2.0
-
-
-
-
4.5
2.0
-
-
-
-
ns
ns
pF
hold time
Dn, E to CP; see Figure 7
fi = 1 MHz; VI = GND to VCC
[3]
CPD
power
23
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
9 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
11. Waveforms
1/f
max
V
I
CP input
V
t
M
GND
t
W
t
PHL
PLH
V
OH
V
Qn output
M
001aac426
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Clock pulse width, maximum frequency and input to output propagation delays
V
CC
E input
V
M
GND
t
t
h
h
t
t
su
su
V
CC
Dn input
GND
V
M
t
su
t
t
h
W
V
CC
CP input
GND
V
M
mna609
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Data set-up and hold times
Table 8.
Type
Measurement points
Input
VM
Output
VM
74AHC377
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
74AHCT377
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
10 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 8. Load circuitry for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74AHC377
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74AHCT377
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
11 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 9. Package outline SOT163-1 (SO20)
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
12 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 10. Package outline SOT360-1 (TSSOP20)
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
13 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
14. Revision history
Table 11. Revision history
Document ID
Release date
20080612
Data sheet status
Change notice
Supersedes
74AHC_AHCT377_2
Modifications:
Product data sheet
-
74AHC_AHCT377_1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT377_1
20000815
Product specification
-
-
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
14 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT377_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 June 2008
15 of 16
74AHC377; 74AHCT377
NXP Semiconductors
Octal D-type flip-flop with data enable; positive-edge trigger
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 June 2008
Document identifier: 74AHC_AHCT377_2
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