PI6C39912-5 [PERICOM]
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32;
| 型号： | PI6C39912-5 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer-SuperClock
Features
Description
All output pair skew <100ps typical (250 Max.)
3.75 MHz to 133 MHz output operation
User-selectable output functions
Selectable skew to 18ns
ThePI6C39911andPI6C39912offerselectablecontroloversystem
clock functions. These multiple-output clock drivers provide the
systemintegratorwithfunctionsnecessarytooptimizethetimingof
high-performance computer systems. Eight individual drivers, ar-
ranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50 Ohm
whiledeliveringminimalandspecifiedoutputskewsandfull-swing
logiclevels.
Inverted and Non-Inverted
Operation at ½ and ¼ input frequency
Operation at 2X and 4X input frequency
(input as low as 3.75 MHz)
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output delays
of up to ±12 time units.
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50 Ohm terminated lines
Operates from a single 3.3V supply
Low operating current
Divide-by-twoanddivide-by-fouroutputfunctionsareprovidedfor
additional flexibility in designing complex clock systems. When
combinedwiththeinternalPLL,thesedividefunctionsallowdistri-
butionofalow-frequencyclockthatcanbemultipliedbytwoorfour
at the clock destination. This facility minimizes clock distribution
difficulty while allowing maximum system user-clock speed and
flexibility.
32-pinPLCCpackage
Jitter < 200ps peak-to-peak (< 25ps RMS)
AvailableinLVTTL(PI6C39911)orBalanced(PI6C39912)
PI6C39911isapin-to-pincompatiblewithCY7B9911V
LogicBlockDiagram
PinConfiguration
Test
Phase
Freq.
DET
VCO and
Time Unit
Generator
FB
1Q0
1Q1
Filter
REF
4
3
2
1
32 31 30
5
29
28
27
26
25
24
23
22
21
3F1
4F0
4F1
2F0
GND
1F1
1F0
6
4Q0
4Q1
7
4F0
4F1
8
V
CCQ
32-pin PLCC
Select Inputs
(three level)
9
V
V
CCN
4Q1
CCN
Skew
10
11
12
13
3Q0
3Q1
1Q0
1Q1
GND
GND
3F0
3F1
4Q0
Select
GND
GND
2Q0
2Q1
2F0
2F1
14 15 16 17 18 19 20
Matrix
1Q0
1Q1
1F0
1F1
PSXXXX
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
PinDescriptions
Signal Name
I/O
Description
Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs)
Three-level frequency range select. see Table 1.
REF
I
FB
I
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
Three-level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2.
Three-level select. See test mode section under the block diagram descriptions
Output pair 1. see Table 2
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
O
O
Output pair 2. see Table 2
Output pair 3. see Table 2
Output pair 4. see Table 2
PWR Power supply for output drivers
PWR Power supply for internal circuitry
PWR Ground
VCCQ
GND
(1)
Table1.FrequencyRangeSelectandt Calculation
U
1
tU
=
Approximate
Freq. (MHz) at
which tU = 1.0ns
FNOM (MHz)
f
NOM × N
FS(2,3)
where N=
Min.
15
Max.
30
LOW
MID
44
26
16
22.7
38.5
62.5
25
50
HIGH
40
133
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
(1)
Table2.ProgrammableSkewConfigurations
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
Function Selects
Output Functions
,
CC
LOWindicatesaconnectiontoGND,andMIDindicatesanopen
connection. Internal termination circuitry holds an unconnected
1F1, 2F1, 1F0, 2F0, 1Q0, 1Q1,
3Q0, 3Q1 4Q0, 4Q1
3F1, 4F1
LOW
LOW
LOW
MID
3F0, 4F0
LOW
MID
2Q0, 2Q1
input to V /2.
CC
4tU
Divide by 2 Divide by 2
2. The level to be set on FS is determined by the normal operating
frequency(f )oftheV andTimeUnitGenerator(seeLogic
NOM CO
3tU
6tU
4tU
6tU
4tU
Block Diagram). Nominal frequency (f
) always appears at
NOM
1Q0 and the other outputs when they are operated in their
undivided modes (see Table 2). The frequency appearing at the
HIGH
LOW
MID
2tU
1tU
2tU
2tU
REF and FB inputs will be f
when the output connected to
NOM
FB is undivided. The frequency of the REF and FB inputs will be
/2 or f /4 when the part is configured for a frequency
MID
0tU
0tU
0tU
f
NOM
NOM
multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+2tU
+4tU
+6tU
Inverted
HIGH
HIGH
HIGH
+4tU
transition upon power-up until V has reached 2.8V.
CC
+6tU
HIGH
Divide by 4
FB Input
REF Input
1Fx
2Fx
3Fx
4Fx
LM
LH
(N/A)
LL
–6tU
–4tU
–3tU
–2tU
–1tU
0tU
LM (N/A)
LH ML
ML (N/A)
MM MM
MH
HL
(N/A) +1tU
MH +2tU
(N/A) +3tU
HM
HH
HL
+4tU
+6tU
(N/A)
HM
(N/A) LL/HH Divided
(N/A) HH Invert
(4)
Figure1.TypicalOutputswithFBConnectedtoaZero-SkewOutput
Note:
4. FB connected to an output selected for
"zero"skew(ie.,xF1=xF0=MID).
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Test Mode
MaximumRatings
The TEST input is a three-level input. In normal system operation,
thispinisconnectedtoground, allowingthePI6C39911tooperate
as explained briefly above (for testing purposes, any of the three
levelinputscanhavearemovablejumpertoground,orbetiedLOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
Storage Temperature ...................................... 65°Cto+150°C
AmbientTemperaturewith
PowerApplied.................................................55°Cto+125°C
Supply Voltage to Ground Potential .................. 0.5Vto+5.0V
DC Input Voltage ...............................................0.5Vto+5.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(perMIL-STD-883,Method3015)
IftheTESTinputisforcedtoitsMIDorHIGHstate,thedevicewill
operatewithitsinternalphaselockedloopdisconnected, andinput
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
Latch-UpCurrent .........................................................>200mA
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
selectinputs(xF0andxF1)andthewaveformcharacteristicsofthe
REFinput.
OperatingRange
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
3.3V ±10%
3.3V ±10%
40°C to +85°C
Capacitance(10)
Parameter
CIN
Description
Test Conditions
Max.
Units
Input Capacitance
TA = 25°C, f = 1MHz, VCC = 3.3V
10
pF
AC Test Loads and Waveforms
TTL AC Test Load
TTL Input Test Waveform
VCC
≤1ns
≤1ns
R1
R2
3.0V
2.0V
Vth=1.5V
0.8V
0V
C
L
R1=100
R2=100
C =30pF
L
(Includes fixture and probe capacitance)
PSXXXX
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
(5)
Electrical Characteristics (Over the Operating Range)
PI6C39911/PI6C39912
Test Conditions
Parameter
Description
Min. Max. Units
V
Output HIGH Voltage
Output LOW Voltage
V
= Min., I = 18mA
2.4
OH
CC
OH
V
V
CC
= Min., I = 35mA
0.45
OL
OL
V
Input HIGH Voltage (REF and FB inputs only)
Input LOW Voltage (REF and FB inputs only)
2.0
0.5
0.87
V
CC
IH
V
0.8
IL
V
(6)
(6)
V
IHH
Three-Level Input HIGH Voltage (Test, FS, xFn)
Min. ≤ V ≤ Max.
V
CC
CC
V
CC
0.47
0.53
V
CC
(6)
V
IMM
Three-Level Input MID Voltage (Test, FS, xFn)
Min. ≤ V ≤ Max.
CC
V
CC
0.13
V
ILL
Three-Level Input LOW Voltage (Test, FS, xFn)
Min. ≤ V ≤ Max.
0.0
CC
V
CC
I
IH
Input HIGH Leakage Current (REF and FB inputs only) V = Max., V = Max.
20
CC
IN
I
Input LOW Leakage Current (REF and FB inputs only)
Input HIGH Current (Test, FS, xFn)
V
= Max., V = 0.4V
20
50
IL
CC
IN
I
V
IN
= V
CC
200
50
µA
IHH
I
Input MID Current (Test, FS, xFn)
V
= V /2
IMM
IN CC
I
Input LOW Current (Test, FS, xFn)
V
GND
200
200
95
ILL
IN =
(7)
I
Short Circuit Current
V
CC
= Max., V
OUT
= GND (25°C only)
Com'l
OS
mA
I
Operating Current Used by Internal Circuitry
CCQ
V
CCN
= V
= Max.,
CCQ
All Input Selects Open
Mil/Ind
100
V
= V = Max.,
= 0mA
CCN
CCQ
(8)
I
Output Buffer Current per Output Pair
I
25
mA
CCN
OUT
All Input Selects Open, f
MAX
V
= V
= 0mA
= Max.,
CCN
CCQ
(9)
PD
Power Dissipation per Output Pair
I
130
mW
OUT
All Input Selects Open, f
MAX
Notes:
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal
CC
CC
termination resistors hold unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch
CC
and the PLL may require an additional t
time before all data sheet limits are achieved.
LOCK
7. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Roomtemperatureonly.
8. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
PI6C39911:I
Where
=[(4+0.11F)+[[((8353F)/Z)+(.0022FC)]N]x1.1
CCN
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus
powerdissipationduetotheloadcircuit:PD=[(22+0.61F)+[[(1550+2.7F)/Z)+(.0125FC)]N]x1.1 Seenote8forvariabledefinition.
10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
PSXXXX
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
(2,11)
Switching Characteristics PI6C3991 (Over the Operating Range)
PI6C39911-2
PI6C39912-2
PI6C39911-5
PI6C39912-5
PI6C39911
PI6C39912
Parameter
Description
Units
Min.
15
Typ.
Max. Min.
Typ. Max. Min.
Typ.
Max.
30
(1,2)
FS = LOW
30
50
15
25
30
50
15
25
Operating
Clock Frequency
in MHz
(23)
(1,2)
f
FS = MID
25
50
MHz
ns
NOM
(1,2)
FS = HIGH
40
133
40
133
40
133
t
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
5.0
5.0
5.0
5.0
RPWH
t
RPWL
t
U
See Table 1
0.1
See Table 1
See Table 1
(13,14)
t
Zero Output Matched-Pair Skew (XQ0, XQ1)
0.25
0.25
0.5
0.1
0.25
0.6
0.25
0.5
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
SKEWPR
(13,15)
t
Zero Output Skew (All Outputs)
0.20
0.4
SKEW0
(13,17)
t
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
0.7
SKEW1
(13,17)
t
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
0.6
0.8
0.5
1.0
1.5
SKEW2
(13,17)
t
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
0.4
0.5
0.5
0.7
1.2
SKEW3
(13,17)
t
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
0.5
0.8
0.5
1.0
1.7
SKEW4
(12,18)
t
Device-to-Device Skew
1.0
1.25
+0.5
+1.0
2.5
1.65
+0.7
+1.2
3.0
ns
DEV
t
PD
Propagation Delay, REF Rise to FB Rise
0.3
0.7
0.0
0.0
0.3
0.7
2.5
0.5
1.0
0.0
0.0
0.7
1.2
0.0
0.0
(19)
t
Output Duty Cycle Variation
ODCV
(20)
t
Output HIGH Time Deviation from 50%
PWH
(20)
t
Output LOW Time Deviation from 50%
3.0
3.0
3.5
PWL
(20,21)
t
Output Rise Time
0.15
0.15
1.0
1.0
1.5
0.15
0.15
1.0
1.0
1.5
0.15
0.15
1.0
1.0
1.5
ORISE
(20,21)
t
Output Fall Time
1.5
1.5
1.5
OFALL
(22)
t
PLL Lock Time
0.5
0.5
0.5
ms
ps
LOCK
(12)
RMS
25
25
25
Cycle-to-cycle
Output Jitter
t
JR
(12)
Peak-to-peak
200
200
200
Notes:
11. Test measurement levels for the PI6C39911 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output
loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected
when all are loaded with 30pF and terminated with 50 Ohm to VCC/2.
14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
16. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns.
17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and
4Qx only in Divide-by-2 or Divide-by-4 mode).
18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
20. Specified with outputs loaded with 30pF for the PI6C39911 and PI6C39912 devices. Devices are terminated through 50 Ohm to VCC/2. tPWH is
measured at 2.0V. tPWL is measured at 0.8V.
21. tORISE and tOFALL measured between 0.8V and 2.0V.
22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
23. For frequencies higher than 110MHz outputs should not have higher than 20pF loads, in order to meet package thermal requirement.
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
ACTimingDiagrams
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
SKEW2,4
REF Divided by 2
t
SKEW1,3,4
REF Divided by 4
PSXXXX
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
OperationalModeDescriptions
REF
FB
LOAD
System Clock
REF
FS
L1
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
LOAD
L2
L3
L4
Z
Z
0
0
LENGTH: L1 = L2 = L3 = L4
Figure2.Zero-Skewand/orZero-DelayClockDriver
Figure2showstheSUPERCLOCKconfiguredasazero-skewclock
buffer.InthismodethePI6C39911canbeusedasthebasisforalow-
skew clock distribution tree. When all of the function select inputs
(xF0, xF1) are left open, the outputs are aligned and may each drive
aterminatedtransmissionlinetoanindependentload.TheFBinput
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specifi-
cation,coupledwiththeabilitytodriveterminatedtransmissionlines
(withimpedancesaslowas50Ohm),allowsefficientprintedcircuit
board design.
REF
FB
LOAD
LOAD
System Clock
REF
FS
L1
L2
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L3
L4
LOAD
LOAD
Z
Z
0
0
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure3.ProgrammableSkewClockDriver
PSXXXX
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8
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Figure 3 shows a configuration to equalize skew between metal Figure4showsanexampleoftheinvertfunctionoftheSuperClock.
tracesofdifferentlengths. Inadditiontolowskewbetweenoutputs, In this example the 4Q0 output used as the FB input is programmed
the SuperClock can be programmed to stagger the timing of its forinvert(4F0=4F1=HIGH)whiletheotherthreepairsofoutputs
outputs. The four groups of output pairs can each be programmed areprogrammedforzeroskew.When4F0and4F1aretiedHIGH,4Q0
to different output timing. Skew timing can be adjusted over a wide and 4Q1 become inverted zero phase outputs. The PLL aligns the
range in small increments with the appropriate strapping of the rising edge of the FB input with the rising edge of the REF. This
functionselectpins. Inthisconfigurationthe4Q0outputisfedback causesthe1Q,2Q,and3Qoutputstobecometheinvertedoutputs
to FB and configured for zero skew.
with respect to the REF input. By selecting which output is connect
to FB, it is possible to have 2 inverted and 6 non-inverted outputs
or6invertedand2non-invertedoutputs.Thecorrectconfigura-tion
would be determined by the need for more (or fewer) inverted
outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate
for varying trace delays independent of inver-sion on 4Q.
The other three pairs of outputs are programmed to yield different
skewsrelativetothefeedback. Byadvancingtheclocksignalonthe
longertracesorretardingtheclocksignalonshortertraces,allloads
can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0ns
skew(xF1,xF0=MID)selected.TheinternalPLLsynchronizesthe
FB and REF inputs and aligns their rising edges to insure that all
outputs have precise phase alignment.
REF
Clock skews can be advanced by ±6 time units (t ) when using an
U
output selected for zero skew as the feedback. A wider range of
delaysispossibleiftheoutputconnectedtoFBisalsoskewed.Since
FB
20 MHz
REF
ZeroSkew,+t ,andt aredefinedrelativetooutputgroups,and
U
U
sincethePLLalignstherisingedgesofREFandFB, itispossibleto
createwideroutputskewsbyproperselectionofthexFninputs. For
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
40 MHz
20 MHz
examplea+10t betweenREFand3Qxcanbeachievedbyconnect-
U
ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =
High.(SinceFBalignsat4t and3Qxskewsto+6t ,atotalof+10
U
U
t skew is realized). Many other configurations can be realized by
U
80 MHz
skewing both the output used as the FB input and skewing the other
outputs.
REF
Figure5.FrequencyMultiplierwithSkewConnections
FB
REF
FS
Figure5illustratestheSuperClockconfiguredasaclockmultiplier.
The 3Q0 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 3Q0 and
3Q1outputsarelockedat20MHzwhilethe1Qxand2Qxoutputsrun
at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by
two,whichresultsina40MHzwaveformattheseoutputs.Notethat
the 20 and 40 MHz clocks fall simultaneously and are out of phase
on their rising edge. This will allow the designer to use the rising
edges of the ½ frequency and ¼ frequency outputs without concern
forrising-edgeskew.The2Q0,2Q1,1Q0,and1Q1outputsrunat80
MHz and are skewed by programming their select inputs accord-
ingly.NotethattheFSpiniswiredfor80MHzoperationbecausethat
is the frequency of the fastest output.
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure4.InvertedOutputConnections
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PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
offerdivide-by-2anddivide-by-4timing.Aninvertedoutputallows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew spec.
REF
FB
20 MHz
REF
FS
10 MHz
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the 1X clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
5 MHz
20 MHz
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locallymultiplytheclockratetoamoresuitablefrequency,whilestill
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
sametime.Itcanmultiplybytwoandfourordividebytwo(andfour)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
Figure6.FrequencyDividerConnections
Figure6demonstratestheSuperClock inaclockdividerapplication.
2Q0isfedbacktotheFBinputandprogrammedforzeroskew. 3Qx
isprogrammedtodividebyfour.4Qxisprogrammedtodividebytwo.
Note that the falling edges of the 4Qx and 3Qx outputs are aligned.
This allows use of the rising edges of the ½ frequency and ¼
frequencywithoutconcernforskewmismatch.The1Qxoutputsare
programmed to zero skew and are aligned with the 2Qx outputs. In
thisexample, theFSinputisgroundedtoconfigurethedeviceinthe
15 to 30 MHz range since the highest frequency output is running
at20MHz.
REF
FB
LOAD
27.5 MHz
REF
Distribution
Z0
Clock
FS
110 MHz
Inverted
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
27.5 MHz
LOAD
110 MHz
Zero Skew
Z0
110 MHz Skewed
LOAD
–2.273ns (–4t )
Z0
U
Figure7.Multi-FunctionClockDriver
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PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
REF
LOAD
FB
System
Clock
Z0
REF
FS
L1
L2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
L3
LOAD
Z0
L4
FB
Z0
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure8.Board-to-BoardClockDistribution
Figure8showsthePI6C39911connectedinseriestoconstructazero delay clock tree. Cascaded clock buffers will accumulate low-fre-
skew clock distribution tree between boards. Delays of the down quencyjitterbecauseofthenon-idealfilteringcharacteristicsofthe
streamclockbufferscanbeprogrammedtocompensateforthewire PLLfilter.Itisrecommendedthatnotmorethantwoclockbuffersbe
length (i.e., select negative skew equal to the wire delay) necessary connected in series.
to connect them to the master clock source, approximating a zero-
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ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTLor Balanced Output
Programmable Skew Clock Buffer - SuperClock
Package Diagram - 32-Pin PLCC (J)
OrderingInformation
Accuracy (ps) Ordering Code Package Name
Package Type
Operating Range
250
500
700
250
500
700
PI6C39911-2
PI6C39911-5
PI6C39911
32-Pin Plastic
Leaded Chip Carrier
J32
Commercial
PI6C39912-2
PI6C39912-5
PI6C39912
PericomSemiconductorCorporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
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