SZESD9101P2T5G [ONSEMI]
超低电容 ESD 保护二极管，用于高速数据线;
| 型号： | SZESD9101P2T5G |
| 厂家： | 
ONSEMI |
| 描述： | 超低电容 ESD 保护二极管，用于高速数据线 二极管 |
| 文件： | 总7页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD9101
ESD Protection Diode
Low Capacitance ESD Protection Diodes
for High Speed Data Lines
The ESD9101 is designed to protect a single high speed data line
from ESD. Ultra−low capacitance and low ESD clamping voltage via
SCR technology make this device an ideal solution for protecting
voltage sensitive high speed data lines. The SOD−923 mico−package
allows for easy PCB layout and the ability to be placed in space
constrained applications where board area comes at a premium.
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MARKING
DIAGRAM
SOD−923
CASE 514AB
Features
X M
• Low Capacitance (0.5 pF Max, I/O to GND)
• Protection for the Following Standards:
IEC 61000−4−2 (Level 4) & ISO 10605
• Low ESD Clamping Voltage
XX = Specific Device Code
M
G
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
PIN CONFIGURATIONS
AND SCHEMATICS
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Cathode
Typical Applications
• USB 3.0/3.1
• HDMI 1.3/1.4/2.0
• DisplayPort
• GPS Antenna
Anode
Pin 1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
−55 to +150
−55 to +150
260
Unit
°C
Operating Junction Temperature Range
Storage Temperature Range
T
J
T
stg
°C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
°C
Pins 2
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 150 pF/2 kW
ISO 10605 330 pF/2 kW
ISO 10605 330 pF/330 W
ESD
25
25
30
30
20
kV
=
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
May, 2017 − Rev. 0
ESD9101/D
ESD9101
ELECTRICAL CHARACTERISTICS
I
(T = 25°C unless otherwise noted)
A
I
PP
Symbol
Parameter
R
DYN
V
RWM
Working Peak Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
V
BR
V
BR
Breakdown Voltage @ I
V
V
V
RWM HOLD
C
T
I
I
V
R
T
C
I
T
Test Current
I
V
Holding Reverse Voltage
Holding Reverse Current
Dynamic Resistance
Maximum Peak Pulse Current
HOLD
HOLD
HOLD
I
R
DYN
R
DYN
−I
PP
I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
V
C
Clamping Voltage @ I
PP
V
C
= V
+ (I * R
)
HOLD
PP
DYN
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
5.0
8.0
1.0
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
5.3
7.0
V
T
Reverse Leakage Current
Holding Reverse Voltage
Holding Reverse Current
Clamping Voltage
I
R
V
RWM
= 5.0 V, I/O Pin to GND
mA
V
V
I/O Pin to GND
2.2
97
HOLD
HOLD
I
I/O Pin to GND
65
mA
V
V
V
IEC61000−4−2, 8 KV Contact
See Figures 1 and 2
C
Clamping Voltage TLP
I
PP
I
PP
= 8 A
= −8 A
5.0
−4.0
V
C
I
PP
I
PP
= 16 A
= −16 A
7.0
−7.0
Dynamic Resistance
Junction Capacitance
R
I/O Pin to GND
GND to I/O Pin
0.30
0.38
W
DYN
C
V
R
V
R
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
= 0 V, f = 2.5 GHz between I/O Pins and GND
= 0 V, f = 5.0 GHz between I/O Pins and GND
0.36
0.36
0.36
0.50
0.45
0.45
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
10
0
−80
−90
−10
−20
0
20
40
60
80
100
120 140
−20
0
20
40
60
80
100
120 140
TIME (ns)
TIME (ns)
Figure 1. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 2. IEC61000−4−2 −8 kV Contact
Clamping Voltage
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2
ESD9101
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD9101
20
18
16
14
12
10
8
10
10
8
−20
−18
8
6
4
−16
−14
−12
−10
−8
6
4
6
−6
−4
−2
0
2
0
4
2
0
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 5. Positive TLP IV Curve
Figure 6. Negative TLP IV Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage
IEC
0
p
r
1
2
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD9101
1.E+00
1.E−01
1.E−02
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
−2 −1
0
1
2
3
4
5
6
7
8
9
10
V (V)
Figure 9. IV Characteristics
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5
ESD9101
Latch-Up Considerations
therefore latch-up free. In the non-latch up free load line
case, the IV characteristic of the snapback protection device
ON Semiconductor’s 9100 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
intersects the load-line in two points (V
, I
OPA OPA
) and
(V , I ). Therefore in this case, the potential for
OPB OPB
latch-up exists if the system settles at (V
, I
) after a
OPB OPB
transient. Due to its high holding current, the ESD9101 is
suitable for HDMI and 5 V active antenna applications
where previous ESD8000 series devices were not. When
designing this part into the application, please note the
latch−up considerations by performing a loadline analysis
corresponding to the data line and ESD9101’s SCR
characteristics. For a more in-depth explanation of latch-up
considerations please refer to Application Note AND9116/D.
the load-line in one unique point (V , I ). This is the only
stable operating point of the circuit and the system is
OP OP
I
I
ISSMAX
IOPB
ISSMAX
IOP
IOPA
V
V
VOP VDD
VOPB
VOPA VDD
Latch−up Free Condition
Potential Latch−up Condition
Figure 10. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch-up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
VBR (min)
IH (min)
VH (min)
(V)
(mA)
(V)
Application
HDMI 1.4/1.3a TMDS
USB 2.0 LS/FS
USB 2.0 HS
3.465
3.301
0.482
2.800
3.600
5.200
54.78
1.76
N/A
1.0
1.0
1.0
1.0
1.0
1.0
USB 3.0/3.1 SS
DisplayPort
N/A
25.00
80.00
GPS (Active)
ORDERING INFORMATION
Device
†
Package
Shipping
ESD9101P2T5G
SOD−923
(Pb−Free)
8000 / Tape & Reel
SZESD9101P2T5G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
ESD9101
PACKAGE DIMENSIONS
SOD−923
CASE 514AB−01
ISSUE C
−X−
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
−Y−
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
E
1
2
2X b
0.08 X
Y
TOP VIEW
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
MIN
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.37
0.20
0.12
0.80
0.60
1.00
0.19 REF
0.10
0.40
0.25
0.17
0.85
0.65
1.05
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
A
D
E
H
E
L
c
L2 0.05
0.15
0.002 0.004 0.006
H
E
SIDE VIEW
2X
L
SOLDERING FOOTPRINT*
1.20
2X
2X
0.25
0.36
2X
L2
BOTTOM VIEW
PACKAGE
OUTLINE
DIMENSIONS: MILLIMETERS
See Application Note AND8455/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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◊
ESD9101/D
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