SZESD9R3.3ST5G [ONSEMI]
ESD 保护二极管,超低泄漏,低电容;型号: | SZESD9R3.3ST5G |
厂家: | ONSEMI |
描述: | ESD 保护二极管,超低泄漏,低电容 局域网 测试 光电二极管 |
文件: | 总4页 (文件大小:111K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ESD9R3.3ST5G
Transient Voltage
Suppressors
ESD Protection Diodes with Ultra−Low
Leakage
The ESD9R is designed to provide ESD protection for ASSPs and
ASICs used in ultra low current applications such as human body sensors.
These devices have been designed for leakage under 1 nA from 0°C to
50°C when turned off. During an ESD event, these devices turn on to
clamp the ESD to a safe voltage level for the IC. These devices have the
added benefits of low capacitance for high speed data lines and small
package size for space constrained designs.
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Specification Features:
• Ultra−Low Leakage < 1 nA
• Ultra−Low Capacitance 0.5 pF
• Low Clamping Voltage
SOD−923
CASE 514AB
• Small Body Outline Dimensions:
0.039″ x 0.024″ (1.00 mm x 0.60 mm)
• Low Body Height: 0.016″ (0.4 mm)
MARKING DIAGRAM
• Stand−off Voltage: 3.3 V
• Response Time < 1.0 ns
J M
• IEC61000−4−2 Level 4 ESD Protection
• This is a Pb−Free and Halogen−Free Device
J
M
= Specific Device Code
= Date Code
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
ORDERING INFORMATION
†
Device
Package
Shipping
MAXIMUM RATINGS
ESD9R3.3ST5G SOD−923
8000/Tape & Reel
Rating
Symbol
Value
Unit
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
IEC 61000−4−2 (ESD)
Contact
Air
10
15
kV
HBM
16
Total Power Dissipation on FR−5 Board
°P °
150
mW
DEVICE MARKING INFORMATION
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
D
(Note 1) @ T = 25°C
A
Storage Temperature Range
Junction Temperature Range
T
stg
−55 to +150
−55 to +125
260
°C
°C
°C
T
J
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
July, 2008 − Rev. 0
ESD9R3.3S/D
ESD9R3.3ST5G
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
F
I
PP
V
C
PP
V
RWM
Working Peak Reverse Voltage
V
C
V
V
BR RWM
I
Maximum Reverse Leakage Current @ V
V
R
RWM
I
V
F
R
T
I
V
BR
Breakdown Voltage @ I
Test Current
T
I
T
I
F
Forward Current
I
PP
V
F
Forward Voltage @ I
F
P
Peak Power Dissipation
Max. Capacitance @ V = 0 and f = 1.0 MHz
pk
Uni−Directional TVS
C
R
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted, V = 1.0 V Max. @ I = 10 mA for all types)
A
F
F
I
R
(nA) @ 1 V
V
(V)
T
= 05C
C
A
V
RWM
V
(V) @ I
(Note 2)
@ I = 1 A
to 505C
BR T
PP
(V)
(Note 5)
(Note 4)
I
T
C (pF)
V
C
Per IEC61000−4−2
Device
Marking
(Note 3)
Max
Max
Min
mA
Typ
0.5
Max
Max
Device
ESD9R3.3ST5G
J*
3.3
1.0
4.8
1.0
0.9
7.8
Figures 1 and 2
See Below
*Rotated 270°.
2. V is measured with a pulse test current I at an ambient temperature of 25°C.
BR
T
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
4. Limits over temperature are guaranteed by design, not production tested.
5. V measured using pulse waveform in Figure 5.
C
Figure 1. ESD Clamping Voltage Screenshot
Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Negative 8 kV Contact per IEC61000−4−2
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2
ESD9R3.3ST5G
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
Test
Voltage
(kV)
First Peak
Current
(A)
100%
90%
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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3
ESD9R3.3ST5G
PACKAGE DIMENSIONS
SOD−923
CASE 514AB−01
ISSUE B
−X−
D
NOTES:
−Y−
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
E
1
2
b 2X
0.08 (0.0032) X Y
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
MIN
A
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.05
0.37
0.20
0.12
0.80
0.60
1.00
0.10
0.40
0.25
0.17
0.85
0.65
1.05
0.15
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.002 0.004 0.006
D
E
H
E
L
c
L
H
E
SOLDERING FOOTPRINT*
0.90
0.40
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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ESD9R3.3S/D
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