SZESD9B3.3ST5G [ONSEMI]
ESD Protection Diodes, Bidirectional;型号: | SZESD9B3.3ST5G |
厂家: | ONSEMI |
描述: | ESD Protection Diodes, Bidirectional 二极管 瞬态抑制器 |
文件: | 总4页 (文件大小:127K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ESD9B3.3ST5G
Transient Voltage
Suppressors
Micro−Packaged Diodes for ESD Protection
The ESD9B Series is designed to protect voltage sensitive
components from ESD. Excellent clamping capability, low leakage,
and fast response time provide best in class protection on designs that
are exposed to ESD. Because of its small size, it is suited for use in
cellular phones, MP3 players, digital cameras and many other portable
applications where board space comes at a premium.
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Specification Features
• Low Capacitance 15 pF
• Low Clamping Voltage
• Small Body Outline Dimensions: 0.039″ x 0.024″ (1.0mm x 0.60mm)
• Low Body Height: 0.016″ (0.4 mm)
• Stand−off Voltage: 3.3 V
• Low Leakage
SOD−923
CASE 514AB
• Response Time is < 1 ns
• IEC61000−4−2 Level 4 ESD Protection
• This is a Pb−Free Device
MARKING DIAGRAM
X M
Mechanical Characteristics
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
X
M
= Specific Device Code
Date Code
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
ORDERING INFORMATION
†
Device
Package
Shipping
MAXIMUM RATINGS
ESD9B3.3ST5G SOD−923
(Pb−Free)
8000/Tape & Reel
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
Contact
Air
8.0
15
kV
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Total Power Dissipation on FR−5 Board
°P °
D
300
mW
(Note 1) @ T = 25°C
A
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
Junction and Storage Temperature Range
T , T
J stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
September, 2008 − Rev. 0
ESD9B3.3S/D
ESD9B3.3ST5G
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V V
R
BR RWM
V
Clamping Voltage @ I
V
C
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
BR
Breakdown Voltage @ I
T
I
PP
I
T
Test Current
Bi−Directional TVS
C
Capacitance @ V = 0 V and f = 1.0 MHz
R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
V
RWM
I
R
(mA)
V
BR
(V) @ I
T
(V)
@ V
(Note 2)
I
T
C (pF)
V
C
V (V) @ I = 1 A
C PP
RWM
Per IEC61000−4−2
Max Per 8 x 20 ms
Device
Marking
(Note 3)
(Note 4)
Max
Max
1.0
Min
Max
mA
Typ
Device
ESD9B3.3ST5G
2*
3.3
5.0
7.0
1.0
15
Figures 1 and 2
See Below
10.5
* Rotated 270°.
2. V is measured with a pulse test current I at an ambient temperature of 25°C.
BR
T
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
4. Surge current waveforms per Figure 5.
Figure 1. ESD Clamping Voltage Screenshot
Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Negative 8 kV Contact per IEC61000−4−2
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2
ESD9B3.3ST5G
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
Test
Voltage
(kV)
First Peak
Current
(A)
100%
90%
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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3
ESD9B3.3ST5G
PACKAGE DIMENSIONS
SOD−923
CASE 514AB−01
ISSUE B
−X−
D
NOTES:
−Y−
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
E
1
2
b 2X
0.08 (0.0032) X Y
MILLIMETERS
DIM MIN NOM MAX
INCHES
NOM MAX
MIN
A
A
b
c
0.34
0.15
0.07
0.75
0.55
0.95
0.05
0.37
0.20
0.12
0.80
0.60
1.00
0.10
0.40
0.25
0.17
0.85
0.65
1.05
0.15
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.002 0.004 0.006
D
E
H
E
L
c
L
H
E
SOLDERING FOOTPRINT*
0.90
0.40
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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ESD9B3.3S/D
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