NVD5890N [ONSEMI]
Power MOSFET 40 V, 123 A, Single NâChannel DPAK; 功率MOSFET的40 V ， 123 A，单娜????频道DPAK
| 型号： | NVD5890N |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 40 V, 123 A, Single NâChannel DPAK |
| 文件： | 总7页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVD5890N
Power MOSFET
40 V, 123 A, Single N−Channel DPAK
Features
• Low R
to Minimize Conduction Losses
• MSL 1/260°C
DS(on)
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• AEC Q101 Qualified and PPAP Capable
• 100% Avalanche Tested
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
I
D
(BR)DSS
DS(on)
40 V
3.7 mW @ 10 V
123 A
Applications
• Motor Drivers
D
• Pump Drivers for Automotive Braking, Steering and Other High
Current Systems
N−Channel
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
G
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
S
Gate−to−Source Voltage
V
"20
123
95
V
GS
4
Continuous Drain Cur-
T
T
T
= 25°C
= 85°C
= 25°C
I
A
C
C
C
D
rent (R
)
q
JC
2
1
Power Dissipation
(R
P
107
W
A
D
3
)
q
JC
Steady
State
CASE 369C
DPAK
(Bent Lead)
STYLE 2
Continuous Drain Cur-
rent (R ) (Note 1)
T = 25°C
A
I
24
18.5
4.0
D
q
JA
T = 85°C
A
Power Dissipation
(R ) (Note 1)
T = 25°C
A
P
W
D
q
JA
MARKING DIAGRAMS
& PIN ASSIGNMENT
Pulsed Drain Current
t =10ms T = 25°C
I
400
100
A
A
p
A
DM
I
DmaxPkg
Current Limited by Package
T = 25°C
A
4
Operating Junction and Storage Temperature
T , T
J
−55 to
175
°C
stg
Drain
Source Current (Body Diode)
Drain to Source dV/dt
I
100
6.0
A
S
dV/dt
V/ns
mJ
Single Pulse Drain−to−Source Avalanche En-
E
AS
240
2
ergy (V = 32 V, V = 10 V,
DD
GS
Drain
L = 0.3 mH, I
= 40 A, R = 25 W)
1
3
L(pk)
G
Gate Source
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Y
WW
= Year
= Work Week
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
5890N = Device Code
= Pb−Free Package
G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
January, 2012 − Rev. 1
NVD5890N/D
NVD5890N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case (Drain)
R
1.4
37
76
°C/W
q
JC
Junction−to−Ambient − Steady State (Note 1)
R
q
JA
Junction−to−Ambient − Steady State (Note 2)
R
q
JA
2
1. Surface−mounted on FR4 board using 650 mm pad size, 2 oz Cu.
2
2. Surface−mounted on FR4 board using 36 mm pad size.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = 250 mA
40
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
J
40
mV/°C
(BR)DSS
Zero Gate Voltage Drain Current
I
T = 25°C
1.0
100
mA
DSS
J
V
= 0 V,
= 40 V
GS
DS
V
T = 150°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
I
V
= 0 V, V = "20 V
"100
nA
GSS
DS
GS
V
V
= V , I = 250 mA
1.5
3.5
3.7
V
GS(TH)
GS
DS
D
Negative Threshold Temperature
Coefficient
V
/T
J
7.4
mV/°C
GS(TH)
Drain−to−Source On Resistance
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
R
V
= 10 V, I = 50 A
2.9
mW
DS(on)
GS
D
gFS
V
= 15 V, I = 15 A
16.8
S
DS
D
C
4975
785
490
4760
580
385
74
pF
pF
nC
iss
V
= 0 V, f = 1.0 MHz,
DS
GS
Output Capacitance
C
oss
V
= 12 V
Reverse Transfer Capacitance
Input Capacitance
C
rss
C
V
= 0 V, f = 1.0 MHz,
= 25 V
iss
GS
V
DS
Output Capacitance
C
oss
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
100
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
5.0
G(TH)
V
GS
= 10 V, V = 15 V,
DS
I
= 50 A
D
Q
17
GS
GD
Q
16
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
t
14
55
35
7.0
ns
d(on)
t
r
V
= 10 V, V = 20 V,
GS
D
DS
I
= 50 A, R = 2.0 W
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NVD5890N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
V
S
= 0 V,
T = 25°C
0.9
0.8
1.2
1.0
V
GS
J
I
= 50 A
V
S
= 0 V,
= 20 A
T = 25°C
J
GS
I
Reverse Recovery Time
Charge Time
t
35
20
15
40
ns
RR
ta
V
GS
= 0 V, dIs/dt = 100 A/ms,
I
= 50 A
S
Discharge Time
tb
Reverse Recovery Charge
Q
nC
RR
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3
NVD5890N
TYPICAL PERFORMANCE CURVES
300
280
260
240
220
200
300
10 V
7 V
6 V
T = 25°C
280
260
240
220
200
J
V
DS
≥ 10 V
V
GS
= 5 V
180
160
140
120
100
80
60
40
20
0
180
160
140
120
100
80
60
40
20
0
4.5 V
4.2 V
4 V
T = 25°C
J
3.8 V
3.6 V
T = 150°C
J
T = −55°C
J
0
1
2
3
4
5
2
3
4
5
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
20
20
18
16
14
12
10
8
T = 25°C
J
T = 25°C
J
18
16
14
12
I
D
= 50 A
V
GS
= 5 V
10
8
6
4
2
0
6
V
= 10 V
GS
4
2
0
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
280
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Drain Current
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.0
1.75
1.5
1000
100
10
V
GS
= 0 V
V
= 10 V
= 50 A
GS
I
D
T = 175°C
J
1.25
1.0
T = 150°C
J
0.75
0.5
−50 −25
1
0
25
50
75
100 125 150 175
0
4
8
12 16 20 24 28 32 36
40
T , JUNCTION TEMPERATURE (°C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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4
NVD5890N
TYPICAL PERFORMANCE CURVES
7000
6000
5000
4000
3000
2000
15
20
15
14
13
12
11
10
9
V
= 0 V
GS
T = 25°C
J
Q
T
C
f = 1 MHz
iss
V
DS
V
GS
8
7
6
5
4
3
2
1
0
0
10
5
Q
Q
DS
GS
V
DS
= 15 V
= 50 A
C
oss
1000
0
I
D
T = 25°C
J
C
rss
0
80
0
5
10
15
20
25
30
35
40
10
20
30
40
50
60
70
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
1000
100
10
100
10
1
V
= 10 V
= 20 V
= 50 A
GS
DD
t
d(off)
V
I
t
f
D
t
T = 150°C
r
J
t
d(on)
100°C
25°C
T = −55°C
J
1
0.1
1
10
100
0.3 0.4 0.5 0.6
0.7 0.8
0.9 1.0 1.1 1.2
R , GATE RESISTANCE (W)
G
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
10 ms
100
100 ms
V
≤ 20 V
GS
1 ms
SINGLE PULSE
10
1
T
C
= 25°C
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
NVD5890N
TYPICAL PERFORMANCE CURVES
10
D = 0.5
0.2
1.0
0.1
0.05
0.02
0.1
0.01
0.01
SINGLE PULSE
R
= 1.4°C/W
q
JC
Steady State
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, TIME (s)
Figure 12. Thermal Response
ORDERING INFORMATION
Order Number
†
Package
Shipping
NVD5890NT4G
DPAK
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NVD5890N
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
D
A
E
c2
b3
B
4
2
L3
L4
Z
H
DETAIL A
1
3
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
A
b2
c
b
b
b2 0.030 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2 0.018 0.024
GAUGE
SEATING
PLANE
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
L2
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
0.020 BSC
DETAIL A
L3 0.035 0.050
ROTATED 905 CW
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
SOLDERING FOOTPRINT*
6.20
3.00
0.244
0.118
2.58
0.102
5.80
1.60
0.063
6.17
0.228
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NVD5890N/D
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