NTLUD3191PZTBG [ONSEMI]
Power MOSFET −20 V, −1.8 A, Cool Dual P−Channel, ESD, 1.6x1.6x0.55 mm UDFN Package; 功率MOSFET -20 V， -1.8 A， ？酷？双P通道， ESD ， 1.6x1.6x0.55毫米UDFN封装
| 型号： | NTLUD3191PZTBG |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET −20 V, −1.8 A, Cool Dual P−Channel, ESD, 1.6x1.6x0.55 mm UDFN Package |
| 文件： | 总6页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTLUD3191PZ
Power MOSFET
−20 V, −1.8 A, mCoolt Dual P−Channel,
ESD, 1.6x1.6x0.55 mm UDFN Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
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Conduction
• Low Profile UDFN 1.6 x 1.6 x 0.55 mm for Board Space Saving
• ESD
• This is a Halide Free Device
• This is a Pb−Free Device
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
250 mW @ −4.5 V
380 mW @ −2.5 V
500 mW @ −1.8 V
700 mW @ −1.5 V
−1.5 A
−1.0 A
−0.5 A
−0.2 A
−20 V
Applications
• High Side Load Switch
• PA Switch
• Battery Switch
D1
D2
• Optimized for Power Management Applications for Portable
Products, such as Cell Phones, PMP, DSC, GPS, and others
G1
G2
MAXIMUM RATINGS (T = 25°C unless otherwise stated)
J
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Symbol
Value
−20
8.0
Units
V
DSS
V
V
A
S1
S2
P−Channel MOSFET
V
GS
Continuous Drain
Current (Note 1)
Steady
State
T = 25°C
I
D
−1.4
−1.0
−1.8
0.8
MARKING
DIAGRAM
A
T = 85°C
A
1
UDFN6
CASE 517AT
mCOOLt
6
t ≤ 5 s
T = 25°C
A
AC MG
Power Dissipation
(Note 1)
Steady
State
T = 25°C
A
P
D
W
A
G
1
AC= Specific Device Code
M = Date Code
t ≤ 5 s
T = 25°C
A
1.3
−1.1
−0.8
0.5
Continuous Drain
Current (Note 2)
Steady
State
T = 25°C
A
I
D
G
= Pb−Free Package
T = 85°C
A
(Note: Microdot may be in either location)
Power Dissipation (Note 2)
Pulsed Drain Current
T = 25°C
A
P
D
W
A
tp = 10 ms
I
−8.0
DM
Operating Junction and Storage
Temperature
T ,
STG
-55 to
150
°C
J
T
Source Current (Body Diode) (Note 2)
I
S
−1.0
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
260
°C
L
Gate-to-Source ESD Rating
(HBM) per JESD22−A114F
ESD
1000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
2. Surface-mounted on FR4 board using the minimum recommended pad size
2
of 30 mm , 2 oz. Cu.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
April, 2009 − Rev. 1
NTLUD3191PZ/D
NTLUD3191PZ
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
155
100
245
Units
Junction-to-Ambient – Steady State (Note 3)
R
θJA
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3)
R
θJA
Junction-to-Ambient – Steady State min Pad (Note 4)
R
θJA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0 V, I = −250 mA
−20
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
/T
I = −250 mA, ref to 25°C
D
15
mV/°C
(BR)DSS
J
Zero Gate Voltage Drain Current
I
mA
mA
T = 25°C
−1.0
−10
10
DSS
J
V
DS
= 0 V,
GS
V
= −20 V
T = 85°C
J
Gate-to-Source Leakage Current
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
I
V
= 0 V, V =
GS
8.0 V
GSS
DS
V
V
GS
= V , I = 250 mA
−0.4
−1.0
V
GS(TH)
DS
D
Negative Threshold Temp. Coefficient
Drain−to−Source On Resistance
V
/T
2.5
175
240
330
410
1.4
mV/°C
mW
GS(TH)
J
R
V
V
V
V
= −4.5 V, I = −1.5 A
250
380
500
700
DS(on)
GS
GS
GS
GS
D
= −2.5 V, I = −1.0 A
D
= −1.8 V, I = −0.5 A
D
= −1.5 V, I = −0.2 A
D
Forward Transconductance
g
FS
V
= −5.0 V, I = −0.2 A
S
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
pF
Input Capacitance
C
160
32
ISS
V
= 0 V, f = 1 MHz,
DS
GS
Output Capacitance
C
OSS
C
RSS
V
= −10 V
Reverse Transfer Capacitance
Total Gate Charge
23
nC
ns
Q
2.3
0.2
0.4
0.7
3.5
G(TOT)
Threshold Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Q
G(TH)
V
= −4.5 V, V = −10 V;
GS
DS
ID = −1.5 A
Q
GS
GD
Q
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
Rise Time
t
13
24
68
62
d(ON)
t
r
V
= −4.5 V, V = −10 V,
DD
D
GS
I
= −1.5 A, R = 1 W
G
Turn-Off Delay Time
Fall Time
t
d(OFF)
t
f
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
V
T = 25°C
0.85
0.75
10
1.2
J
V
S
= 0 V,
GS
I
= −1.0 A
T = 85°C
J
ns
Reverse Recovery Time
Charge Time
t
RR
t
a
t
b
8.0
2.0
5.0
V
GS
= 0 V, dISD/dt = 100 A/ms,
I
= −1.0 A
S
Discharge Time
Reverse Recovery Charge
Q
nC
RR
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
2
4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm , 2 oz. Cu.
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NTLUD3191PZ
TYPICAL CHARACTERISTICS
10
9
5
V
GS
= −4.5 V
−4.0 V
V
DS
= −5 V
T = 25°C
J
−3.5 V
−3.0 V
8
4
3
2
7
6
5
−2.5 V
−2.0 V
4
3
2
1
0
−1.8 V
−1.5 V
T = 125°C
T = 25°C
J
J
1
0
T = −55°C
J
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.0
1.0
0.8
0.6
0.4
−1.5 V
T = 25°C
J
T = 25°C
J
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
−1.8 V
−2.5 V
I
= −1.5 A
D
0.2
0
I
D
= −0.2 A
V
GS
= −4.5 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
1
2
3
4
5
6
7
8
9
10
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
−I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
1000
100
1.7
V
= −4.5 V
= −1.5 A
GS
V
GS
= 0 V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
I
D
T = 150°C
J
T = 125°C
J
0.8
0.7
0.6
T = 85°C
J
10
−50 −25
0
25
50
75
100
125 150
0
5
10
15
20
T , JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NTLUD3191PZ
TYPICAL CHARACTERISTICS
250
225
200
175
150
125
100
75
12
10
5
Q
T
V
= 0 V
GS
T = 25°C
J
4
3
2
f = 1 MHz
C
iss
V
DS
V
GS
8
6
4
Q
Q
GD
GS
C
V
= −10 V
= −1.5 A
oss
GS
50
1
0
2
0
I
D
25
0
C
T = 25°C
J
rss
0
4
8
12
16
20
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
1.0
0.1
100
t
t
d(off)
t
f
V
V
= −4.5 V
= −10 V
= −1.5 A
GS
DD
T = 150°C
T = 25°C
J
J
I
D
r
t
d(on)
10
1
10
R , GATE RESISTANCE (W)
100
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
−V , SOURCE−TO−DRAIN VOLTAGE (V)
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
175
0.85
0.80
I
D
= −250 mA
150
125
100
75
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
50
25
0
−50 −25
0
25
50
75
100
125 150 0.00000010.000010.0001 0.001 0.01 0.1
1
10 100 1000
T , TEMPERATURE (°C)
J
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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4
NTLUD3191PZ
TYPICAL CHARACTERISTICS
10
1
10 ms
100 ms
1 ms
V
= −8 V
GS
10 ms
SINGLE PULSE
0.1
T
= 25°C
C
dc
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
−V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
175
150
125
100
75
0.5
0.2
50
0.02
25
0
0.1
0.01
0.05
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 14. FET Thermal Response
DEVICE ORDERING INFORMATION
Device
†
Package
Shipping
NTLUD3191PZTAG
UDFN6
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NTLUD3191PZTBG
UDFN6
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTLUD3191PZ
PACKAGE DIMENSIONS
UDFN6 1.6x1.6, 0.5P
CASE 517AT−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
B
2X
L
0.10
C
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DETAIL A
OPTIONAL
CONSTRUCTION
PIN ONE
REFERENCE
E
MILLIMETERS
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
2X
A
0.10
C
MOLD CMPD
EXPOSED Cu
A3
b
D
E
0.13 REF
0.20
1.60 BSC
1.60 BSC
0.50 BSC
TOP VIEW
0.30
A3
A
(A3)
e
DETAIL B
D1 1.14
D2 0.38
E1 0.54
1.34
0.58
0.74
−−−
0.35
0.10
0.05
0.05
C
C
A1
DETAIL B
K
L
L1
0.20
0.15
−−−
OPTIONAL
6X
CONSTRUCTION
SIDE VIEW
SEATING
PLANE
C
A1
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
D1
DETAIL A
6X K
2X
D2
E1
3
1
1.34
2X
0.58
6
4
6X b
6X L
6X
0.48
0.10
0.05
C A B
e
0.74 1.90
NOTE 3
C
BOTTOM VIEW
1
0.50 PITCH
6X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTLUD3191PZ/D
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