NOIP1SE1300A-QTI_技术文档

NOIP1SN1300A

PYTHON 1.3/0.5/0.3 MegaPixels

Global Shutter CMOS

Image Sensors

FEATURES

• Size Options:

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♦ PYTHON 300: 640 x 480 Active Pixels, 1/4” Optical Format

♦ PYTHON 500: 800 x 600 Active Pixels, 1/3.6” Optical Format

♦ PYTHON 1300: 1280 x 1024 Active Pixels, 1/2” Optical Format

• Data Output Options:

♦ P1−SN/SE/FN: 4 LVDS Data Channels

♦ P2−SN/SE: 10 bit Parallel

♦ P3−SN/SE/FN: 2 LVDS Data Channels

• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with In-pixel CDS

• Monochrome (SN), Color (SE) and NIR (FN)

• Zero Row Overhead Time (ZROT) Mode Enabling Higher Frame

Rate

• Frame Rate at Full Resolution, 4 LVDS Data Channels

(P1−SN/SE/FN only)

♦ 210/165 frames per second @ SXGA (ZROT/NROT)

♦ 545/385 frames per second @ SVGA (ZROT/NROT)

Figure 1. PYTHON 1300

DESCRIPTION

♦ 815/545 frames per second @ VGA (ZROT/NROT)

• Frames Rate at Full Resolution (CMOS)

♦ 50/43 Frames per Second @ SXGA (ZROT/NROT)

• On−chip 10−bit Analog−to−Digital Converter (ADC)

• Four/Two/One LVDS High Speed Serial Outputs or

Parallel CMOS Output

• Random Programmable Region of Interest (ROI)

Readout

• Serial Peripheral Interface (SPI)

• Automatic Exposure Control (AEC)

• Phase Locked Loop (PLL)

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors utilize high sensitivity 4.8 mm x 4.8 mm pixels

that support low noise “pipelined” and “triggered” global

shutter readout modes. The sensors support correlated

double sampling (CDS) readout, reducing noise and

increasing dynamic range.

The image sensors have on−chip programmable gain

amplifiers and 10−bit A/D converters. The integration time

and gain parameters can be reconfigured without any visible

image artifact. Optionally the on−chip automatic exposure

control loop (AEC) controls these parameters dynamically.

The image’s black level is either calibrated automatically or

can be adjusted by adding a user programmable offset.

A high level of programmability using a four wire serial

peripheral interface enables the user to read out specific

regions of interest. Up to eight regions can be programmed,

achieving even higher frame rates.

The image data interface of the P1−SN/SE/FN devices

consists of four LVDS lanes, enabling frame rates up to 210

frames per second in Zero ROT mode for the

PYTHON 1300. Each channel runs at 720 Mbps. A separate

synchronization channel containing payload information is

provided to facilitate the image reconstruction at the

receiving end. The P2−SN/SE devices provide a parallel

CMOS output interface at reduced frame rate. The

P3−SN/SE/FN devices are the same as the P1−SN/SE/FN

but with only two of the four LVDS data channels enabled,

facilitating frame rates of 90 frames per second in Normal

ROT for the PYTHON 1300.

• High Dynamic Range (HDR) Modes Possible

• Dual Power Supply (3.3 V and 1.8 V)

• −40°C to +85°C Operational Temperature Range

• 48−pin LCC

• Power Dissipation:

♦ 620 mW (P1, 4 LVDS, ZROT)

♦ 420 mW (P1, P3, 2 LVDS, NROT)

♦ 270 mW (P1, P3, 1 LVDS, NROT)

♦ 420 mW (P2, ZROT)

• These Devices are Pb−Free and are RoHS Compliant

APPLICATIONS

• Machine Vision

• Motion Monitoring

• Security

• Barcode Scanning (2D)

1

Publication Order Number:

November, 2017 − Rev. 4

NOIP1SN1300A/D

NOIP1SN1300A

The devices are provided in a 48−pin LCC package and are available in monochrome, Bayer color, and extended

near−infrared (NIR) configurations.

ORDERING INFORMATION

Part Number

PYTHON 1300

Description

Package

NOIP1SN1300A−QDI

NOIP1SE1300A−QDI

NOIP1FN1300A−QDI

NOIP2SN1300A−QDI

NOIP2SE1300A−QDI

NOIP1SN1300A−QTI

NOIP1SE1300A−QTI

NOIP1FN1300A−QTI

NOIP3SN1300A−QDI

NOIP3FN1300A−QDI

NOIP3SE1300A−QDI

NOIP3SN1300A−QTI

NOIP3FN1300A−QTI

NOIP3SE1300A−QTI

PYTHON 500

1.3 Megapixel, Monochrome, LVDS Output

1.3 Megapixel, Bayer Color, LVDS Output

1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output

1.3 Megapixel, Monochrome, CMOS (parallel) Output

1.3 Megapixel, Bayer Color, CMOS (parallel) Output

1.3 Megapixel, Monochrome, LVDS Output, Protective Foil

1.3 Megapixel, Bayer Color, LVDS Output, Protective Foil

1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

1.3 Megapixel, 2 LVDS Outputs, Monochrome

48−pin LCC

1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome

1.3 Megapixel, 2 LVDS Outputs, Color

1.3 Megapixel, 2 LVDS Outputs, Monochrome, Protective Foil

1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome, Protective Foil

1.3 Megapixel, 2 LVDS Outputs, Color, Protective Foil

NOIP1SN0500A−QDI

NOIP1SE0500A−QDI

NOIP1FN0500A−QDI

NOIP1SN0500A−QTI

NOIP1SE0500A−QTI

NOIP1FN0500A−QTI

PYTHON 300

0.5 Megapixel, Monochrome, LVDS Output

0.5 Megapixel, Bayer Color, LVDS Output

0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output

0.5 Megapixel, Monochrome, LVDS Output, Protective Foil

0.5 Megapixel, Bayer Color, LVDS Output, Protective Foil

0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

48−pin LCC

NOIP1SN0300A−QDI

NOIP1SE0300A−QDI

NOIP1FN0300A−QDI

NOIP1SN0300A−QTI

NOIP1SE0300A−QTI

NOIP1FN0300A−QTI

0.3 Megapixel, Monochrome, LVDS Output

0.3 Megapixel, Bayer Color, LVDS Output

0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output

0.3 Megapixel, Monochrome, LVDS Output, Protective Foil

0.3 Megapixel, Bayer Color, LVDS Output, Protective Foil

0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

48−pin LCC

The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 4 LVDS interface; the P2−SN/SE

base part references the mono and color versions of the CMOS interface; the P3−SN/SE/FN base part references the mono,

color and NIR enhanced version of the 2 LVDS interface. More details on the part number coding can be found at

http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF

Production Package Mark

Line 1: NOIPyxxRRRRA where y is either “1” for 4 LVDS Outputs, “2” for CMOS Parallel Output, “3” for 2 LVDS Outputs,

where xx denotes mono micro lens (SN) or color micro lens (SE) or NIR micro lens (FN)

RRRR is the resolution (1300), (0500) or (0300)

Line 2: −QDI (without protective foil), −QTI (with protective foil)

Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code

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2

NOIP1SN1300A

SPECIFICATIONS

Key Specifications

Table 1. GENERAL SPECIFICATIONS

Table 2. ELECTRO−OPTICAL SPECIFICATIONS

Parameter

Pixel type

Specification

Parameter

Active pixels

Specification

In−pixel CDS. Global shutter pixel

architecture

PYTHON 300: 640 (H) x 480 (V)

PYTHON 500: 800 (H) x 600 (V)

PYTHON 1300: 1280 (H) x 1024 (V)

Shutter type

Frame rate

Pipelined and triggered global shutter

Pixel size

4.8 mm x 4.8 mm

P1−SN/SE/FN:

−

Conversion gain

0.096 LSB10/e

PYTHON 300: 815/545 fps

PYTHON 500: 545/385 fps

PYTHON 1300: 210/165 fps

P2−SN/SE: 50/43 fps

Zero ROT/

Normal ROT

mode

−

140 mV/e

−

Dark temporal noise

< 9 e (Normal ROT, 1x gain)

< 7 e (Normal ROT, 2x gain)

P3−SN/SE/FN: NA/90 fps

Responsivity

at 550 nm

7.7 V/lux.s

<1/8000

Master clock

Windowing

P1, P3−SN/SE/FN:

72 MHz when PLL is used,

360 MHz (10−bit) / 288 MHz (8−bit)

when PLL is not used

Parasitic Light

Sensitivity (PLS)

P2−SN/SE: 72 MHz

−

Full Well Charge

10000 e

8 Randomly programmable windows. Nor-

mal, sub−sampled and binned readout

modes

Quantum Efficiency

at 550 nm

56%

ADC resolution

LVDS outputs

10−bit, 8−bit (Note 1)

Pixel FPN

PRNU

< 1.0 LSB10

P1−SN/SE/FN: 4/2/1 data + sync + clock

P3−SN/SE/FN: 2/1 data + sync + clock

< 2% or 10 LSB10 on half scale

response of 525LSB10

CMOS outputs

Data rate

P2−SN/SE: 10−bit parallel output,

frame_valid, line_valid, clock

MTF

68% @ 535 nm − X−dir & Y−dir

−

PSNL at 20°C

Dark signal at 20°C

Dynamic Range

120 LSB10/s, 1200 e /s

P1−SN/SE/FN:

4 x 720 Mbps (10−bit) /

4 x 576 Mbps (8−bit)

P2−SN/SE: 72 Mhz

P3−SN/SE/FN: 2 x 720 Mbps (10−bit)

−

5 e /s, 0.5 LSB10/s

> 60 dB in global shutter mode

40 dB

Signal to Noise Ratio

(SNR max)

Power

dissipation

(10−bit mode)

P1−SN/SE/FN: 620 mW (4 data channels)

P1, P3−SN/SE/FN: 420 mW (2 data ch.)

P1, P3−SN/SE/FN: 270 mW (1 data ch.)

P2−SN/SE: 420 mW

Package type

48−pin LCC

Table 3. RECOMMENDED OPERATING RATINGS (Note 2)

Symbol

Description

Operating temperature range

Min

Max

Unit

T

J

−40

85

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)

Symbol

Parameter

ABS rating for 1.8 V supply group

Min

–0.5

−40

Max

2.2

Unit

V

ABS (1.8 V supply group)

ABS (3.3 V supply group)

ABS rating for 3.3 V supply group

ABS storage temperature range

4.3

V

T

S

+150

85

°C

ABS storage humidity range at 85°C

Human Body Model (HBM): JS−001−2010

Charged Device Model (CDM): JESD22−C101

Latch−up: JESD−78

%RH

V

Electrostatic discharge (ESD)

2000

500

LU

100

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.

2. Operating ratings are conditions in which operation of the device is intended to be functional.

3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer

to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.

4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can

absorb moisture if the sensor is placed in a high % RH environment.

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NOIP1SN1300A

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for T = T

to T

, all other limits T = +30°C. (Notes 5, 6, 7, 8 and 9)

J

MIN

MAX

J

Parameter

Description

Min

Typ

Max

Unit

Power Supply Parameters − P1 − SN/SE/FN LVDS (ZROT)

(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)

vdd_33

Idd_33

vdd_18

Idd_18

vdd_pix

Idd_pix

Ptot

Supply voltage, 3.3 V

3.2

3.3

140

1.8

80

3.4

1.9

V

mA

V

Current consumption 3.3 V supply

Supply voltage, 1.8 V

1.7

Current consumption 1.8 V supply

Supply voltage, pixel

mA

V

3.25

3.3

5

3.35

Current consumption pixel supply

mA

mW

Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

P1−SN/SE/FN, 4 LVDS, ZROT

620

Pstby_lp

Popt

Power consumption in low power standby mode

Power consumption at lower pixel rates

50

mW

Configurable

Power Supply Parameters − P3 − SN/SE/FN LVDS (NROT)

(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)

vdd_33

Idd_33

vdd_18

Idd_18

vdd_pix

Idd_pix

Ptot

Supply voltage, 3.3 V

3.2

3.3

95 / 55

1.8

3.4

1.9

V

mA

V

Current consumption 3.3 V supply (2 / 1 LVDS)

Supply voltage, 1.8 V

1.7

Current consumption 1.8 V supply (2 / 1 LVDS)

Supply voltage, pixel

55 / 45

3.3

mA

V

3.25

3.35

Current consumption pixel supply (2 / 1 LVDS)

2 / 1

mA

mW

Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

P3−SN/SE/FN, 2 LVDS, NROT

P3−SN/SE/FN, 1 LVDS, NROT

420

270

Pstby_lp

Popt

Power consumption in low power standby mode

Power consumption at lower pixel rates

50

mW

Configurable

Power Supply Parameters − P2−SN/SE CMOS

vdd_33

Idd_33

vdd_18

Idd_18

vdd_pix

Idd_pix

Ptot

Supply voltage, 3.3 V

3.2

1.7

3.3

120

1.8

10

3.4

1.9

V

mA

V

Current consumption 3.3 V supply

Supply voltage, 1.8 V

Current consumption 1.8 V supply

Supply voltage, pixel

mA

V

3.25

3.3

1

3.35

Current consumption pixel supply

Total power consumption

mA

mW

420

Pstby_lp

Popt

Power consumption in low power standby mode

Power consumption at lower pixel rates

50

Configurable

I/O − P1−SN/SE/FN, P3−SN/SE/FN LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed

fserdata

Data rate on data channels

720

Mbps

DDR signaling − 4 data channels, 1 synchronization channel

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. All parameters are characterized for DC conditions after thermal equilibrium is established.

6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is

recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high

impedance circuit.

7. Minimum and maximum limits are guaranteed through test and design.

8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.

9. For power supply management recommendations, please refer to Application Note AND9158.

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4

NOIP1SN1300A

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for T = T

to T

, all other limits T = +30°C. (Notes 5, 6, 7, 8 and 9)

J

MIN

MAX

J

Parameter

Description

Clock rate of output clock

Min

Typ

Max

Unit

fserclock

360

MHz

Clock output for mesochronous signaling

Vicm

LVDS input common mode level

0.3

1.25

1.8

50

V

Tccsk

Channel to channel skew (Training pattern allows per channel

skew correction)

ps

I/O − P2−SN/SE CMOS (JEDEC− JESD8C−01): Conforming to standard/additional specifications and deviations listed

fpardata

Data rate on parallel channels (10−bit)

Output load (only capacitive load)

Rise time (10% to 90% of input signal)

Fall time (10% to 90% of input signal)

72

10

6.5

5

Mbps

pF

Cout

tr

tf

2.5

2

4.5

3.5

ns

Electrical Interface − P1 − SN/SE/FN LVDS

fin

tidc

tj

Input clock rate when PLL used

72

360

55

MHz

%

Input clock when LVDS input used

Input clock duty cycle when PLL used

Input clock jitter

45

50

20

ps

ratspi

(= fin/fspi)

10−bit (4 LVDS channels), PLL used

10−bit (2 LVDS channels), PLL used

10−bit (1 LVDS channel), PLL used

10−bit (4 LVDS channels), LVDS input used

10−bit (2 LVDS channels), LVDS input used

10−bit (1 LVDS channel), LVDS input used

8−bit (4 LVDS channels), PLL used

8−bit (2 LVDS channels), PLL used

8−bit (1 LVDS channel), PLL used

8−bit (4 LVDS channels), LVDS input used

8−bit (2 LVDS channels), LVDS input used

8−bit (1 LVDS channel), LVDS input used

6

12

24

30

60

120

6

12

24

48

96

Electrical Interface − P2−SN/SE CMOS

fin

tidc

tj

Input clock rate

72

55

20

MHz

%

Input clock duty cycle

Input clock jitter

45

24

50

ps

ratspi

10−bit, PLL bypassed

(= fin/fspi)

Electrical Interface − P3 − SN/SE/FN LVDS

fin

tidc

tj

Input clock rate when PLL used

Input clock when LVDS input used

Input clock duty cycle when PLL used

Input clock jitter

72

360

55

MHz

%

45

50

20

ps

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. All parameters are characterized for DC conditions after thermal equilibrium is established.

6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is

recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high

impedance circuit.

7. Minimum and maximum limits are guaranteed through test and design.

8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.

9. For power supply management recommendations, please refer to Application Note AND9158.

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5

NOIP1SN1300A

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for T = T

to T

, all other limits T = +30°C. (Notes 5, 6, 7, 8 and 9)

J

MIN

MAX

J

Parameter

Description

Min

12

Typ

Max

288

Unit

ratspi

(= fin/fspi)

10−bit (2 LVDS channels), PLL used

10−bit (1 LVDS channel), PLL used

24

10−bit (2 LVDS channels), LVDS input used

10−bit (1 LVDS channel), LVDS input used

60

120

Frame Specifications − P1−SN/SE/FN−LVDS (ZROT)

Maximum

Normal ROT

165

Zero ROT

210

Units

fps

Frame rate at full resolution

Xres x Yres = 1024 x 1024

Xres x Yres = 800 x 600

Xres x Yres = 640 x 480

Xres x Yres = 512 x 512

Xres x Yres = 256 x 256

Pixel rate (4 channels at 72 Mpix/s)

fps_roi1

fps_roi2

fps_roi3

fps_roi4

fps_roi5

fpix

195

260

fps

385

545

fps

545

815

fps

580

925

fps

1400

2235

fps

Mpix/s

Frame Specifications − P2−SN/SE CMOS

Maximum

Normal ROT

Zero ROT

Units

fps

Frame rate at full resolution

43

50

fps

Frame Specifications − P3−SN/SE/FN LVDS (NROT)

Maximum

2 LVDS

90

1 LVDS

45

Max

Units

fps

Frame rate at full resolution

Xres x Yres = 1024 x 1024

Xres x Yres = 800 x 600

Xres x Yres = 640 x 480

Xres x Yres = 512 x 512

Xres x Yres = 256 x 256

Pixel rate (4 channels at 72 Mpix/s)

fps_roi1

fps_roi2

fps_roi3

fps_roi4

fps_roi5

fpix

110

55

fps

230

120

185

205

660

fps

340

fps

375

fps

1110

fps

144

Mpix/s

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. All parameters are characterized for DC conditions after thermal equilibrium is established.

6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is

recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high

impedance circuit.

7. Minimum and maximum limits are guaranteed through test and design.

8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.

9. For power supply management recommendations, please refer to Application Note AND9158.

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6

NOIP1SN1300A

Color Filter Array

The PYTHON color sensors are processed with a Bayer RGB color pattern as shown in Figure 2. Pixel (0,0) has a red filter

situated to the bottom left.

Y

Gb

Gr

X

pixel (0;0)

Figure 2. Color Filter Array for the Pixel Array

Quantum Efficiency

60.0%

Red

50.0%

40.0%

30.0%

20.0%

10.0%

0.0%

Gr

Gb

Blue

Mono

300

400

500

600

700

800

900

1000

1100

Wavelength [nm]

Figure 3. Quantum Efficiency Curve for Mono and Color

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7

NOIP1SN1300A

70

60

50

40

30

20

10

0

MONO

NIR

300

400

500

600

700

800

900

1000

1100

Wavelengths [nm]

Figure 4. Quantum Efficiency Curve for Standard and NIR Mono

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8

NOIP1SN1300A

Ray Angle and Microlens Array Information

regards to its photodiode. A shift in microlens position

versus photodiode position will cause a tilted angle of peak

photoresponse, here denoted Chief Ray Angle (CRA).

Microlenses and photodiodes are aligned with 0 shift and

CRA in the center of the array, while the shift and CRA

increases radially towards its edges, as illustrated by

Figure 7.

The purpose of the shifted microlenses is to improve the

uniformity of photoresponse when camera lenses with a

finite exit pupil distance are used. The CRA varies nearly

linearly with distance from the center as illustrated in Figure

8, with a corner CRA of approximately 2.7 degrees. This

edge CRA is matching a lens with exit pupil distance of

∼ 80 mm.

An array of microlenses is placed over the CMOS pixel

array in order to improve the absolute responsivity of the

photodiodes. The combined microlens array and pixel array

has two important properties:

1. Angular dependency of photoresponse of a pixel

The photoresponse of a pixel with microlens in the center

of the array to a fixed optical power with varied incidence

angle is as plotted in Figure 5, where definitions of angles fx

and fy are as described by Figure 6.

2. Microlens shift across array and CRA

The microlens array is fabricated with a slightly smaller

pitch than the array of photodiodes. This difference in pitch

creates a varying degree of shift of a pixel’s microlens with

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

fx = 0

fy = 0

0.2

0.1

0

−30

−20

−10

0

10

20

30

Incidence Angle f , f

x

y

[degrees deviation from normal]

Note that the photoresponse peaks near normal incidence for center pixels.

Figure 5. Central Pixel Photoresponse to a Fixed Optical Power with Incidence Angle varied along f_xand f_y

Figure 6. Definition of Angles used in Figure 5.

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NOIP1SN1300A

Shift

CRA

Center pixel

(aligned)

Edge pixel

(with shift)

The center axes of the microlens and the photodiode coincide for the center pixels. For the edge pixels,

there is a shift between the axes of the microlens and the photodiode causing a Peak Response Incidence

Angle (CRA) that deviates from the normal of the pixel array.

Figure 7. Principles of Microlens Shift

3

2.7

2.5

2.1

2

1.7

1.5

diagonal

1

x direction

y direction

0.5

0

1

2

3

4

Distance from Center [mm]

Figure 8. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array

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NOIP1SN1300A

OVERVIEW

Figures 9 and 10 give an overview of the major functional blocks of the P1−SN/SE/FN, P3−SN/SE/FN and P2−SN/SE sensor

respectively.

Image Core

Image Core Bias

Pixel Array

Column Structure

Automatic

Exposure

Control

Automatic

Exposure

Control

8 analog channels

(AEC)

Analog Front End (AFE)

8 x 10 bit

Control &

Registers

Control &

Registers

digital channels

Clock

Data Formatting

Output MUX

Data Formatting

Distribution

Clock

4 x 10 bit

Distribution

digital channels

CMOS Clock

Serializers & LVDS Interface

PLL

LVDS

PLL

Receiver

CMOS Clock

Input

10 bit Parallel Data

CMOS Interface

4, 2, 1 Multiplexed LVDS Output Channels

1 LVDS Sync Channel

Frame Valid Indication

Line Valid Indication

CMOS Clock

Input

LVDS Clock

Input

1 LVDS Clock Channel

Note: P3 part only has 2,1 Multiplexed LVDS Output Channels

Figure 9. Block Diagram − P1−SN/SE/FN,

P3−SN/SE/FN

Figure 10. Block Diagram − P2−SN/SE

Image Core

Phase Locked Loop

The PLL accepts a (low speed) clock and generates the

required high speed clock. Optionally this PLL can be

bypassed. Typical input clock frequency is 72 MHz.

The image core consists of:

• Pixel Array

• Address Decoders and Row Drivers

• Pixel Biasing

LVDS Clock Receiver

The LVDS clock receiver receives an LVDS clock signal

and distributes the required clocks to the sensor.

Typical input clock frequency is 360 MHz in 10−bit mode

and 288 MHz in 8−bit mode. The clock input needs to be

terminated with a 100 W resistor.

The PYTHON 1300 pixel array contains 1280 (H) x

1024 (V) readable pixels with a pixel pitch of 4.8 mm. The

PYTHON 300 and PYTHON 500 image arrays contain

672 (H) x 512 (V) and 832 (H) x 632 (V) readable pixels

respectively, inclusive of 16 pixel rows and 16 pixel

columns at every side to allow for reprocessing or color

reconstruction. The sensors use in−pixel CDS architecture,

which makes it possible to achieve a low noise read out of

the pixel array in global shutter mode with CDS.

The function of the row drivers is to access the image array

line by line, or all lines together, to reset or read the pixel

data. The row drivers are controlled by the on−chip

sequencer and can access the pixel array.

Column Multiplexer

All pixels of one image row are stored in the column

sample−and−hold (S/H) stages. These stages store both the

reset and integrated signal levels.

The data stored in the column S/H stages is read out

through 8 parallel differential outputs operating at a

frequency of 36 MHz. At this stage, the reset signal and

integrated signal values are transferred into an

FPN−corrected differential signal. A programmable gain of

1x, 2x, or 4x can be applied to the signal. The column

The pixel biasing block guarantees that the data on a pixel

is transferred properly to the column multiplexer when the

row drivers select a pixel line for readout.

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11

NOIP1SN1300A

multiplexer

also

supports

read−1−skip−1

and

In addition to the LVDS data outputs, two extra LVDS

read−2−skip−2 mode. Enabling this mode increases the

frame rate, with a decrease in resolution.

outputs are available. One of these outputs carries the output

clock, which is skew aligned to the output data channels. The

second LVDS output contains frame format synchronization

codes to serve system−level image reconstruction.

Bias Generator

The bias generator generates all required reference

voltages and bias currents used on chip. An external resistor

of 47 kW, connected between pin IBIAS_MASTER and

gnd_33, is required for the bias generator to operate

properly.

Output MUX (P2−SN/SE)

The output MUX multiplexes the four data channels to

one channel and transmits the data words using a 10−bit

parallel CMOS interface.

Frame synchronization information is communicated by

means of frame and line valid strobes.

Analog Front End

The AFE contains 8 channels, each containing a PGA and

a 10−bit ADC.

Channel Multiplexer

For each of the 8 channels, a pipelined 10−bit ADC is used

to convert the analog image data into a digital signal, which

is delivered to the data formatting block. A black calibration

loop is implemented to ensure that the black level is mapped

to match the correct ADC input level.

The P1−SN/SE/FN LVDS channel multiplexer provides

a 4:2 and 4:1 feature, in addition to utilizing all 4 output

channels.

The P3− SN/SE/FN LVDS channel multiplexer provides

a 2:1 feature, in addition to utilizing both the output

channels.

Data Formatting

The data block receives data from two ADCs and

multiplexes this data to one data stream. A cyclic

redundancy check (CRC) code is calculated on the passing

data.

Sequencer

The sequencer:

• Controls the image core. Starts and stops integration

and control pixel readout.

A

frame synchronization data block transmits

• Operates the sensor in master or slave mode.

synchronization codes such as frame start, line start, frame

end, and line end indications.

The data block calculates a CRC once per line for every

channel. This CRC code can be used for error detection at the

receiving end.

• Applies the window settings. Organizes readouts so that

only the configured windows are read.

• Controls the column multiplexer and analog core.

Applies gain settings and subsampling modes at the

correct time, without corrupting image data.

Serializer and LVDS Interface (P1−SN/SE/FN,

P3−SN/SE/FN only)

The serializer and LVDS interface block receives the

formatted (10−bit or 8−bit) data from the data formatting

block. This data is serialized and transmitted by the LVDS

288 MHz output driver.

In 10−bit mode, the maximum output data rate is

720 Mbps per channel. In 8−bit mode, the maximum output

data rate is 576 Mbps per channel.

• Starts up the sensor correctly when leaving standby

mode.

Automatic Exposure Control

The AEC block implements a control system to modulate

the exposure of an image. Both integration time and gains

are controlled by this block to target a predefined

illumination level.

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12

FOT

Readout Fra

e

-1

eadout Fra e N

Integration Ti

Handling

e

Reset

N

Reset

N+1

NOIP1SN1300A

OPERATING MODES

Global Shutter Mode

at the same period of time. The whole pixel core is reset

simultaneously and after the integration time all pixel values

are sampled together on the storage node inside each pixel.

The pixel core is read out line by line after integration. Note

that the integration and readout can occur in parallel or

sequentially. The integration starts at a certain period,

relative to the frame start.

The PYTHON 300, PYTHON 500, and PYTHON 1300

operate in pipelined or triggered global shuttering modes. In

this mode, light integration, light integration takes place on

all pixels in parallel, although subsequent readout is

sequential. Figure 11 shows the integration and readout

sequence for the global shutter. All pixels are light sensitive

Figure 11. Global Shutter Operation

Pipelined Global Shutter Mode

In pipelined global shutter mode, the integration and

readout are done in parallel. Images are continuously read

and integration of frame N is ongoing during readout of the

previous frame N−1. The readout of every frame starts with

a Frame Overhead Time (FOT), during which the analog

value on the pixel diode is transferred to the pixel memory

element. After the FOT, the sensor is read out line per line

and the readout of each line is preceded by the Row

Overhead Time (ROT). Figure 12 shows the exposure and

readout time line in pipelined global shutter mode.

Master Mode

The PYTHON 300, PYTHON 500, and PYTHON 1300

operate in pipelined or triggered global shuttering modes. In

this mode, light, the integration time is set through the

register interface and the sensor integrates and reads out the

images autonomously. The sensor acquires images without

any user interaction.

Exposure Time N

FOT

Exposure Time N+1

FOT

Readout

Handling

ROT

Line Readout

Figure 12. Integration and Readout for Pipelined Shutter

Slave Mode

of reset and integration starts. The integration continues

until the user or system deasserts the external pin. Upon a

falling edge of the trigger input, the image is sampled and the

readout begins. Figure 13 shows the relation between the

external trigger signal and the exposure/readout timing.

The slave mode adds more manual control to the sensor.

The integration time registers are ignored in this mode and

the integration time is instead controlled by an external pin.

As soon as the control pin is asserted, the pixel array goes out

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13

Exposure Ti

Register Controlled

Readout -1

FOT

Exposure Ti

Readout N

e N

e

+1

FOT

Integration Ti

Handling

e

Reset

N

Reset

N+1

NOIP1SN1300A

External Trigger

Integration Time

Handling

Reset

N

Reset

N+1

Exposure Time N

FOT

Exposure T im e N+1

Readout N

FOT

Readout

Handling

FOT

Readout N−1

ROT

Line Readout

Figure 13. Pipelined Shutter Operated in Slave Mode

Triggered Global Shutter Mode

The triggered global mode can also be controlled in a

master or in a slave mode.

In this mode, manual intervention is required to control

both the integration time and the start of readout. After the

integration time, indicated by a user controlled pin, the

image core is read out. After this sequence, the sensor goes

to an idle mode until a new user action is detected.

The three main differences with the pipelined global

shutter mode are:

Master Mode

In this mode, a rising edge on the synchronization pin is

used to trigger the start of integration and readout. The

integration time is defined by a register setting. The sensor

autonomously integrates during this predefined time, after

which the FOT starts and the image array is readout

sequentially. A falling edge on the synchronization pin does

not have any impact on the readout or integration and

subsequent frames are started again for each rising edge.

Figure 14 shows the relation between the external trigger

signal and the exposure/readout timing.

• Upon user action, one single image is read.

• Normally, integration and readout are done

sequentially. However, the user can control the sensor

in such a way that two consecutive batches are

overlapping, that is, having concurrent integration and

readout.

If a rising edge is applied on the external trigger before the

exposure time and FOT of the previous frame is complete,

it is ignored by the sensor.

• Integration and readout is under user control through an

external pin.

This mode requires manual intervention for every frame.

The pixel array is kept in reset state until requested.

No effect on falling edge

External Trigger

Readout

Handling

ROT

Line Readout

Figure 14. Triggered Shutter Operated in Master Mode

Slave Mode

FOT starts. The analog value on the pixel diode is

transferred to the pixel memory element and the image

readout can start. A request for a new frame is started when

the synchronization pin is asserted again.

Integration time control is identical to the pipelined

shutter slave mode. An external synchronization pin

controls the start of integration. When it is de−asserted, the

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14

NOIP1SN1300A

Normal and Zero Row Overhead Time (ROT) Modes

can thus be longer, however the perceived ROT will be

shorter (‘overhead’ spent per line is reduced). The

integration time and gain parameters can be reconfigured

without any visible image artifact in Normal ROT mode.

Column−level offset corrections are required in Zero ROT

mode. Refer to Column−Level Image Correction

application note in the PYTHON Developer’s Guide

AND9362/D available at the Image Sensor Portal.

In pipelined global shutter mode, the integration and

readout are done in parallel. Images are continuously read

out and integration of frame N is ongoing during readout of

the previous frame N−1. The readout of every frame starts

with a Frame Overhead Time (FOT), during which the

analog value of the pixel diode is transferred to the pixel

memory element. After the FOT, the sensor is read out line

by line and the readout of each line is preceded by a Row

Overhead Time (ROT) as shown in Figure 15.

In Reduced/Zero ROT operation mode (refer to

Figure 16), the row blanking and kernel readout occur in

parallel. This mode is called reduced ROT as a part of the

ROT is done while the image row is readout. The actual ROT

This operation mode can be used for two reasons:

• Reduced total line time.

• Lower power due of reduced clock−rate.

NOTE: Zero ROT is not supported on P3−SN/SE/FN

devices.

FOT

(

)

ROT

ys

Readout

ys

ROT

ys+1

Readout

ys

ROT

ye

Readout

ye

Valid Data

Figure 15. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with

Normal ROT Readout.

FOT

(

)

ROT

ys

(blanked ou)t

ROT

ys+1

Readout

ys

ROT

ye

Readout

ye−1

ROT

dummy

Readout

ye

Valid Data

Figure 16. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with

Zero ROT Readout.

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15

NOIP1SN1300A

SENSOR OPERATION

Flowchart

Figure 17 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval

circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.

Power Off

Power Down

Sequence

Power Up Sequence

Low-Power Standby

Disable Clock Management

Part 1

Enable Clock Management - Part 1

Poll Lock Indication

(only when PLL is enabled)

Standby (1)

Enable Clock Management - Part 2

(First Pass after Hard Reset)

Disable Clock Management

Part 2

Intermediate Standby

Required Register

Upload

Sensor (re-)configuration

(optional)

Standby (2)

Soft Power-Down

Soft Power-Up

Sensor (re-)configuration

(optional)

Idle

Enable Sequencer

Disable Sequencer

Sensor (re-)configuration

(optional)

Running

Figure 17. Sensor Operation Flowchart

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16

NOIP1SN1300A

Sensor States

Running

In running state, the sensor is enabled and grabbing

images. The sensor can be operated in global master/slave

modes.

Low Power Standby

In low power standby state, all power supplies are on, but

internally every block is disabled. No internal clock is

running (PLL / LVDS clock receiver is disabled).

All register settings are unchanged.

Only a subset of the SPI registers is active for read/write

in order to be able to configure clock settings and leave the

low power standby state. The only SPI registers that should

be touched are the ones required for the ‘Enable Clock

Management’ action described in Enable Clock

Management − Part 1 on page 18

User Actions: Power Up Functional Mode Sequences

Power Up Sequence

Figure 18 shows the power up sequence of the sensor. The

figure indicates that the first supply to ramp−up is the

vdd_18 supply, followed by vdd_33 and vdd_pix

respectively. It is important to comply with the described

sequence. Any other supply ramping sequence may lead to

high current peaks and, as consequence, a failure of the

sensor power up.

Standby (1)

In standby state, the PLL/LVDS clock receiver is running,

but the derived logic clock signal is not enabled.

The clock input should start running when all supplies are

stabilized. When the clock frequency is stable, the reset_n

signal can be de−asserted. After a wait period of 10 ms, the

power up sequence is finished and the first SPI upload can

be initiated.

Standby (2)

In standby state, the derived logic clock signal is running.

All SPI registers are active, meaning that all SPI registers

can be accessed for read or write operations. All other blocks

are disabled.

NOTE: The ‘clock input’ can be the CMOS PLL clock

input (clk_pll), or the LVDS clock input

(lvds_clock_inn/p) in case the PLL is bypassed.

Idle

In the idle state, all internal blocks are enabled, except the

sequencer block. The sensor is ready to start grabbing

images as soon as the sequencer block is enabled.

clock input

reset_n

vdd_18

vdd_33

vdd_pix

SPI Upload

> 10us

Figure 18. Power Up Sequence

Enable Clock Management − Part 1

serial, P2−SN/SE 10−bit parallel, ...) are available to

customers under NDA at the ON Semiconductor Image

Sensor Portal.

In the serial modes, if the PLL is not used, the LVDS clock

input must be running.

In the P2−SN/SE 10−bit parallel mode, the PLL is

bypassed. The clk_pll clock is used as sensor clock.

It is important to follow the upload sequence listed in

Table 6.

The ‘Enable Clock Management’ action configures the

clock management blocks and activates the clock generation

and distribution circuits in a pre−defined way. First, a set of

clock settings must be uploaded through the SPI register.

These settings are dependent on the desired operation mode

of the sensor.

Table 6 shows the SPI uploads to be executed to configure

the sensor for P1−SN/SE/FN, P3−SN/SE/FN 10−bit serial

mode, with the PLL, and all available LVDS channels.

Note that the SPI uploads to be executed to configure the

sensor for other supported modes (P1−SN/SE/FN 8−bit

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17

NOIP1SN1300A

Use of Phase Locked Loop

Check the PLL_lock flag 24[0] by reading the SPI

register. When the flag is set, the ‘Enable Clock

Management− Part 2’ action can be continued. When PLL

is not used, this step can be bypassed as shown in Figure 17

on page 16.

If PLL is used, the PLL is started after the upload of the

SPI registers. The PLL requires (dependent on the settings)

some time to generate a stable output clock. A lock detect

circuit detects if the clock is stable. When complete, this is

flagged in a status register.

NOTE: The lock detect status must not be checked for

the P2−SN/SE sensor.

Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL

1

2

0x0000

0x0001

0x0000

0x0003

0x2113

0x0000

0x2280

0x3D2D

0x7004

0x6014

Monochrome sensor

Color sensor

2

3

4

5

6

7

8

Release PLL soft reset

Enable PLL

16

17

20

26

27

32

Configure PLL

Configure clock management

Configure PLL lock detector

Configure clock management for P1 only

Configure clock management for P3 only

P2−SN/SE 10−bit mode

1

2

0x0002

0x0003

0x0007

0x0000

0x700C

Monochrome sensor

Color sensor

2

3

4

16

20

32

Enable PLL bypass mode

Configure clock management

Enable Clock Management − Part 2

The next step to configure the clock management consists

of SPI uploads which enables all internal clock distribution.

The required uploads are listed in Table 4. Note that it is

important to follow the upload sequence listed in Table 7.

Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL

1

2

9

0x0000

0x7006

0x6016

0x0001

Release clock generator soft reset

32

Enable logic clock for P1 only

Enable logic clock for P3 only

Enable logic blocks

3

34

P2−SN/SE 10−bit mode

1

2

3

9

0x0000

0x700E

0x0001

Release clock generator soft reset

Enable logic clock

32

34

Enable logic blocks

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18

NOIP1SN1300A

Required Register Upload

In this phase, the ‘reserved’ register settings are uploaded

through the SPI register. Different settings are not allowed

and may cause the sensor to malfunction. The required

uploads are listed in Table 8.

Table 8. REQUIRED REGISTER UPLOAD

P1−SN/SE/FN 10−bit

mode with PLL

P3−SN/SE/FN 10−bit

mode with PLL (2 LVDS

NROT)

P2−SN/SE 10−bit

mode (ZROT)

(4 LVDS ZROT)

0x085F

0x4100

0x0008

0x382B

0x53C8

0x0665

0x0085

0x0088

0x1111

Upload #

1

Address

41

Address

41

Address

41

0x085F

0x4100

0x0008

0x382B

0x53C8

0x0344

0x0085

0x0088

0x1111

0x0010

0x4714

0xA001

0x0001

0x1002

0x0080

0x00E6

0x0400

0x080C

0x0224

0x0103

0x01E1

0x0000

0x0E49

0x111F

0x7F00

0x0017

0x2C1C

0x623C

0x3E02

0x0000

0x2081

0xC800

0xFB1F

0xFB17

0xF802

0xF003

0xF30F

0x085F

0x4100

0x0008

0x382B

0x53C4

0x0645

0x0085

0x0048

0x1111

0x0017

0x4714

0x8001

0x1002

0x0080

0x00E6

0x0400

0x0800

0x0224

0x0306

0x01E3

0x0000

0x0E39

0x111F

0x7F00

0x0020

0x3728

0x6245

0x6230

0x3E5E

0x0000

0x2081

0xC800

0xFB1F

0xFB12

0xF903

0xF802

0xF30F

2

42

3

43

4

65

5

66

6

67

7

68

8

69

9

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

72

0x0010

0x4714

0x8001

0x1002

0x0080

0x00E6

0x0400

0x080C

0x0224

0x0306

0x01E1

0x0000

0x0E49

0x111F

0x7F00

0x0020

0x3A28

0x624D

0x3E5E

0x0000

0x2081

0xC800

0xFB1F

0xFB12

0xF903

0xF802

0xF30F

72

128

129

171

175

176

177

192

194

197

204

207

211

215

216

219

220

221

222

224

227

250

384

385

386

387

388

389

390

128

129

130

171

175

176

177

192

194

197

204

207

211

215

216

219

220

221

222

224

227

250

384

385

386

387

388

389

128

129

171

175

176

177

192

194

197

204

207

211

215

216

219

220

221

222

224

227

250

384

385

386

387

388

389

390

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19

NOIP1SN1300A

Table 8. REQUIRED REGISTER UPLOAD

P1−SN/SE/FN 10−bit

mode with PLL

P3−SN/SE/FN 10−bit

mode with PLL (2 LVDS

NROT)

P2−SN/SE 10−bit

mode (ZROT)

0xF30F

0xF101

0xF005

0xF247

0xF226

0xF002

0xF402

0xF001

0xF20F

0xF205

0xF002

0xC801

0xCC01

0xC802

0xC800

0xC801

0xCC04

0xC801

0xC800

0x0030

0x0078

0x0072

0x1071

0x3073

0x1073

0x0072

0x0031

0x00B1

0x01B8

0x00B2

0x10B1

0x30B3

0x10B3

0x00B2

0x0030

0x0178

(4 LVDS ZROT)

0xF30F

0xF30A

0xF101

0xF00A

0xF24B

0xF226

0xF001

0xF402

0xF001

0xF402

0xF001

0xF401

0xF007

0xF20F

0xF202

0xF006

0xEC02

0xE801

0xEC02

0xE801

0xEC02

0xC801

0xC800

0xCC02

0xC801

0xCC02

0xC801

0xCC02

0xC805

0xC800

0x0030

0x207C

0x2071

0x0074

0x107F

0x1072

0x1074

Upload #

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

Address

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

Address

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

Address

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

0xF30F

0xF30A

0xF101

0xF00A

0xF24B

0xF226

0xF001

0xF402

0xF001

0xF402

0xF001

0xF401

0xF007

0xF20F

0xF202

0xF006

0xEC02

0xE801

0xEC02

0xE801

0xEC02

0xC801

0xC800

0xCC02

0xC801

0xCC02

0xC801

0xCC02

0xC805

0xC800

0x0030

0x2073

0x2071

0x0071

0x1079

0x1072

0x0073

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20

NOIP1SN1300A

Table 8. REQUIRED REGISTER UPLOAD

P1−SN/SE/FN 10−bit

mode with PLL

P3−SN/SE/FN 10−bit

mode with PLL (2 LVDS

NROT)

P2−SN/SE 10−bit

mode (ZROT)

0x0072

0x1071

0x3073

0x1073

0x0072

0x0031

0x00B1

0x00B8

0x00B2

0x10B1

0x30B3

0x10B3

0x00B2

0x0030

(4 LVDS ZROT)

0x0076

0x0031

0x21BB

0x20B1

0x00B1

0x10BF

0x10B2

0x10B4

0x00B1

0x0030

0x217B

0x2071

0x0074

0x107F

0x1072

0x1074

0x0076

0x0031

0x20BB

0x20B1

0x00B1

0x10BF

0x10B2

0x10B4

0x00B1

0x0030

Upload #

79

Address

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

460

Address

430

431

432

433

434

435

436

437

438

439

440

441

442

443

Address

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

0x0031

0x21B6

0x20B1

0x00B1

0x10B9

0x10B2

0x00B1

0x0030

0x2176

0x2071

0x0071

0x1079

0x1072

0x0073

0x0031

0x20B3

0x00B1

0x10B9

0x10B2

0x00B1

0x0030

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

NOTE: Register uploads for other supported operation modes can be accessed at the Image Sensor Portal on MyON.

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21

NOIP1SN1300A

Soft Power Up

During the soft power up action, the internal blocks are

enabled and prepared to start processing the image data

stream. This action exists of a set of SPI uploads. The soft

power up uploads are listed in Table 9.

Table 9. SOFT POWER UP REGISTER UPLOAD

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NROT)

1

2

10

32

0x0000

0x7007

0x6017

0x0003

0x4103

0x0001

0x0017

0x0007

Release soft reset state

Enable analog clock for P1

Enable analog clock for P3

Enable column multiplexer

Configure image core

Enable AFE

3

4

5

6

7

8

40

42

48

64

Enable biasing block

Enable charge pump

Enable LVDS transmitters

72

112

P2−SN/SE 10−bit mode (ZROT)

1

2

3

4

5

6

7

10

32

40

42

48

64

72

0x0000

0x700F

0x0003

0x4103

0x0001

0x0017

Release soft reset state

Enable analog clock

Enable column multiplexer

Configure image core

Enable AFE

Enable biasing block

Enable charge pump

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22

NOIP1SN1300A

Enable Sequencer

During the ‘Enable Sequencer’ action, the frame grabbing

sequencer is enabled. The sensor starts grabbing images in

the configured operation mode. Refer to Sensor States on

page 17.

The ‘Enable Sequencer’ action consists of a set of register

uploads. The required uploads are listed in Table 10.

Table 10. ENABLE SEQUENCER REGISTER UPLOAD

Upload #

Address

Data

Description

1

192

0x080D

0x0801

Enable Sequencer for P1 in ZROT

Enable Sequencer for P3 in NROT

User Actions: Functional Modes to Power Down Sequences

Disable Sequencer

During the ‘Disable Sequencer’ action, the frame

grabbing sequencer is stopped. The sensor stops grabbing

images and returns to the idle mode.

The ‘Disable Sequencer’ action consists of a set of register

uploads. as listed in Table 11.

Table 11. DISABLE SEQUENCER REGISTER UPLOAD

Upload #

Address

Data

Description

1

192

0x080C

0x0800

Disable sequencer for P1 in ZROT

Disable sequencer for P3 in NROT

Soft Power Down

During the soft power down action, the internal blocks are

disabled and the sensor is put in standby state to reduce the

current dissipation. This action exists of a set of SPI uploads.

The soft power down uploads are listed in Table 12.

Table 12. SOFT POWER DOWN REGISTER UPLOAD

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NROT)

1

2

10

32

0x0999

0x7006

0x6016

0x0000

0x4100

0x0000

0x0010

0x0000

Soft reset

Disable analog clock for P1

Disable analog clock for P3

Disable column multiplexer

Image core config

3

4

5

6

7

8

40

42

48

Disable AFE

64

Disable biasing block

Disable charge pump

Disable LVDS transmitters

72

112

P2−SN/SE 10−bit mode (ZROT)

1

2

3

4

5

6

7

10

32

40

42

48

64

72

0x0999

0x700E

0x0000

0x4100

0x0000

0x0010

Soft reset

Disable analog clock

Disable column multiplexer

Image core config

Disable AFE

Disable biasing block

Disable charge pump

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23

NOIP1SN1300A

Disable Clock Management − Part 2

The ‘Disable Clock Management’ action stops the

internal clocking to further decrease the power dissipation.

This action can be implemented with the SPI uploads as

shown in Table 13.

Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL

1

2

0x0000

0x7004

0x6014

0x0000

Soft reset clock generator

Disable logic clock for P1

Disable logic clock for P3

Disable logic blocks

9

32

3

34

P2−SN/SE 10−bit mode

1

2

3

0x0000

0x700C

0x0000

Soft reset clock generator

Disable logic clock

9

32

34

Disable logic blocks

Disable Clock Management − Part 1

The ‘Disable Clock Management’ action stops the

internal clocking to further decrease the power dissipation.

This action can be implemented with the SPI uploads as

shown in Table 14.

Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1

Upload #

Address

Data

Description

P1−SN/SE/FN, P3−SN/SE/FN 10−bit mode with PLL

1

2

8

0x0099

0x0000

Soft reset PLL

Disable PLL

16

Power Down Sequence

Figure 19 illustrates the timing diagram of the preferred

power down sequence. It is important that the sensor is in

reset before the clock input stops running. Otherwise, the

internal PLL becomes unstable and the sensor gets into an

unknown state. This can cause high peak currents.

clock input

reset_n

vdd_18

The same applies for the ramp down of the power

supplies. The preferred order to ramp down the supplies is

first vdd_pix, second vdd_33, and finally vdd_18. Any other

sequence can cause high peak currents.

vdd_33

vdd_pix

NOTE: The ‘clock input’ can be the CMOS PLL clock

input (clk_pll), or the LVDS clock input

> 10us > 10us > 10us > 10us

(lvds_clock_inn/p) in case the PLL is bypassed.

Figure 19. Power Down Sequence

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NOIP1SN1300A

Sensor Reconfiguration

Sensor Configuration

During the standby, idle, or running state several sensor

parameters can be reconfigured.

• Frame Rate and Exposure Time: Frame rate and

exposure time changes can occur during standby, idle,

and running states by modifying registers 199 to 203.

Refer to page 30−32 for more information.

This device contains multiple configuration registers.

Some of these registers can only be configured while the

sensor is not acquiring images (while register 192[0] = 0),

while others can be configured while the sensor is acquiring

images. For the latter category of registers, it is possible to

distinguish the register set that can cause corrupted images

(limited number of images containing visible artifacts) from

the set of registers that are not causing corrupted images.

These three categories are described here.

• Signal Path Gain: Signal path gain changes can occur

during standby, idle, and running states by modifying

registers 204/205. Refer to page 37 for more

information.

Static Readout Parameters

• Windowing: Changes with respect to windowing can

occur during standby, idle, and running states. Refer to

Multiple Window Readout on page 32 for more

information.

Some registers are only modified when the sensor is not

acquiring images. Reconfiguration of these registers while

images are acquired can cause corrupted frames or even

interrupt the image acquisition. Therefore, it is

recommended to modify these static configurations while

the sequencer is disabled (register 192[0] = 0). The registers

shown in Table 15 should not be reconfigured during image

acquisition. A specific configuration sequence applies for

these registers. Refer to the operation flow and startup

description.

• Subsampling: Changes of the subsampling mode can

occur during standby, idle, and running states by

modifying register 192. Refer to Subsampling on

page 33 for more information.

• Shutter Mode: The shutter mode can only be changed

during standby or idle mode by modifying register 192.

Reconfiguring the shutter mode during running state is

not supported.

Table 15. STATIC READOUT PARAMETERS

Group

Clock generator

Addresses

32

Description

Configure according to recommendation

Image core

40

Configure according to recommendation

AFE

48

Bias

64–71

112

LVDS

Sequencer mode selection

192 [6:1]

Operation modes are: • triggered_mode

• slave_mode

All reserved registers

Keep reserved registers to their default state, unless otherwise described in the

recommendation

Dynamic Configuration Potentially Causing Image

Artifacts

The category of registers as shown in Table 16 consists of

configurations that do not interrupt the image acquisition

process, but may lead to one or more corrupted images

during and after the reconfiguration. A corrupted image is an

image containing visible artifacts. A typical example of a

corrupted image is an image which is not uniformly

exposed.

The effect is transient in nature and the new configuration

is applied after the transient effect.

Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS

Group

Addresses

Description

Black level configuration

128–129

197[12:8]

Reconfiguration of these registers may have an impact on the black−level

calibration algorithm. The effect is a transient number of images with incorrect black level com-

pensation.

Sync codes

129[13]

Incorrect sync codes may be generated during the frame in which these registers are modified.

116–126

Datablock test configurations

144, 146–150

Modification of these registers may generate incorrect test patterns during

a transient frame.

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25

NOIP1SN1300A

Dynamic Readout Parameters

shown in Table 17. Some reconfiguration may lead to one

frame being blanked. This happens when the modification

requires more than one frame to settle. The image is blanked

out and training patterns are transmitted on the data and sync

channels.

It is possible to reconfigure the sensor while it is acquiring

images. Frame related parameters are internally

resynchronized to frame boundaries, such that the modified

parameter does not affect a frame that has already started.

However, there can be restrictions to some registers as

Table 17. DYNAMIC READOUT PARAMETERS

Group

Addresses

Description

Subsampling/binning

192[7]

192[8]

Subsampling or binning is synchronized to a new frame start.

ROI configuration

195

A ROI switch is only detected when a new window is selected as the active window

(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does not

lead to a frame blank and can cause a corrupted image.

256–303

Exposure

reconfiguration

199−203

204

Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unless

reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).

Gain reconfiguration

Gains are synchronized at the start of a new frame. Optionally, one frame latency can be incorporated

to align the gain updates to the exposure updates

(refer to register 204[13] − gain_lat_comp).

Freezing Active Configurations

them for the coming frames. The freezing of the active set

Though the readout parameters are synchronized to frame

boundaries, an update of multiple registers can still lead to

a transient effect in the subsequent images, as some

configurations require multiple register uploads. For

example, to reconfigure the exposure time in master global

mode, both the fr_length and exposure registers need to be

updated. Internally, the sensor synchronizes these

configurations to frame boundaries, but it is still possible

that the reconfiguration of multiple registers spans over two

or even more frames. To avoid inconsistent combinations,

freeze the active settings while altering the SPI registers by

disabling synchronization for the corresponding

functionality before reconfiguration. When all registers are

uploaded, re−enable the synchronization. The sensor’s

sequencer then updates its active set of registers and uses

of registers can be programmed in the sync_configuration

registers, which can be found at the SPI address 206.

Figure 20 shows a reconfiguration that does not use the

sync_configuration option. As depicted, new SPI

configurations are synchronized to frame boundaries.

Figure 21 shows the usage of the sync_configuration

settings. Before uploading

a set of registers, the

corresponding sync_configuration is de−asserted. After the

upload is completed, the sync_configuration is asserted

again and the sensor resynchronizes its set of registers to the

coming frame boundaries. As seen in the figure, this ensures

that the uploads performed at the end of frame N+2 and the

start of frame N+3 become active in the same frame (frame

N+4).

Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3

Frame N+4

Time Line

SPI Registers

Active Registers

Figure 20. Frame Synchronization of Configurations (no freezing)

Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3ꢁꢁꢂꢀFrame N+4

Time Line

sync_configuration

SPI Registers

This configuration is not taken into

account as sync_register is inactive.

Active Registers

Figure 21. reconfiguration Using Sync_configuration

NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen

for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being

frozen.

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26

NOIP1SN1300A

Table 18. ALTERNATE SYNC CONFIGURATIONS

Group

Affected Registers

Description

sync_black_lines

black_lines

Update of black line configuration is not synchronized at start of frame when ‘0’.

The sensor continues with its previous configurations.

sync_exposure

mult_timer

fr_length

exposure

Update of exposure configurations is not synchronized at start of frame when ‘0’.

The sensor continues with its previous configurations.

sync_gain

sync_roi

mux_gainsw

afe_gain

Update of gain configurations is not synchronized at start of frame when ‘0’.

The sensor continues with its previous configurations.

roi_active0[7:0]

subsampling

binning

Update of active ROI configurations is not synchronized at start of frame when ‘0’.

The sensor continues with its previous configurations.

Note: The window configurations themselves are not frozen. reconfiguration of

active windows is not gated by this setting.

Window Configuration

Black Calibration

The sensor automatically calibrates the black level for

Global Shutter Mode

each frame. Therefore, the device generates a configurable

number of electrical black lines at the start of each frame.

The desired black level in the resulting output interface can

be configured and is not necessarily targeted to ‘0’.

Configuring the target to a higher level yields some

information on the left side of the black level distribution,

while the other end of the distribution tail is clipped to ‘0’

when setting the black level target to ‘0’.

The black level is calibrated for the 8 columns contained

in one kernel. This implies 8 black level offsets are generated

and applied to the corresponding columns. Configurable

parameters for the black−level algorithm are listed in

Table 19.

Up to 8 windows can be defined in global shutter mode

(pipelined or triggered). The windows are defined by

registers 256 to 303. Each window can be activated or

deactivated separately using register 195. It is possible to

reconfigure the inactive windows while the sensor is

acquiring images.

Switching between predefined windows is achieved by

activation of the respective windows. This way a minimum

number of registers need to be uploaded when it is necessary

to switch between two or more sets of windows. As an

example of this, scanning the scene at higher frame rates

using multiple windows and switching to full frame capture

when the object is tracked. Switching between the two

modes only requires an upload of one register.

Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM

Address

Black Line Generation

197[7:0]

Register Name

Description

black_lines

This register configures the number of black lines that are generated at the start of a frame. At least one

black line must be generated. The maximum number is 255.

Note: When the automatic black−level calibration algorithm is enabled, make sure that this register is

configured properly to produce sufficient black pixels for the black−level filtering.

The number of black pixels generated per line is dependent on the operation mode and window configu-

rations:

Each black line contains 162 kernels.

197[12:8]

gate_first_line

A number of black lines are blanked out when a value different from 0 is configured. These blanked out

lines are not used for black calibration. It is recommended to enable this functionality, because the first

line can have a different behavior caused by boundary effects. When enabling, the number of black

lines must be set to at least two in order to have valid black samples for the calibration algorithm.

Black Value Filtering

129[0]

auto_blackcal_enable

Internal black−level calibration functionality is enabled when set to ‘1’. Required black level offset com-

pensation is calculated on the black samples and applied to all image pixels.

When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible to apply an

offset compensation to the image pixels, which is defined by the registers 129[10:1].

Note: Black sample pixels are not compensated; the raw data is sent out to provide

external statistics and, optionally, calibrations.

129[9:1]

129[10]

blackcal_offset

Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_en-

able is set to ‘0’. The sign of the offset is determined by register 129[10] (blackcal_offset_dec).

Note: All channels use the same offset compensation when automatic black calibration is disabled.

blackcal_offset_dec

Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set to ‘1’, the

black calibration offset is subtracted from each pixel.

This register is not used when auto_blackcal_enable is set to ‘1’.

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27

NOIP1SN1300A

Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM

Address

Black Line Generation

128[10:8]

Register Name

Description

black_samples

The black samples are low−pass filtered before being used for black level calculation. The more sam-

ples are taken into account, the more accurate the calibration, but more samples require more black

lines, which in turn affects the frame rate.

The effective number of samples taken into account for filtering is 2^ black_samples.

Note: An error is reported by the device if more samples than available are requested (refer to register

136).

Black Level Filtering Monitoring

136 blackcal_error0

An error is reported by the device if there are requests for more samples than are available (each bit

corresponding to one data path). The black level is not compensated correctly if one of the channels

indicates an error. There are three possible methods to overcome this situation and to perform a correct

offset compensation:

• Increase the number of black lines such that enough samples are generated at the cost of increas-

ing frame time (refer to register 197).

• Relax the black calibration filtering at the cost of less accurate black level determination (refer to

register 128).

• Disable automatic black level calibration and provide the offset via SPI register upload. Note that

the black level can drift in function of the temperature. It is thus recommended to perform the offset

calibration periodically to avoid this drift.

NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.

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28

NOIP1SN1300A

Serial Peripheral Interface

The sck clock is passed through to the sensor as

indicated in Figure 22. The sensor samples this

data on a rising edge of the sck clock (mosi needs

to be driven by the system on the falling edge of

the sck clock).

The sensor configuration registers are accessed through

an SPI. The SPI consists of four wires:

• sck: Serial Clock

• ss_n: Active Low Slave Select

• mosi: Master Out, Slave In, or Serial Data In

5. The tenth bit sent by the master indicates the type

of transfer: high for a write command, low for a

read command.

• miso: Master In, Slave Out, or Serial Data Out

The SPI is synchronous to the clock provided by the

master (sck) and asynchronous to the sensor’s system clock.

When the master wants to write or read a sensor’s register,

it selects the chip by pulling down the Slave Select line

(ss_n). When selected, data is sent serially and synchronous

to the SPI clock (sck).

Figure 22 shows the communication protocol for read and

write accesses of the SPI registers. The PYTHON 300,

PYTHON 500, and PYTHON 1300 image sensors use 9−bit

addresses and 16−bit data words.

Data driven by the system is colored blue in Figure 16,

while data driven by the sensor is colored yellow. The data

in grey indicates high−Z periods on the miso interface. Red

markers indicate sampling points for the sensor (mosi

sampling); green markers indicate sampling points for the

system (miso sampling during read operations).

The access sequence is:

6. Data transmission:

- For write commands, the master continues

sending the 16−bit data, most significant bit first.

- For read commands, the sensor returns the

requested address on the miso pin, most significant

bit first. The miso pin must be sampled by the

system on the falling edge of sck (assuming

nominal system clock frequency and maximum

10 MHz SPI frequency).

7. When data transmission is complete, the system

deselects the sensor one clock period after the last

bit transmission by pulling ss_n high.

Note that the maximum frequency for the SPI interface

scales with the input clock frequency, bit depth and LVDS

output multiplexing as described in Table 5.

Consecutive SPI commands can be issued by leaving at

least two SPI clock periods between two register uploads.

Deselect the chip between the SPI uploads by pulling the

ss_n pin high.

3. Select the sensor for read or write by pulling down

the ss_n line.

4. One SPI clock cycle after selecting the sensor, the

9−bit data is transferred, most significant bit first.

SPI − WRITE

ss_n

sck

t_sckss

t_sssck

tsck

ts_mos i

th_mosi

A8

A7

..

A1

A0

`1'

D

5

D14

..

D1

D0

mosi

miso

SPI − READ

ss_n

sck

t_sckss

t_sssck

tsck

ts_mosi

th_mosi

A8

A7

..

A1

A0

`0'

mosi

miso

ts_miso

th_miso

D

5

D14

..

D1

D0

Figure 22. SPI Read and Write Timing Diagram

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29

NOIP1SN1300A

Table 20. SPI TIMING REQUIREMENTS

Group

Addresses

Description

Units

ns

(*)

tsck

sck clock period

100

tsssck

tsckss

ts_mosi

th_mosi

ts_miso

th_miso

tspi

ss_n low to sck rising edge

sck falling edge to ss_n high

Required setup time for mosi

Required hold time for mosi

Setup time for miso

tsck

ns

20

ns

20

ns

tsck/2−10

tsck/2−20

2 x tsck

ns

Hold time for miso

ns

Minimal time between two consecutive SPI accesses (not shown in figure)

ns

*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).

tsck is defined as 1/f . See text for more information on SPI clock frequency restrictions.

SPI

IMAGE SENSOR TIMING AND READOUT

The following sections describe the configurations for

single slope reset mechanism. Dual and triple slope handling

during global shutter operation is similar to the single slope

operation. Extra integration time registers are available.

reset period, the global photodiode reset condition is

abandoned. This indicates the start of the integration or

exposure time. The length of the exposure time is defined by

the registers exposure and mult_timer.

NOTE: The start of the exposure time is synchronized to

the start of a new line (during ROT) if the

exposure period starts during a frame readout.

As a consequence, the effective time during

which the image core is in a reset state is

extended to the start of a new line.

• Make sure that the sum of the reset time and exposure

time exceeds the time required to readout all lines. If

this is not the case, the exposure time is extended until

all (active) lines are read out.

Global Shutter Mode

Pipelined Global Shutter (Master)

The integration time is controlled by the registers

fr_length[15:0] and exposure[15:0]. The mult_timer

configuration defines the granularity of the registers

reset_length and exposure. It is read as number of system

clock cycles (14.706 ns nominal at 68 MHz) for the

P1−SN/SE/FN, P3−SN/SE/FN version and 18 MHz cycles

(55.556 ns nominal) for the P2−SN/SE version.

The exposure control for (Pipelined) Global Master mode

is depicted in Figure 23.

• Alternatively, it is possible to specify the frame time

and exposure time. The sensor automatically calculates

the required reset time. This mode is enabled by the

fr_mode register. The frame time is specified in the

register fr_length.

The pixel values are transferred to the storage node during

FOT, after which all photo diodes are reset. The reset state

remains active for a certain time, defined by the reset_length

and mult_timer registers, as shown in the figure. Note that

meanwhile the image array is read out line by line. After this

Frame N

Frame N+1

Exposure State

Readout

FOT

Reset

Integrating

FOT

Reset

Integrating

FOT

Image Array Global Reset

reset_length

x

mult_timer

exposure

x

mult_timer

= ROT

= Readout

= Readout Dummy Line (blanked)

Figure 23. Integration Control for (Pipelined) Global Shutter Mode (Master)

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30

NOIP1SN1300A

Triggered Global Shutter (Master)

exposure and mult_timer, as in the master pipelined global

mode. The fr_length configuration is not used. This

operation is graphically shown in Figure 24.

In master triggered global mode, the start of integration

time is controlled by a rising edge on the trigger0 pin. The

exposure or integration time is defined by the registers

Frame N

Frame N+1

FOT

Reset

Integrating

FOT

Reset

Integrating

FOT

Exposure State

trigger0

(No effect on falling edge)

Readout

Image Array Global Reset

exposure x mult_timer

= ROT

= Readout

= Readout Dummy Line (blanked)

Figure 24. Exposure Time Control in Triggered Shutter Mode (Master)

Notes:

the pixel storage node and readout of the image array. In

other words, the high time of the trigger pin indicates the

integration time, the period of the trigger pin indicates the

frame time.

The use of the trigger during slave mode is shown in

Figure 25.

• The falling edge on the trigger pin does not have any

impact. Note however the trigger must be asserted for

at least 100 ns.

• The start of the exposure time is synchronized to the

start of a new line (during ROT) if the exposure period

starts during a frame readout. As a consequence, the

effective time during which the image core is in a reset

state is extended to the start of a new line.

Notes:

• The registers exposure, fr_length, and mult_timer are

not used in this mode.

• If the exposure timer expires before the end of readout,

the exposure time is extended until the end of the last

active line.

• The trigger pin needs to be kept low during the FOT.

The monitor pins can be used as a feedback to the

FPGA/controller (eg. use monitor0, indicating the very

first line when monitor_select = 0x5 − a new trigger can

be initiated after a rising edge on monitor0).

• The start of exposure time is synchronized to the start

of a new line (during ROT) if the exposure period starts

during a frame readout. As a consequence, the effective

time during which the image core is in a reset state is

extended to the start of a new line.

• If the trigger is de−asserted before the end of readout,

the exposure time is extended until the end of the last

active line.

Triggered Global Shutter (Slave)

• The trigger pin needs to be kept low during the FOT.

The monitor pins can be used as a feedback to the

FPGA/controller (eg. use monitor0, indicating the very

first line when monitor_select = 0x5 − a new trigger can

be initiated after a rising edge on monitor0).

Exposure or integration time is fully controlled by means

of the trigger pin in slave mode. The registers fr_length,

exposure and mult_timer are ignored by the sensor.

A rising edge on the trigger pin indicates the start of the

exposure time, while a falling edge initiates the transfer to

Frame N

Frame N+1

Exposure State

trigger0

FOT

Reset

Integrating

FOT

Reset

Integrating

FOT

Readout

Image Array Global Reset

= ROT

= Readout

= Readout Dummy Line (blanked)

Figure 25. Exposure Time Control in Global−Slave Mode

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31

NOIP1SN1300A

ADDITIONAL FEATURES

Multiple Window Readout

y1_end

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors support multiple window readout, which

means that only the user−selected Regions Of Interest (ROI)

are read out. This allows limiting data output for every

frame, which in turn allows increasing the frame rate. In

global shutter mode, up to eight ROIs can be configured.

ROI 1

y0_end

y1_start

ROI 0

Window Configuration

Figure 26 shows the four parameters defining a region of

interest (ROI).

y0_start

y-end

x0_start

x0_end

x1_start

x1_end

ROI 0

Figure 27. Overlapping Multiple Window

Configuration

The sequencer analyses each line that need to be read out

for multiple windows.

y-start

Restrictions

The following restrictions for each line are assumed for

the user configuration:

• Windows are ordered from left to right, based on their

x-startꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢂx-end

x−start address:

Figure 26. Region of Interest Configuration

x_start_roi(i) vx_start_roi(j) AND

x_end_roi(i) vx_end_roi(j)

Where j > i

• x−start[7:0]

x−start defines the x−starting point of the desired window.

The sensor reads out 8 pixels in one single clock cycle. As

a consequence, the granularity for configuring the x−start

position is also 8 pixels for no sub sampling. The value

configured in the x−start register is multiplied by 8 to find

the corresponding column in the pixel array.

• x−end[7:0]

Processing Multiple Windows

The sequencer control block houses two sets of counters

to construct the image frame. As previously described, the

y−counter indicates the line that needs to be read out and is

incremented at the end of each line. For the start of the frame,

it is initialized to the y−start address of the first window and

it runs until the y−end address of the last window to be read

out. The last window is configured by the configuration

registers and it is not necessarily window #7.

The x−counter starts counting from the x−start address of

the window with the lowest ID which is active on the

addressed line. Only windows for which the current

y−address is enclosed are taken into account for scanning.

Other windows are skipped.

This register defines the window end point on the x−axis.

Similar to x−start, the granularity for this configuration is

one kernel. x−end needs to be larger than x−start.

• y−start[9:0]

The starting line of the readout window. The granularity

of this setting is one line, except with color sensors where it

needs to be an even number.

• y−end[9:0]

The end line of the readout window. y−end must be

configured larger than y−start. This setting has the same

granularity as the y−start configuration.

Up to eight windows can be defined, possibly (partially)

overlapping, as illustrated in Figure 27.

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32

NOIP1SN1300A

Figure 28 illustrates

a

practical example of

a

• The read pointer is not necessarily incremented by one,

but depending on the configuration, it can jump in

y−direction. In Figure 28, this is the case when reaching

the end of ROI0 where the read pointer jumps to the

y−start position of ROI1

configuration with five windows. The current position of the

read pointer (ys) is indicated by a red line crossing the image

array. For this position of the read pointer, three windows

need to be read out. The initial start position for the x−kernel

pointer is the x−start configuration of ROI1. Kernels are

scanned up to the ROI3 x−end position. From there, the

x−pointer jumps to the next window, which is ROI4 in this

illustration. When reaching ROI4’s x−end position, the read

pointer is incremented to the next line and xs is reinitialized

to the starting position of ROI1.

• The x−pointer starting position is equal to the x−start

configuration of the first active window on the current

line addressed. This window is not necessarily window

#0.

• The x−pointer is not necessarily incremented by one

each cycle. At the end of a window it can jump to the

start of the next window.

Notes:

• The starting point for the readout pointer at the start of

a frame is the y−start position of the first active

window.

• Each window can be activated separately. There is no

restriction on which window and how many of the 8

windows are active.

ROI 2

ROI 4

ROI 3

ys

ROI 1

ROI 0

Figure 28. Scanning the Image Array with Five Windows

Subsampling

Color Sensors

Subsampling is used to reduce the image resolution. This

allows increasing the frame rate. Two subsampling modes

are supported: for monochrome and NIR enhanced sensors

(P1−SN/FN, P2−SN and P3−SN/FN) and color sensors

(P1−SE / P2−SE / P3−SE).

For color sensors, the read−2−skip−2 subsampling

scheme is used. Subsampling occurs both in x− and y−

direction. Figure 29 shows which pixels are read and which

ones are skipped.

Monochrome and NIR Sensors

These sensors utilize the read−1−skip−1 subsampling

scheme. Subsampling occurs both in x− and y− direction.

Figure 29. Subsampling Scheme for Monochrome and Color Sensors

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33

NOIP1SN1300A

Binning

Multiple Slope Integration

Pixel binning is a technique in which different pixels

‘Multiple Slope Integration’ is a method to increase the

dynamic range of the sensor. The PYTHON 300,

PYTHON 500, and PYTHON 1300 support up to three

slopes.

Figure 30 shows the sensor response to light when the

sensor is used with one slope, two slopes, and three slopes.

The X−axis represents the light power; the Y−axis shows the

sensor output signal. The kneepoint of the multiple slope

curves are adjustable in both position and voltage level.

It is clear that when using only one slope (red curve), the

sensor has the same responsivity over the entire range, until

the output saturates at the point indicated with ‘single slope

saturation point’.

belonging to a rectangular bin are averaged in the analog

domain. Two−by−two pixel binning is available with the

monochrome and NIR enhanced image sensors (P1−SN/FN,

P2−SN, P3−SN/FN). This implies that two adjacent pixels

are averaged both in column and row. Binning is

configurable using a register setting. Pixel binning is not

supported on PYTHON color option (P1−SE / P2−SE /

P3−SE) and in Zero ROT mode.

NOTES:

1. Register 194[13:12] needs to be configured to 0x0

for 2x2 pixel binning and to 0x1 for 2x1 binning.

Binning occurs only in x direction.

To increase the dynamic range of the sensor, a second

slope is applied in the dual slope mode (green curve). The

sensor has the same responsivity in the black as for a single

slope, but from ‘knee point 1’ on, the sensor is less

responsive to incoming light. The result is that the saturation

point is at a higher light power level.

To further increase the dynamic range, a third slope can be

applied, resulting in a second knee point.

The multiple slope function is only available in global

shutter modes. Refer to section Global Shutter Mode on

page 30 for general notes applicable to the global shutter

operation and more particular to the use of the trigger0 pin.

2. Binning in y-direction cannot be used in

combination with pipelined integration and

readout. The integration time and readout time

should be separated in time (do not coincide).

Reverse Readout in Y−direction

Reverse readout in y−direction can be done by toggling

reverse_y (reg 194[8]). The reference for y_start and y_end

pointers is reversed.

output

1023

slope 3

`kneepoint 2'

slope 1ꢁꢁꢁꢁꢂslope 2

`kneepoint 1'

light

0

single slope

saturation point

triple slope

saturation point

dual slope

saturation point

Figure 30. Multiple Slope Operation

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NOIP1SN1300A

Kneepoint Configuration (Multiple Slope Reset Levels)

dual_slope_enableand triple_slope_enable and their values

are defined by the registers exposure_ds and exposure_ts.

The kneepoint reset levels are configured by means of

DAC configurations in the image core. The dual slope

kneepoint is configured with the dac_ds configuration,

while the triple slope kneepoint is configured with the

dac_ts register setting. Both are located on address 41.

NOTE: Dual and triple slope sequences must start after

readout of the previous frame is fully completed.

Figure 31 shows the frame timing for pipelined master

mode with dual and triple slope integration and

fr_mode = ‘0’ (fr_length representing the reset length).

In triggered master mode, the start of integration is

initiated by a rising edge on trigger0, while the falling edge

does not have any relevance. Exposure duration and

dual/triple slope points are defined by the registers.

Multiple Slope Integration in “Master Mode” (Pipelined

or Triggered)

In master mode, the time stamps for the double and triple

slope resets are configured in a similar way as the exposure

time. They are enabled through the registers

Figure 31. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)

Slave Mode

In slave mode, the register settings for integration control are ignored. The user has full control through the trigger0, trigger1

and trigger2 pins. A falling edge on trigger1 initiates the dual slope reset while a falling edge on trigger2 initiates the triple

slope reset sequence. Rising edges on trigger1 and trigger2 do not have any impact.

NOTE: Dual and triple slope sequences must start after readout of the previous frame is fully completed.

Figure 32. Multiple Slope Operation in Slave Mode

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NOIP1SN1300A

Black Reference

Signal Path Gain

The sensor reads out one or more black lines at the start of

every new frame. The number of black lines to be generated

is programmable and is minimal equal to 1. The length of the

black lines depends on the operation mode. The sensor

always reads out the entire line (160 kernels), independent

of window configurations.

The black references are used to perform black calibration

and offset compensation in the data channels. The raw black

pixel data is transmitted over the usual output interface,

while the regular image data is compensated (can be

bypassed).

On the output interface, black lines can be seen as a

separate window, however without Frame Start and Ends

(only Line Start/End). The Sync code following the Line

Start and Line End indications (“window ID”) contains the

active window number, which is 0. Black reference data is

classified by a BL code.

Analog Gain Stages

Referring to Table 21, three gain settings are available in

the analog data path to apply gain to the analog signal before

it is digitized. The gain amplifier can apply a gain of

approximately 1x to 4x to the analog signal.

The moment a gain reconfiguration is applied and

becomes valid can be controlled by the gain_lat_comp

configuration.

With ‘gain_lat_comp’ set to ‘0’, the new gain

configurations are applied from the very next frame.

With ‘gain_lat_comp’ set to ‘1’, the new gain settings are

postponed by one extra frame. This feature is useful when

exposure time and gain are reconfigured together, as an

exposure time update always has one frame latency.

Table 21. SIGNAL PATH GAIN STAGES

Gain Stage 1 (204[4:0])

Gain Stage 2 (204[12:5])

Normal

Overall Gain

ROT

Normal ROT

Zero ROT

Normal ROT

Zero ROT

Address

204[12:0]

Gain Setting

0x01E3

1

NA

1

NA

1

NA

1

0x01E1

1.9

3.5

14

1.9

3.5

14

0x01E4

1.8

8

1

1.8

8

0x01E8

1

NOTE: The sensor performance specifications are tested at unity gain. Analog gain above 2x affects noise performance. All other gain

settings shown in this table are tested for sensor functionality.

Digital Gain Stage

The digital gain stage allows fine gain adjustments on the

digitized samples. The gain configuration is an absolute 5.7

unsigned number (5 digits before and 7 digits after the

decimal point).

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36

NOIP1SN1300A

Automatic Exposure Control

The exposure control mechanism has the shape of a

general feedback control system. Figure 33 shows the high

level block diagram of the exposure control loop.

AEC

Statistics

AEC

Filter

AEC

Enforcer

Requested Illumination Level

(Target)

Integration Time

Analog Gain (Coarse Steps)

Digital Gain (Fine Steps)

Image Capture

Figure 33. Automatic Exposure Control Loop

AEC Statistics Block

Three main blocks can be distinguished:

The statistics block calculates the average illumination of

the current image. Based on the difference between the

calculated illumination and the target illumination the

statistics block requests a relative gain change.

• The statistics block compares the average of the

current image’s samples to the configured target value

for the average illumination of all pixels

• The relative gain change request from the statistics

block is filtered through the AEC Filter block in the

time domain (low pass filter) before being integrated.

The output of the filter is the total requested gain in the

complete signal path.

Statistics Subsampling and Windowing

For average calculation, the statistics block will

sub−sample the current image or windows by taking every

fourth sample into account. Note that only the pixels read out

through the active windows are visible for the AEC. In the

case where multiple windows are active, the samples will be

selected from the total samples. Samples contained in a

region covered by multiple (overlapping) window will be

taking into account only once.

It is possible to define an AEC specific sub−window on

which the AEC will calculate it’s average. For instance, the

sensor can be configured to read out a larger frame, while the

illumination is measured on a smaller region of interest, e.g.

center weighted as shown in Table 22.

• The enforcer block accepts the total requested gain and

distributes this gain over the integration time and gain

stages (both analog and digital)

The automatic exposure control loop is enabled by asserting

the aec_enable configuration in register 160.

NOTE: Dual and Triple slope integration is not

supported in conjunction with the AEC.

Table 22. AEC SAMPLE SELECTION

Register

Name

Description

192[10]

roi_aec_enable When 0x0, all active windows are selected for statistics calculation.

When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined

by roi_aec

253−255 roi_aec

These registers define a window from which the AEC samples will be selected when roi_aec_enable is

asserted. Configuration is similar to the regular region of interests.

The intersection of this window with the active windows define the selected pixels. It is important that this

window at least overlaps with one or more active windows.

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NOIP1SN1300A

AEC Filter Block

Target Illumination

The filter block low−pass filters the gain change requests

received from the statistics block.

The target illumination value is configured by means of

register desired_intensity as shown in Table 23.

The filter can be restarted by asserting the restart_filter

configuration of register 160.

Table 23. AEC TARGET ILLUMINATION

CONFIGURATION

AEC Enforcer Block

Register

Name

Description

The enforcer block calculates the four different gain

parameters, based on the required total gain, thereby

respecting a specific hierarchy in those configurations.

Some (digital) hysteresis is added so that the (analog) sensor

settings don’t need to change too often.

161[9:0] desired_in- Target intensity value, on 10−bit scale.

tensity

For 8−bit mode, target value is con-

figured on desired_intensity[9:2]

Color Sensor

Exposure Control Parameters

The weight of each color can be configured for color

sensors by means of scale factors. Note these scale factor are

only used to calculate the statistics in order to compensate

for (off−chip) white balancing and/or color matrices. The

pixel values itself are not modified.

The several gain parameters are described below, in the

order in which these are controlled by the AEC for large

adjustments. Small adjustments are regulated by digital gain

only.

The scale factors are configured as 3.7 unsigned numbers

(0x80 = unity). Refer to Table 24 for color scale factors. For

mono sensors, configure these factors to their default value.

• Exposure Time

The exposure is the time between the global image array

reset de−assertion and the pixel charge transfer. The

granularity of the integration time steps is configured by the

mult_timer register.

Table 24. COLOR SCALE FACTORS

NOTE: The exposure_time register is ignored when the

AEC is enabled. The register fr_length defines

the frame time and needs to be configured

accordingly.

Register

Name

Description

162[9:0] red_scale_factor

Red scale factor for AEC

statistics

163[9:0] green1_scale_fa

ctor

Green1 scale factor for AEC

statistics

• Analog Gain

The sensor has two analog gain stages, configurable

independently from each other. Typically the AEC shall only

regulate the first stage.

164[9:0] green2_scale_fa

ctor

Green2 scale factor for AEC

statistics

165[9:0] blue_scale_factor Blue scale factor for AEC

statistics

• Digital Gain

The last gain stage is a gain applied on the digitized

samples. The digital gain is represented by a 5.7 unsigned

number (i.e. 7 bits after the decimal point). While the analog

gain steps are coarse, the digital gain stage makes it possible

to achieve very fine adjustments.

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NOIP1SN1300A

AEC Control Range

AEC Update Frequency

The control range for each of the exposure parameters can

be pre−programmed in the sensor. Table 25 lists the relevant

registers.

As an integration time update has a latency of one frame,

the exposure control parameters are evaluated and updated

every other frame.

Note: The gain update latency must be postpone to match

the integration time latency. This is done by asserting the

gain_lat_comp register on address 204[13].

Table 25. MINIMUM AND MAXIMUM EXPOSURE

CONTROL PARAMETERS

Register

Name

Description

Exposure Control Status Registers

Configured integration and gain parameters are reported

to the user by means of status registers. The sensor provides

two levels of reporting: the status registers reported in the

AEC address space are updated once the parameters are

recalculated and requested to the internal sequencer. The

status registers residing in the sequencer’s address space on

the other hand are updated once these parameters are taking

effect on the image readout. Refer to Table 26 reflecting the

AEC and Sequencer Status registers.

168[15:0] min_exposure

Lower bound for the integration

time applied by the AEC

169[1:0]

169[3:2]

min_mux_gain

Lower bound for the first stage

analog amplifier.

This stage has three

configurations with the following

approximative gains:

0x0 = 1x

0x1 = 2x

0x2 = 4x

min_afe_gain

Lower bound for the second

stage analog amplifier.

This stage has one

configuration with the following

approximative gain:

Table 26. EXPOSURE CONTROL STATUS REGISTERS

Register

Name

Description

0x0 = 1.00x

AEC Status Registers

184[15:0] total_pixels

169[15:4] min_digital_gain Lower bound for the digital gain

stage. This configuration

Total number of pixels taken into

account for the AEC statistics.

specifies the effective gain in 5.7

unsigned format

186[9:0]

average

Calculated average illumination

level for the current frame.

170[15:0] max_exposure

Upper bound for the integration

time applied by the AEC

187[15:0] exposure

AEC calculated exposure.

Note: this parameter is updated at

the frame end.

171[1:0]

max_mux_gain

Upper bound for the first stage

analog amplifier.

This stage has three

configurations with the following

approximative gains:

0x0 = 1x

0x1 = 2x

0x2 = 4x

188[1:0]

188[3:2]

mux_gain

afe_gain

AEC calculated analog gain

(1 stage)

Note: this parameter is updated at

the frame end.

st

AEC calculated analog gain

st

(2 stage)

171[3:2]

max_afe_gain

Upper bound for the second

stage analog amplifier

Note: this parameter is updated at

the frame end.

This stage has one

configuration with the following

approximative gain:

0x0 = 1.00x

188[15:4] digital_gain

AEC calculated digital gain

(5.7 unsigned format)

Note: this parameter is updated at

the frame end.

171[15:4] max_digit-

al_gain

Upper bound for the digital gain

stage. This configuration

specifies the effective gain in 5.7

unsigned format

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NOIP1SN1300A

Table 26. EXPOSURE CONTROL STATUS REGISTERS

Register

Name

Description

Register

Name

Description

st

Sequencer Status Registers

242[15:0] mult_timer

247[12:5] afe_gain

2

stage analog gain for the current

frame.

mult_timer for current frame (global

shutter only).

Note: this parameter is updated

once it takes effect on the image.

Note: this parameter is updated

once it takes effect on the image.

248[11:0] db_gain

Digital gain configuration for the

current frame (5.7 unsigned

format).

Note: this parameter is updated

once it takes effect on the image.

243[15:0] reset_length Image array reset length for the

current frame (global shutter only).

Note: this parameter is updated

once it takes effect on the image.

248[12]

248[13]

dual_slope

triple_slope

Dual slope configuration for the

current frame

Note 1: this parameter is updated

once it takes effect on the image.

Note 2: This parameter is not

controlled by the AEC.

244[15:0] exposure

Exposure for the current frame.

Note: this parameter is updated

once it takes effect on the image.

245[15:0] exposure_ds Dual slope exposure for the current

frame. Note this parameter is not

controlled by the AEC.

Note: this parameter is updated

once it takes effect on the image.

Triple slope configuration for the

current frame.

Note 1: this parameter is updated

once it takes effect on the image.

Note 2: This parameter is not

controlled by the AEC.

246[15:0] exposure_ts Triple slope exposure for the

current frame. Note this parameter

is not controlled by the AEC.

Note: this parameter is updated

once it takes effect on the image.

st

247[4:0]

mux_gainsw

1

stage analog gain for the current

frame.

Note: this parameter is updated

once it takes effect on the image.

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NOIP1SN1300A

Mode Changes and Frame Blanking

summarized in the following table for the sensor’s image

related modes.

Dynamically reconfiguring the sensor may lead to

corrupted or non-uniformilly exposed frames. For some

reconfigurations, the sensor automatically blanks out the

image data during one frame. Frame blanking is

NOTE: Major mode switching (i.e. switching between

master, triggered or slave mode) must be

performed while the sequencer is disabled

(reg_seq_enable = 0x0).

Table 27. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING

Corrupted

Frame

Blanked Out

Frame

Configuration

Notes

Shutter Mode and Operation

triggered_mode

Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting

reg_seq_enable = 0x0.

slave_mode

Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting

reg_seq_enable = 0x0.

subsampling

Enabling: No

Configurable

Configurable with blank_subsampling_ss register.

Disabling: Yes

binning

No

Configurable

Configurable with blank_subsampling_ss register

Frame Timing

black_lines

Exposure Control

mult_timer

fr_length

No

Latency is 1 frame

exposure

Gain

mux_gainsw

afe_gain

No

Latency configurable by means of gain_lat_comp register

Latency configurable by means of gain_lat_comp register.

db_gain

Window/ROI

roi_active

See Note

No

Windows containing lines previously not read out may lead to corrupted

frames.

roi*_configuration*

Reconfiguring the windows by means of roi*_configuration* may lead to

corrupted frames when configured close to frame boundaries.

It is recommended to (re)configure an inactive window and switch the

roi_active register.

See Notes on roi_active.

Black Calibration

black_samples

No

If configured within range of configured black lines

auto_blackal_enable

See Note

Manual correction factors become instantly active when

auto_blackcal_enable is deasserted during operation.

blackcal_offset

CRC Calculation

crc_seed

Sync Channel

bl_0

See Note

No

Manual blackcal_offset updates are instantly active.

Impacts the transmitted CRC

No

Impacts the Sync channel information, not the Data channels.

img_0

crc_0

tr_0

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NOIP1SN1300A

Temperature Sensor

low respectively. The temperature sensor is reset or disabled

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors have an on−chip temperature sensor which

returns a digital code (Tsensor) of the silicon junction

temperature. The Tsensor output is a 8−bit digital count

between 0 and 255, proportional to the temperature of the

silicon substrate. This reading can be translated directly to

a temperature reading in °C by calibrating the 8−bit readout

at 0°C and 85°C to achieve an output accuracy of 2°C. The

Tsensor output can also be calibrated using a single

temperature point (example: room temperature or the

ambient temperature of the application), to achieve an

output accuracy of 5°C.

when the input reg_tempd_enable is set to a digital low state.

Calibration using one temperature point

The temperature sensor resolution is fixed for a given type

of package for the operating range of 0°C to +85°C and

hence devices can be calibrated at any ambient temperature

of the application, with the device configured in the mode of

operation.

Interpreting the actual temperature for the digital code

readout:

The formula used is

T = R (Nread − Ncalib) + Tcalib

J

Note that any process variation will result in an offset in

the bit count and that offset will remain within 5°C over the

temperature range of 0°C and 85°C. Tsensor output digital

code can be read out through the SPI interface.

T = junction die temperature

J

R = resolution in degrees/LSB (typical 0.75 deg/LSB)

Nread = Tsensor output (LSB count between 0 and 255)

Tcalib = Tsensor calibration temperature

Ncalib = Tsensor output reading at Tcalib

Output of the temperature sensor to the SPI:

tempd_reg_temp<7:0>: This is the 8−bit N count readout

proportional to temperature.

Monitor Pins

The internal sequencer has two monitor outputs (Pin 44

and Pin 45) that can be used to communicate the internal

states from the sequencer. A three−bit register configures the

assignment of the pins as shown in Table 28.

Input from the SPI:

The reg_tempd_enable is a global enable and this enables

or disables the temperature sensor when logic high or logic

Table 28. REGISTER SETTING FOR THE MONITOR SELECT PIN

monitor_select [2:0]

192 [13:11]

monitor pin

Description

0x0

monitor0

monitor1

‘0’

0x1

0x2

0x3

0x4

0x5

0x6

0x7

monitor0

monitor1

Integration Time

ROT Indication (‘1’ during ROT, ‘0’ outside)

monitor0

monitor1

Integration Time

Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)

monitor0

monitor1

Start of x−Readout Indication

Black Line Indication (‘1’ during black lines, ‘0’ outside)

monitor0

monitor1

Frame Start Indication

Start of ROT Indication

monitor0

monitor1

First Line Indication (‘1’ during first line, ‘0’ for all others)

Start of ROT Indication

monitor0

monitor1

ROT Indication (‘1’ during ROT, ‘0’ outside)

Start of X−Readout Indication

monitor0

monitor1

Start of X−readout Indication for Black Lines

Start of X−readout Indication for Image Lines

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42

NOIP1SN1300A

DATA OUTPUT FORMAT

Frame Format

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors are available in two LVDS output

configuration, P1 and P3.

The P1 configuration utilizes four LVDS output channels

together with an LVDS clock output and an LVDS

synchronization output channel.

The P3 configuration consists of two LVDS output

channels together with an LVDS clock output and an LVDS

synchronization output channel.

The PYTHON 1300 is also available in a CMOS output

configuration − P2, which includes a 10−bit parallel CMOS

output together with a CMOS clock output and ‘frame valid’

and ‘line valid’ CMOS output signals.

The frame format in 8−bit mode is identical to the 10−bit

mode with the exception that the Sync and data word depth

is reduced to eight bits.

The frame format in 10−bit mode is explained by example

of the readout of two (overlapping) windows as shown in

Figure 34(a).

The readout of a frame occurs on a line−by−line basis. The

read pointer goes from left to right, bottom to top.

Figure 34 indicates that, after the FOT is completed, the

sensor reads out a number of black lines for black calibration

purposes. After these black lines, the windows are

processed. First a number of lines which only includes

information of ‘ROI 0’ are sent out, starting at position

y0_start. When the line at position y1_start is reached, a

number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are

sent out, until the line position of y0_end is reached. From

there on, only data of ‘ROI 1’ appears on the data output

channels until line position y1_end is reached

P1−SN/SE/FN, P3−SN/SE/FN: LVDS Interface Version

LVDS Output Channels

The image data output occurs through four LVDS data

channels where a synchronization LVDS channel and an

LVDS output clock signal synchronizes the data. Referring

to Table 21, the four data channels on the P1 option are used

to output the image data only, while on the P3 option, two

data channel channels are utilized. The sync channel

transmits information about the data sent over these data

channels (includes codes indicating black pixels, normal

pixels, and CRC codes).

During read out of the image data over the data channels,

the sync channel sends out frame synchronization codes

which give information related to the image data that is sent

over the four data output channels.

Each line of a window starts with a Line Start (LS)

indication and ends with a Line End (LE) indication. The

line start of the first line is replaced by a Frame Start (FS);

the line end of the last line is replaced with a Frame End

indication (FE). Each such frame synchronization code is

followed by a window ID (range 0 to 7). For overlapping

windows, the line synchronization codes of the overlapping

windows with lower IDs are not sent out (as shown in the

illustration: no LE/FE is transmitted for the overlapping part

of window 0).

8−bit / 10−bit Mode

The sensor can be used in 8−bit or 10−bit mode.

In 10−bit mode, the words on data and sync channel have

a 10−bit length. The output data rate is 720 Mbps.

In 8−bit mode, the words on data and sync channel have

an 8−bit length, the output data rate is 576 Mbps.

Note that the 8−bit mode can only be used to limit the data

rate at the consequence of image data word depth. It is not

supported to operate the sensor in 8−bit mode at a higher

clock frequency to achieve higher frame rates.

The P1 option supports 10−bit/8−bit in ZROT/NROT

mode, while the P3 option supports 10−bit NROT mode

only.

NOTE: In Figure 34, only Frame Start and Frame End

Sync words are indicated in (b). CRC codes are

also omitted from the figure.

For additional information on the

synchronization codes, please refer to

Application Note AND5001.

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43

NOIP1SN1300A

y1_end

y0_end

y1_start

ROI 1

ROI 0

y0_start

x0_start

x0_end

x1_start

x1_end

(a)

Integration Time

Handling

Reset

N

Reset

N+1

FOT

Exposure Time N

Exposure Time N+1

Readout Frame N-1

Readout Frame N

Readout

Handling

B

L

ROI

1

B

L

ROI

1

FOT

ROI 0

FS0

FS1

FE1

FS0

FS1

FE1

(b)

Figure 34. P1−SN/SE/FN, P3−SN/SE/FN: Frame Sync Codes

Figure 35 shows the detail of a black line readout during global or full−frame readout.

Sequencer

FOT

ROT

black

ROT

line Ys+1

ROT

line Ye

line Ys

Internal State

data channels

sync channel

Training

TR

Training

TR

data channels

sync channel

LS

BL

BL LE

CRC

timeslot

0

timeslot

1

timeslot

157

timeslot

158

timeslot

159

CRC

timeslot

Figure 35. P1−SN/SE/FN, P3−SN/SE/FN: Time Line for Black Line Readout

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44

NOIP1SN1300A

Figure 36 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.

Sequencer

Internal State

FOT

ROT

black

ROT

line Ys+1

ROT

line Ye

line Ys

data channels

sync channel

Training

TR

data channels

sync channel

TR

FS

ID

IMG IMG

IMG

IMG IMG IMG LE

ID

CRC

timeslot

Xstart

timeslot

Xstart + 1

timeslot

Xend - 2

timeslot

Xend - 1

timeslot

Xend

CRC

timeslot

Figure 36. P1−SN/SE/FN, P3−SN/SE/FN: Time Line for Single Window Readout (at the start of a frame)

Figure 37 shows the detail of the readout of a number of lines for readout of two overlapping windows.

Sequencer

Internal State

FOT

ROT

black

ROT

line Ys

ROT

line Ys+1

ROT

line Ye

data channels

sync channel

Training

TR

Training

TR

data channels

sync channel

LS

IMG IMG

LS

IDN

IMG

IMG LE

IDN

CRC

IDM

IMG

timeslot

XstartM

timeslot

XstartN

timeslot

XendN

Figure 37. P1−SN/SE/FN, P3−SN/SE/FN: Time Line Showing the Readout of Two Overlapping Windows

Frame Synchronization for 10−bit Mode

Table 29 shows the structure of the frame synchronization

code. Note that the table shows the default data word

(configurable) for 10−bit mode. If more than one window is

active at the same time, the sync channel transmits the frame

synchronization codes of the window with highest index

only.

Table 29. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE

Sync Word Bit

Position

Register

Address

Default

Value

Description

9:7

6:0

N/A

0x5

0x6

Frame start indication

Frame end indication

Line start indication

Line end indication

N/A

0x1

N/A

0x2

117[6:0]

0x2A

These bits indicate that the received sync word is a frame synchronization code. The

value is programmable by a register setting

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45

NOIP1SN1300A

• Window Identification

• Data Classification Codes

Frame synchronization codes are always followed by a

3−bit window identification (bits 2:0). This is an integer

number, ranging from 0 to 7, indicating the active window.

If more than one window is active for the current cycle, the

highest window ID is transmitted.

For the remaining cycles, the sync channel indicates the

type of data sent through the data links: black pixel data

(BL), image data (IMG), or training pattern (TR). These

codes are programmable by a register setting. The default

values are listed in Table 30.

Table 30. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE

Sync Word Bit

Position

Register

Address

Default

Value

Description

9:0

118 [9:0]

119 [9:0]

125 [9:0]

126 [9:0]

0x015

0x035

0x059

0x3A6

Black pixel data (BL). This data is not part of the image. The black pixel data is used

internally to correct channel offsets.

Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the

image).

CRC value. The data on the data output channels is the CRC code of the finished image

data line.

Training pattern (TR). The sync channel sends out the training pattern which can be

programmed by a register setting.

Frame Synchronization in 8−bit Mode

and not sent out. Table 32 shows the structure of the frame

The frame synchronization words are configured using

the same registers as in 10−bit mode. The two least

significant bits of these configuration registers are ignored

synchronization code, together with the default value, as

specified in SPI registers. The same restriction for

overlapping windows applies in 8−bit mode.

Table 31. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE

Sync Word Bit

Position

Register

Address

Default

Value

Description

7:5

4:0

N/A

0x5

0x6

Frame start (FS) indication

Frame end (FE) indication

Line start (LS) indication

Line end (LE) indication

N/A

0x1

N/A

0x2

117 [6:2]

0x0A

These bits indicate that the received sync word is a frame synchronization code.

The value is programmable by a register setting.

• Window Identification

Similar to 10−bit operation mode, the frame

synchronization codes are followed by window

identification. The window ID is located in bits 4:2 (all other

bit positions are ‘0’). The same restriction for overlapping

windows applies in 8−bit mode.

• Data Classification Codes

BL, IMG, CRC, and TR codes are defined by the same

registers as in 10−bit mode. Bits 9:2 of the respective

configuration registers are used as classification code with

default values shown in Table 32.

a

Table 32. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE

Sync Word Bit

Position

Register

Address

Default

Value

Description

7:0

118 [9:2]

119 [9:2]

125 [9:2]

126 [9:2]

0x05

0x0D

0x16

0xE9

Black pixel data (BL). This data is not part of the image. The black pixel data is used

internally to correct channel offsets.

Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of

the image).

CRC value. The data on the data output channels is the CRC code of the finished image

data line.

Training Pattern (TR). The sync channel sends out the training pattern which can be

programmed by a register setting.

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46

NOIP1SN1300A

Training Patterns on Data Channels

In 10−bit mode, during idle periods, the data channels

transmit training patterns, indicated on the sync channel by

a TR code. These training patterns are configurable

independent of the training code on the sync channel as

shown in Table 33.

Table 33. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE

Sync Word Bit

Position

Register

Address

Default

Value

Description

[9:0]

116 [9:0]

0x3A6

Data channel training pattern. The data output channels send out the training pattern,

which can be programmed by a register setting. The default value of the training pattern

is 0x3A6, which is identical to the training pattern indication code on the sync channel.

In 8−bit mode, the training pattern for the data channels is

defined by the same register as in 10−bit mode, where the

lower two bits are omitted; see Table 34.

Table 34. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE

Data Word Bit

Position

Register

Address

Default

Value

Description

[7:0]

116 [9:2]

0xE9

Data Channel Training Pattern (Training pattern).

Cyclic Redundancy Code

LVDS Output Multiplexing

At the end of each line, a CRC code is calculated to allow

error detection at the receiving end. Each data channel

transmits a CRC code to protect the data words sent during

the previous cycles. Idle and training patterns are not

included in the calculation.

The PYTHON300, PYTHON500 and PYTHON1300

image sensors contain a function for down−multiplexing the

output channels. Using this function, one may for instance

use the device with 2 or 1 data channels instead of 4 data

channels.

The sync channel is not protected. A special character

(CRC indication) is transmitted whenever the data channels

send their respective CRC code.

Enabling the channel multiplexing is done through

register 32[5:4]. The default value of 0x0 disables all

channel multiplexing. Higher values sets a higher degree of

channel multiplexing. Note that the Sync identification

codes are repeated multiple times depending on the

multiplex factor. The channels that are used per degree of

multiplexing and the number of Sync Code repetitions are

shown in Table 35. The unused data channels are powered

down and will not send any data.

The polynomial in 10−bit operation mode is

10

9

6

3

2

x

+ x + x + x + x + x + 1. The CRC encoder is seeded

at the start of a new line and updated for every (valid) data

word received. The CRC seed is configurable using the

crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;

when ‘1’ it is seeded with all−‘1’.

8

6

3

2

In 8−bit mode, the polynomial is x + x + x + x + 1.

The CRC seed is configured by means of the crc_seed

register.

NOTE: The CRC is calculated for every line. This

implies that the CRC code can protect lines from

multiple windows.

Table 35. LVDS CHANNEL MULTIPLEXING

Number of Output

Channels

PYTHON 300 / PYTHON 500 /

PYTHON 1300 − LVDS Channels

Register 32[5:4]

Data

Register 211

Data

Sync Code

Repetitions

4 channels

2 channels

1 channel

Ch 0

Ch 1

Ch 2

Ch 3

0x0

0x1, 0x2

0x3

0x0E49

0x0E39

0x0E29

1

2

4

NOTE: The P3−SN/SE/FN sensor does not allow the 4 data lane operation. Functionality is restricted to 2 or 1 data lane.

The mux configuration shall be configured as such.

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47

NOIP1SN1300A

Data Order for P1−SN/SE/FN, P3−SN/SE/FN: LVDS

Interface Version

To read out the image data through the output channels,

the pixel array is organized in kernels. The kernel size is

eight pixels in x−direction by one pixel in y−direction. The

data order in 8−bit mode is identical to the 10−bit mode.

Figure 38 indicates how the kernels are organized. The first

kernel (kernel [0, 0]) is located in the bottom left corner. The

data order of this image data on the data output channels

depends on the subsampling mode.

kernel

(159,1023)

pixel array

ROI

kernel

(x_start,y_start)

kernel

(0,0)

0

1

2

3

5

6

7

Figure 38. Kernel Organization in Pixel Array

Figure 39 shows how a kernel is read out over the four

• P1−SN/SE/FN, P3−SN/SE/FN: Subsampling disabled

♦ 4 LVDS output channels (P1 only)

The image data is read out in kernels of eight pixels in

x−direction by one pixel in y−direction. One data channel

output delivers two pixel values of one kernel sequentially.

output channels. For even positioned kernels, the kernels are

read out ascending, while for odd positioned kernels the data

order is reversed (descending).

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel # (even kernel)

pixel # (odd kernel)

0

7

1

6

2

5

3

4

3

5

2

6

1

7

0

MSB

LSB

MSB

LSB

Note: The bit order is always MSB first

10−bit / 8−bit

Figure 39. P1−SN/SE/FN: 4 LVDS Data Output Order when Subsampling is Disabled

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48

NOIP1SN1300A

♦ 2 LVDS output channels

read out ascending but in pair of even and odd pixels, while

for odd positioned kernels the data order is reversed

(descending) but in pair of even and odd pixels.

Figure 40 shows how a kernel is read out over 2 output

channels. Each pair of adjacent channels is multiplexed into

one channel. For even positioned kernels, the kernels are

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel # (even kernel)

pixel # (odd kernel)

0

7

2

5

1

6

3

4

3

6

1

5

2

7

0

MSB

LSB

MSB

LSB

Note: The bit order is always MSB first

10−bit / 8−bit

Figure 40. P1−SN/SE/FN, P3−SN/SE/FN: 2 LVDS Data Output Order when Subsampling is Disabled

♦ 1 LVDS output channel

the kernels are read out ascending but in sets of 4 even and

4 odd pixels, while for odd positioned kernels the data order

is reversed (descending) but in sets of 4 odd and 4 even

pixels.

Figure 41 shows how a kernel is read out over 1 output

channel. Each bunch of four adjacent channels is

multiplexed into one channel. For even positioned kernels,

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel # (even kernel)

pixel # (odd kernel)

0

7

2

5

4

3

6

1

6

3

4

5

2

7

0

MSB

LSB MSB

LSB

Note: The bit order is always MSB first

10−bit / 8−bit

Figure 41. P1−SN/SE/FN, P3−SN/SE/FN: 1 LVDS Data Output Order when Subsampling is Disabled

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49

NOIP1SN1300A

are read out. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout.

• P1−SN/FN, P3−SN/FN: Subsampling on Monochrome

Sensor

During subsampling on a monochrome sensor, every

other pixel is read out and the lines are read in a

read-1-skip-1 manner. To read out the image data with

subsampling enabled on a monochrome sensor, two

neighboring kernels are combined to a single kernel of

16 pixels in the x−direction and one pixel in the y−direction.

Only the pixels at the even pixel positions inside that kernel

♦ 4 LVDS output channels (P1 only)

Figure 42 shows the data order for 4 LVDS output

channels. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

14

2

12

4

10

6

8

Figure 42. P1−SN/FN: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a

Monochrome Sensor

♦ 2 LVDS output channels

Figure 43 shows the data order for 2 LVDS output

channels. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

2

14 12

4

6

10

8

Figure 43. P1−SN/FN, P3−SN/FN: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a

Monochrome Sensor

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50

NOIP1SN1300A

♦ 1 LVDS output channel

Figure 44 shows the data order for 1 LVDS output

channel. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

2

4

6

14 12 10

8

Figure 44. P1−SN/FN, P3−SN/FN: Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a

Monochrome Sensor

x−direction and one pixel in the y−direction. Only the pixels

• P1−SN/FN, P3−SN/FN: Binning on Monochrome

0, 1, 4, 5, 8, 9, 12 and 13 are read out. Note that there is no

difference in data order for even/odd kernel numbers, as

opposed to the ‘no−subsampling’ readout.

Sensor

The output order in binning mode is identical to the

subsampled mode.

♦ 4 LVDS output channels (P1 only)

• P1−SE, P3−SE: Subsampling on Color Sensor

Figure 45 shows the data order for 4 LVDS output

channels. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

During subsampling on a color sensor, lines are read in a

read-2-skip−2 manner. To read out the image data with

subsampling enabled on a color sensor, two neighboring

kernels are combined to a single kernel of 16 pixels in the

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

1

13 12

4

5

9

8

Figure 45. P1−SE: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor

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51

NOIP1SN1300A

♦ 2 LVDS output channels

Figure 46 shows the data order for 2 LVDS output

channels. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

13

1

12

4

9

5

8

Figure 46. P1−SE, P3−SE: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor

♦ 1 LVDS output channel

Figure 47 shows the data order for 1 LVDS output

channel. Note that there is no difference in data order for

even/odd kernel numbers, as opposed to the

‘no−subsampling’ readout described in previous section.

kernel N−2

kernel N−1

kernel N

kernel N+1

pixel #

0

13

4

9

1

12

5

8

Figure 47. P1−SE, P3−SE: Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor

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NOIP1SN1300A

P2−SN/SE: CMOS Interface Version

• The frame_valid indication is asserted at the start of a

new frame and remains asserted until the last line of the

frame is completely transmitted.

CMOS Output Signals

The image data output occurs through a single 10−bit

parallel CMOS data output, operating at the applied clk_pll

frequency. A CMOS clock output, ‘frame valid’ and ‘line

valid’ signal synchronizes the output data.

• The line_valid indication serves the following needs:

♦ While the line_valid indication is asserted, the data

channels contain valid pixel data.

♦ The line valid communicates frame timing as it is

asserted at the start of each line and it is de−asserted

at the end of the line. Low periods indicate the idle

time between lines (ROT).

♦ The data channels transmit the calculated CRC code

after each line. This can be detected as the data

words right after the falling edge of the line valid.

No windowing information is sent out by the sensor.

8−bit/10−bit Mode

The 8−bit mode is not supported when using the parallel

CMOS output interface.

Frame Format

Frame timing is indicated by means of two signals:

frame_valid and line_valid.

Sequencer

Internal State

FOT ROT

black

ROT

line Ys+1

ROT

line Ye

FOT ROT

black

line Ys

data channels

frame_valid

line_valid

Figure 48. P2−SN/SE/FN: Frame Timing Indication

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53

x1_sꢀt

(a)

x1_eꢀnd

t

x0_start

x0_

aꢀr

end

NOIP1SN1300A

The frame format is explained with an example of the

readout of two (overlapping) windows as shown in

Figure 49 (a).

The readout of a frame occurs on a line−by−line basis. The

read pointer goes from left to right, bottom to top. Figure 49

(a) and (b) indicate that, after the FOT is finished, a number

of lines which include information of ‘ROI 0’ are sent out,

starting at position y0_start. When the line at position

y1_start is reached, a number of lines containing data of

‘ROI 0’ and ‘ROI 1’ are sent out, until the line position of

y0_end is reached. Then, only data of ‘ROI 1’ appears on the

data output until line position y1_end is reached. The

line_valid strobe is not shown in Figure 49.

1280 pixels

y1_end

y0_eꢀnꢀd

y1 ꢀstart

ROI1

ROI0

y0 ꢀstart

Reset

N

Reset

Integration Time

Handling

FOT

Exposure Time N

Exposure Time N +1

N+1

Readout Frame N

Readout Frame N -1

Readout

Handling

ROI1

FOT

ROI0

FOT

ROI0

Frame valid

(b)

Figure 49. P2−SN/SE: Frame Format to Read Out Image Data

Black Lines

possible to ‘mute’ the frame and/or line valid indications for

the black lines. Refer to Table 36 for black line, frame_valid

and line_valid settings.

Black pixel data is also sent through the data channels. To

distinguish these pixels from the regular image data, it is

Table 36. BLACK LINE FRAME_VALID AND LINE_VALID SETTINGS

bl_frame

bl_line

_valid_enable

Description

0x1

The black lines are handled similar to normal image lines. The frame valid indication is asserted

before the first black line and the line valid indication is asserted for every valid (black) pixel.

0x1

0x0

The frame valid indication is asserted before the first black line, but the line valid indication is not

asserted for the black lines. The line valid indication indicates the valid image pixels only. This

mode is useful when one does not use the black pixels and when the frame valid indication needs

to be asserted some time before the first image lines (for example, to precondition ISP pipelines).

0x0

0x1

0x0

In this mode, the black pixel data is clearly unambiguously indicated by the line valid indication,

while the decoding of the real image data is simplified.

Black lines are not indicated and frame and line valid strobes remain de−asserted. Note however

that the data channels contains the black pixel data and CRC codes (Training patterns are

interrupted).

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NOIP1SN1300A

Data order for P2−SN/SE: CMOS Interface Version

• P2−SN/SE: No Subsampling

To read out the image data through the parallel CMOS

output, the pixel array is divided in kernels. The kernel size

is eight pixels in x−direction by one pixel in y−direction.

Figure 38 on page 48 indicates how the kernels are

organized.

The image data is read out in kernels of eight pixels in

x−direction by one pixel in y−direction.

Figure 50 shows the pixel sequence of a kernel which is

read out over the single CMOS output channel. The pixel

order is different for even and odd kernel positions.

The data order of this image data on the data output

channels depends on the subsampling mode.

kernel 12

kernel 13

kernel 14

kernel 15

time

pixel # (even kernel)

pixel # (odd kernel)

0

2

4

6

1

3

5

7

5

3

1

6

4

2

0

time

Figure 50. P2−SN/SE: Data Output Order without Subsampling

pixel positions inside that kernel are read out. Figure 51

shows the data order

Note that there is no difference in data order for even/odd

kernel numbers, as opposed to the ‘no−subsampling’

readout.

• P2−SN: Subsampling On Monochrome Sensor

To read out the image data with subsampling enabled on

a monochrome sensor, two neighboring kernels are

combined to a single kernel of 16 pixels in the x−direction

and one pixel in the y−direction. Only the pixels at the even

kernel 12

kernel 13

kernel 14

kernel 15

time

pixel #

14 12 10

0

2

4

6

8

time

Figure 51. P2−SN: Data Output Order with Subsampling on a Monochrome Sensor

the y−direction. Only the pixels 0, 1, 4, 5, 8, 9, 12, and 13 are

• P2−SE: Subsampling On Color Sensor

read out. Figure 52 shows the data order.

Note that there is no difference in data order for even/odd

kernel numbers, as opposed to the ‘no−subsampling’

readout.

To read out the image data with subsampling enabled on

a color sensor, two neighboring kernels are combined to a

single kernel of 16 pixels in the x−direction and one pixel in

kernel 12

kernel 13

kernel 14

kernel 15

time

pixel #

0

13

4

9

1

12

5

8

time

Figure 52. P2−SE: Data Output Order with Subsampling on a Color Sensor

www.onsemi.com

55

NOIP1SN1300A

REGISTER MAP

The table below represents the register map for the

NOIP1xx1300A part. Deviating default values for the

NOIP1xx0500A and NOIP1xx0300A are mentioned

between brackets (“[ ]”).

Table 37. REGISTER MAP

Address

Offset

Default

(Hex)

Address

Bit Field

Register Name

Default

Description

Type

Status

Chip ID [Block Offset: 0]

0

chip_id

0x50D0

20688

Chip ID

Reserved

[15:0]

id

1

reserved

0x0001

0x0201

0x0101

1

[513,

257]

[3:0]

[9:8]

reserved

0x1

1

Reserved

resolution

0x0

[0x2,

0x1]

0 [2, 1]

Sensor Resolution

0x0: PYTHON1300,

0x1: PYTHON300

0x2: PYTHON500

[11:10]

[0]

reserved

0x0

0

Reserved

2

chip_configuration

color

0x0000

0x0

Chip General Configuration

RW

Color/Monochrome Configuration

‘0’: Monochrome

‘1’: Color

[1]

parallel

0x0

0

LVDS/Parallel Mode Selector

‘0’: LVDS

‘1’: Parallel

Reset Generator [Block Offset: 8]

0

8

soft_reset_pll

pll_soft_reset

0x0099

0x9

153

9

PLL Soft Reset Configuration

RW

[3:0]

[7:4]

PLL Reset

0x9: Soft Reset State

others: Operational

pll_lock_soft_reset

0x9

9

PLL Lock Detect Reset

0x9: Soft Reset State

others: Operational

1

2

9

soft_reset_cgen

cgen_soft_reset

0x0009

0x9

9

Clock Generator Soft Reset

RW

[3:0]

Clock Generator Reset

0x9: Soft Reset State

others: Operational

10

soft_reset_analog

mux_soft_reset

0x0999

0x9

2457

9

Analog Block Soft Reset

[3:0]

[7:4]

Column MUX Reset

0x9: Soft Reset State

others: Operational

afe_soft_reset

ser_soft_reset

0x9

9

AFE Reset

0x9: Soft Reset State

others: Operational

[11:8]

Serializer Reset

0x9: Soft Reset State

others: Operational

PLL [Block Offset: 16]

16

0

power_down

pwd_n

0x0004

0x0

4

0

PLL Configuration

RW

[0]

[1]

[2]

PLL Power Down

‘0’: Power Down,

‘1’: Operational

enable

bypass

0x0

0x1

0

1

PLL Enable

‘0’: disabled,

‘1’: enabled

PLL Bypass

‘0’: PLL Active,

‘1’: PLL Bypassed

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56

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

reserved

(Hex)

0x2113

0x13

0x1

Default

Description

Type

RW

1

17

8467

19

1

Reserved

[7:0]

[12:8]

[14:13]

reserved

0x1

1

I/O [Block Offset: 20]

20

0

config1

0x0000

0x0

0

IO Configuration

RW

[0]

clock_in_pwd_n

reserved

Power down Clock Input

Reserved

[9:8]

[10]

0x0

reserved

0x0

Reserved

PLL Lock Detector [Block Offset: 24]

0

24

pll_lock

lock

0x0000

0x0

0

PLL Lock Indication

Reserved

Status

RW

[0]

0

2

26

reserved

0x2280

0x80

8832

128

2

[7:0]

[10:8]

[14:12]

Reserved

0x2

Reserved

0x2

2

Reserved

3

27

0x3D2D

0x2D

0x3D

15661

45

Reserved

RW

[7:0]

Reserved

[15:8]

61

Reserved

Clock Generator [Block Offset: 32]

32

0

config0

0x0004

0x0

4

0

Clock Generator Configuration

[0]

[1]

[2]

[3]

enable_analog

Enable analogue clocks

‘0’: disabled,

‘1’: enabled

enable_log

select_pll

adc_mode

0x0

0x1

0x0

0

1

0

Enable logic clock

‘0’: disabled,

‘1’: enabled

Input Clock Selection

‘0’: Select LVDS clock input,

‘1’: Select PLL clock input

Set operation mode of CGEN block

‘0’: divide by 5 mode (10-bit mode),

‘1’: divide by 4 mode (8-bit mode)

[5:4]

[11:8]

[14:12]

mux

0x0

0

Multiplex Mode

Reserved

reserved

Reserved

General Logic [Block Offset: 34]

34

0

config0

enable

0x0000

0x0

0

Clock Generator Configuration

RW

[0]

Logic General Enable Configuration

‘0’: Disable

‘1’: Enable

Image Core [Block Offset: 40]

40

0

image_core_config0

imc_pwd_n

0x0000

0x0

0

Image Core Configuration

[0]

Image Core Power Down

‘0’: powered down,

‘1’: powered up

[1]

mux_pwd_n

0x0

0

Column Multiplexer Power Down

‘0’: powered down,

‘1’: powered up

www.onsemi.com

57

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

(Hex)

Default

Description

Type

[2]

colbias_enable

0x0

0

Bias Enable

‘0’: disabled

‘1’: enabled

1

41

image_core_config1

dac_ds

0x0B5A

0xA

0x5

2906

10

5

Image Core Configuration

Double Slope Reset Level

Triple Slope Reset Level

Reserved

RW

[3:0]

[7:4]

[10:8]

[12:11]

[13]

dac_ts

reserved

0x3

3

0x1

1

Reserved

0x0

0

Reserved

[14]

0x0

0

Reserved

[15]

0x0

0

Reserved

2

42

0x0001

0x1

1

Reserved

RW

[0]

[1]

1

Reserved

0x0

0

Reserved

[6:4]

[10:8]

[15:12]

0x0

0

Reserved

0x0

0

Reserved

0x0

0

Reserved

3

43

0x0000

0x0

0

Reserved

RW

[0]

[1]

0

Reserved

0x0

0

Reserved

[2]

0x0

0

Reserved

[3]

0x0

0

Reserved

[6:4]

[15:7]

0x0

0

Reserved

0x0

0

Reserved

AFE [Block Offset: 48]

48

0

power_down

pwd_n

0x0000

0x0

0

AFE Configuration

RW

[0]

Power down for AFE’s

‘0’: powered down,

‘1’: powered up

Bias [Block Offset: 64]

0

64

power_down

pwd_n

0x0000

0x0

0

Bias Power Down Configuration

RW

[0]

Power down bandgap

‘0’: powered down,

‘1’: powered up

1

65

configuration

extres

0x888B

0x1

34955

1

Bias Configuration

External Resistor Selection

‘0’: internal resistor,

‘1’: external resistor

[3:1]

[7:4]

reserved

0x5

5

Reserved

imc_colpc_ibias

imc_colbias_ibias

cp_ibias

0x8

8

Column Precharge ibias Configuration

Column Bias ibias Configuration

Charge Pump Bias

[11:8]

[15:12]

0x8

8

0x8

8

2

3

66

67

afe_bias

0x53C8

0x8

21448

8

AFE Bias Configuration

RW

[3:0]

[7:4]

afe_ibias

AFE ibias Configuration

afe_adc_iref

afe_pga_iref

mux_bias

0xC

12

ADC iref Configuration

[14:8]

0x53

0x8888

0x8

83

PGA iref Configuration

34952

8

Column Multiplexer Bias Configuration

Column Multiplexer Stage 1 Bias Configuration

[3:0]

mux_25u_stage1

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58

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

[7:4]

Register Name

mux_25u_stage2

mux_25u_delay

reserved

(Hex)

Default

Description

Type

0x8

8

Column Multiplexer Stage 2 Bias Configuration

[11:8]

0x8

8

Column Multiplexer Delay Bias Configuration

Reserved

[15:12]

0x8

8

4

5

6

68

69

70

lvds_bias

0x0088

0x8

136

LVDS Bias Configuration

LVDS Ibias

RW

[3:0]

[7:4]

lvds_ibias

8

lvds_iref

0x8

8

LVDS Iref

adc_bias

0x0088

0x8

136

LVDS Bias Configuration

VSFD Medium Bias

ADC Reference Bias

Reserved

RW

[3:0]

[7:4]

imc_vsfdmed_ibias

adcref_ibias

reserved

8

0x8

8

0x8888

0x8

34952

[3:0]

[7:4]

reserved

8

Reserved

reserved

0x8

8

Reserved

[11:8]

[15:12]

reserved

0x8

8

Reserved

reserved

0x8

8

Reserved

7

71

reserved

0x8888

34952

Reserved

RW

[15:0]

reserved

Reserved

Charge Pump [Block Offset: 72]

72

0

configuration

trans_pwd_n

0x2220

0x0

8736

0

Charge Pump Configuration

[0]

[1]

[2]

PD Trans Charge Pump Enable

‘0’: disabled,

‘1’: enabled

resfd_calib_pwd_n

sel_sample_pwd_n

0x0

0

FD Charge Pump Enable

‘0’: disabled,

‘1’: enabled

Select/Sample Charge Pump Enable

‘0’: disabled

‘1’: enabled

[6:4]

[10:8]

[14:12]

trans_trim

0x2

2

PD Trans Charge Pump Trim

FD Charge Pump Trim

resfd_calib_trim

sel_sample_trim

Select/Sample Charge Pump Trim

Charge Pump [Block Offset: 80]

reserved

Reserved

0

80

0x0000

0x0

0

RW

[1:0]

[3:2]

[5:4]

[7:6]

[9:8]

0

0x0

0

0x0

0

0x0

0

0x0

0

1

81

0x8881

34945

RW

[15:0]

Temperature Sensor [Block Offset: 96]

96

0

enable

0x0000

0x0

0

Temperature Sensor Configuration

[0]

Temperature Diode Enable

‘0’: disabled,

‘1’: enabled

[1]

[2]

reserved

0x0

0

Reserved

www.onsemi.com

59

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

[3]

Register Name

reserved

(Hex)

Default

Description

Type

0x0

0

Reserved

[4]

reserved

offset

0x0

0

[5]

0x0

[13:8]

0x0

Temperature Offset (signed)

Temperature Sensor Status

Temperature Readout

1

97

temp

0x0000

0x00

Status

[7:0]

temp

Reserved [Block Offset: 104]

reserved

Reserved

0

1

104

105

0x0000

0x0

0

RW

[15:0]

0x0000

0x0

[1:0]

[6:2]

[7]

0x0

[9:8]

[14:10]

[15]

0x0

2

3

4

5

6

7

106

107

108

109

110

111

0x0000

Status

[15:0]

Serializers/LVDS/IO [Block Offset: 112]

112

0

power_down

0x0000

0x0

0

LVDS Power Down Configuration

RW

[0]

[1]

[2]

clock_out_pwd_n

Power down for Clock Output.

‘0 ’: powered down,

‘1’: powered up

sync_pwd_n

data_pwd_n

0x0

0

Power down for Sync channel

‘0’: powered down,

‘1’: powered up

Power down for data channels (4 channels)

‘0’: powered down,

‘1’: powered up

Sync Words [Block Offset: 116]

4

116

trainingpattern

0x03A6

0x3A6

934

Data Formating - Training Pattern

RW

[9:0]

[6:0]

Training pattern sent on Data channels during

idle mode. This data is used to perform word

alignment on the LVDS data channels.

5

117

sync_code0

0x002A

0x02A

42

LVDS Power Down Configuration

frame_sync_0

Frame Sync Code LSBs - Even kernels

www.onsemi.com

60

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

sync_code1

bl_0

(Hex)

0x0015

0x015

Default

21

Description

Type

RW

6

118

Data Formating - BL Indication

[9:0]

21

Black Pixel Identification Sync Code - Even

kernels

7

8

119

120

sync_code2

img_0

0x0035

0x035

53

Data Formating - IMG Indication

RW

[9:0]

Valid Pixel Identification Sync Code - Even

kernels

sync_code3

ref_0

0x0025

0x025

37

Data Formating - IMG Indication

Reference Pixel Identification Sync Code -

Even kernels

9

121

122

sync_code4

frame_sync_1

sync_code5

bl_1

0x002A

0x02A

0x0015

0x015

42

21

LVDS Power Down Configuration

Frame Sync Code LSBs - Odd kernels

Data Formating - BL Indication

RW

[6:0]

[9:0]

10

Black Pixel Identification Sync Code -

Odd kernels

11

12

123

124

sync_code6

img_1

0x0035

0x035

53

Data Formating - IMG Indication

RW

[9:0]

Valid Pixel Identification Sync Code -

Odd kernels

sync_code7

ref_1

0x0025

0x025

37

Data Formating - IMG Indication

Reference Pixel Identification Sync Code -

Odd kernels

13

14

125

126

sync_code8

0x0059

0x059

89

Data Formating - CRC Indication

RW

[9:0]

crc

89

CRC Value Identification Sync Code

Data Formating - TR Indication

sync_code9

tr

0x03A6

0x3A6

934

Training Value Identification Sync Code

Data Block [Block Offset: 128]

0 128

blackcal

0x4008

0x08

0x0

16392

Black Calibration Configuration

Desired black level at output

RW

[7:0]

black_offset

black_samples

8

0

[10:8]

Black pixels taken into account for black

calibration.

Total samples = 2**black_samples

[14:11]

[15]

reserved

crc_seed

0x8

0x0

8

0

Reserved

CRC Seed

‘0’: All-0

‘1’: All-1

1

129

general_configuration

auto_blackcal_enable

blackcal_offset

0x0001

0x1

1

0

Black Calibration and Data Formating

Configuration

RW

[0]

Automatic blackcalibration is enabled when 1,

bypassed when 0

[9:1]

[10]

0x00

0x0

Black Calibration offset used when au-

to_black_cal_en = ‘0’.

blackcal_offset_dec

blackcal_offset is added when 0, subtracted

when 1

[11]

[12]

[13]

reserved

8bit_mode

0x0

0

Reserved

Shifts window ID indications by 4 cycles.

‘0’: 10 bit mode,

‘1’: 8 bit mode

[14]

[15]

ref_mode

0x0

0

Data contained on reference lines:

‘0’: reference pixels

‘1’: black average for the corresponding data

channel

ref_bcal_enable

Enable black calibration on reference lines

‘0’: Disabled

‘1’: Enabled

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61

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

(Hex)

0x000F

0x1

Default

Description

Type

RW

2

130

trainingpattern

15

1

Data Formating - Training Pattern

bl_frame_valid_en-

able

Assert frame_valid for black lines when ‘1’,

gate frame_valid for black lines when ‘0’.

Parallel output mode only.

[0]

[1]

bl_line_valid_enable

0x1

0x0

1

0

Assert line_valid for black lines when ‘1’, gate

line_valid for black lines when ‘0’.

Parallel output mode only.

ref_frame_valid_en-

able

Assert frame_valid for ref lines when ‘1’, gate

frame_valid for black lines when ‘0’.

Parallel output mode only.

[2]

[3]

ref_line_valid_enable

frame_valid_mode

Assert line_valid for ref lines when ‘1’, gate

line_valid for black lines when ‘0’.

Parallel output mode only.

[4]

Behaviour of frame_valid strobe between

overhead lines when [0] and/or [1] is

deasserted:

‘0’: retain frame_valid deasserted between

lines

‘1’: assert frame_valid between lines

[8]

reserved

0x0

0

Reserved

8

136

blackcal_error0

blackcal_error[15:0]

0x0000

Black Calibration Status

Status

[15:0]

Black Calibration Error. This flag is set when

not enough black samples are availlable.

Black Calibration shall not be valid.

Channels 0-16

(channels 0-7 for PYTHON1300)

9

137

138

139

140

141

144

reserved

0x0000

0xFFFF

0x0000

0x0

0

Reserved

Status

RW

[15:0]

reserved

0

Reserved

10

11

12

13

16

reserved

0

Reserved

reserved

0

Reserved

reserved

0

Reserved

reserved

0

Reserved

reserved

0

Reserved

reserved

0

Reserved

reserved

65535

Reserved

RW

reserved

65535

Reserved

test_configuration

testpattern_en

inc_testpattern

0

Data Formating Test Configuration

Insert synthesized testpattern when ‘1’

RW

[0]

[1]

0x0

Incrementing testpattern when ‘1’, constant

testpattern when ’0’

[2]

[3]

prbs_en

0x0

0

Insert PRBS when ‘1’

frame_testpattern

Frame test patterns when ‘1’, unframed test-

patterns when ‘0’

[4]

reserved

0x0

0

Reserved

17

18

145

146

reserved

0x0000

Reserved

RW

[15:0]

[7:0]

reserved

Reserved

test_configuration0

testpattern0_lsb

0x0100

0x00

256

0

Data Formating Test Configuration

Testpattern used on datapath #0 when

testpattern_en = ‘1’.

Note: Most significant bits are configured in

register 150.

[15:8]

testpattern1_lsb

0x01

1

Testpattern used on datapath #1 when

testpattern_en = ‘1’.

Note: Most significant bits are configured in

register 150.

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62

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

test_configuration1

testpattern2_lsb

(Hex)

0x0302

0x02

Default

Description

Type

RW

19

147

770

2

Data Formating Test Configuration

[7:0]

Testpattern used on datapath #2 when

testpattern_en = ‘1’.

Note: Most significant bits are configured in

register 150.

[15:8]

testpattern3_lsb

0x03

3

Testpattern used on datapath #3 when

testpattern_en = ‘1’.

Note: Most significant bits are configured in

register 150.

20

21

22

148

149

150

reserved

0x0504

0x04

0x05

0x0706

0x06

0x07

0x0000

0x0

1284

Reserved

RW

[7:0]

reserved

4

Reserved

[15:8]

reserved

5

Reserved

reserved

1798

6

Reserved

[7:0]

reserved

Reserved

[15:8]

reserved

7

Reserved

test_configuration16

testpattern0_msb

testpattern1_msb

testpattern2_msb

testpattern3_msb

reserved

0

Data Formating Test Configuration

[1:0]

[3:2]

0

Testpattern used when testpattern_en = ‘1’

0x0

0

Testpattern used when testpattern_en = ‘1’

[5:4]

0x0

0

Testpattern used when testpattern_en = ‘1’

[7:6]

0x0

0

Testpattern used when testpattern_en = ‘1’

[9:8]

0x0

0

Reserved

[11:10]

[13:12]

[15:14]

reserved

0x0

0

reserved

0x0

0

reserved

0x0

0

26

27

154

155

reserved

0x0000

0

RW

[15:0]

reserved

0

reserved

0

reserved

0

AEC [Block Offset: 160]

0 160

configuration

enable

0x0010

0x0

16

0

AEC Configuration

RW

[0]

[1]

[2]

[3]

AEC Enable

restart_filter

freeze

0x0

0

Restart AEC filter

0x0

0

Freeze AEC filter and enforcer gains

pixel_valid

0x0

0

Use every pixel from channel when 0, every

4th pixel when 1

[4]

amp_pri

0x1

1

Column amplifier gets higher priority than AFE

PGA in gain distribution if 1. Vice versa if 0

1

161

intensity

0x60B8

0xB8

24760

184

24

AEC Configuration

Target average intensity

Reserved

RW

[9:0]

desired_intensity

reserved

[15:10]

0x018

0x0080

0x80

2

3

4

162

163

164

red_scale_factor

128

Red Scale Factor

RW

[9:0]

Red Scale Factor

3.7 unsigned

green1_scale_factor

0x0080

0x80

128

Green1 Scale Factor

3.7 unsigned

green2_scale_factor

0x0080

0x80

128

Green2 Scale Factor

3.7 unsigned

www.onsemi.com

63

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

blue_scale_factor

(Hex)

0x0080

0x80

Default

128

Description

Blue Scale Factor

Type

RW

5

165

[9:0]

128

Blue Scale Factor

3.7 unsigned

6

7

166

167

reserved

0x03FF

0x0080

0x0

1023

2048

0

Reserved

RW

[15:0]

reserved

Reserved

reserved

Reserved

[1:0]

[3:2]

reserved

Reserved

reserved

0x0

0

Reserved

[15:4]

reserved

0x080

0x0001

0x0800

0x0

128

1

Reserved

8

9

168

169

min_exposure

min_gain

Minimum Exposure Time

Minimum Gain

RW

[15:0]

1

2048

0

[1:0]

[3:2]

min_mux_gain

min_afe_gain

min_digital_gain

Minimum Column Amplifier Gain

Minimum AFE PGA Gain

0x0

0

[15:4]

0x080

128

Minimum Digital Gain

5.7 unsigned

10

11

170

171

max_exposure

max_gain

0x03FF

0x100D

0x1

1023

4109

1

Maximum Exposure Time

Maximum Gain

RW

[15:0]

[1:0]

[3:2]

max_mux_gain

max_afe_gain

max_digital_gain

Maximum Column Amplifier Gain

Maximum AFE PGA Gain

0x3

3

[15:4]

0x100

256

Maximum Digital Gain

5.7 unsigned

12

172

reserved

0x0083

0x083

0x00

131

0

Reserved

RW

[7:0]

[13:8]

[15:14]

0x0

0

13

14

173

174

0x2824

0x024

0x028

0x2A96

0x6

10276

36

RW

[7:0]

[15:8]

40

10902

6

[3:0]

[7:4]

0x9

9

[11:8]

[15:12]

0xA

10

0x2

2

15

16

17

18

19

175

176

177

178

179

0x0080

0x080

0x0100

0x100

0x0100

0x100

0x0080

0x080

0x00AA

0x0AA

128

256

128

170

RW

[9:0]

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64

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

[9:0]

Register Name

reserved

(Hex)

0x0100

0x100

Default

256

341

0

Description

Type

RW

20

180

Reserved

AEC Status

reserved

21

24

181

184

reserved

0x0155

0x155

RW

[9:0]

reserved

total_pixels0

total_pixels[15:0]

0x0000

Status

[15:0]

0

Total number of pixels sampled for Average,

LSB

25

26

185

186

total_pixels1

0x0000

0x0

0

AEC Status

Status

[7:0]

total_pixels[23:16]

Total number of pixels sampled for Average,

MSB

average_status

average

0x0000

0x000

0x0

0

ASE Status

[9:0]

[12]

AEC Average Status

AEC Average Lock Status

ASE Status

avg_locked

exposure_status

exposure

27

28

187

188

0x0000

0x0

Status

[15:0]

AEC Exposure Status

ASE Status

gain_status

mux_gain

[1:0]

[3:2]

AEC MUX Gain Status

AEC AFE Gain Status

afe_gain

0x0

[15:4]

digital_gain

0x000

AEC Digital Gain Status

5.7 unsigned

29

189

reserved

0x0000

0x000

0x0

0

Reserved

Status

[12:0]

[13]

Sequencer [Block Offset: 192]

192

0

general_configuration

enable

0x0000

0x0

0

Sequencer General Configuration

RW

[0]

Enable sequencer

‘0’: Idle,

‘1’: enabled

[1]

[2]

operation selection

zero_rot_enable

0x0

0

‘0’: Global Shutter

Zero ROT mode Selection.

‘0’: Normal ROT,

‘1’: Zero ROT’

[3]

[4]

reserved

0x0

0

Reserved

triggered_mode

Triggered Mode Selection

‘0’: Normal Mode,

‘1’: Triggered Mode

[5]

[6]

slave_mode

0x0

0

Master/Slave Selection

‘0’: master,

‘1’: slave

nzrot_xsm_delay_en-

able

Insert delay between end of ROT and start of

readout in normal ROT readout mode if ‘1’.

ROT delay is defined by register xsm_delay

[7]

subsampling

binning

Subsampling mode selection

‘0’: no subsampling,

‘1’: subsampling

[8]

Binning mode selection

‘0’: no binning,

‘1’: binning

[10]

roi_aec_enable

Enable windowing for AEC Statistics.

‘0’: Subsample all windows

‘1’: Subsample configured window

[13:11]

[14]

monitor_select

reserved

0x0

0

Control of the monitor pins

Reserved

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65

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

reserved

(Hex)

Default

Description

Type

[15]

0x0

0

Reserved

1

193

delay_configuration

reserved

0x0000

0x00

0

Sequencer Delay Configuration

Reserved

RW

[7:0]

[15:8]

xsm_delay

0x00

Delay between ROT start and X-readout (Zero

ROT mode)

Delay between ROT end and X-readout

(Normal ROT mode with

nzrot_xsm_delay_enable=‘1’)

2

194

integration_control

dual_slope_enable

triple_slope_enable

fr_mode

0x00E4

0x0

228

0

Integration Control

Enable Dual Slope

Enable Triple Slope

RW

[0]

[1]

[2]

0x0

0

0x1

1

Representation of fr_length.

‘0’: reset length

‘1’: frame length

[4]

[5]

[6]

[7]

[8]

int_priority

halt_mode

fss_enable

fse_enable

reverse_y

0x0

0x1

0x0

0

1

0

Integration Priority

‘0’: Frame readout has priority over integration

‘1’: Integration End has priority over frame

readout

The current frame will be completed when the

sequencer is disabled and halt_mode = ‘1’.

When ‘0’, the sensor stops immediately when

disabled, without finishing the current frame.

Generation of Frame Sequence Start Sync

code (FSS)

‘0’: No generation of FSS

‘1’: Generation of FSS

Generation of Frame Sequence End Sync

code (FSE)

‘0’: No generation of FSE

‘1’: Generation of FSE

Reverse readout

‘0’: bottom to top readout

‘1’: top to bottom readout

[9]

reserved

0x0

0

Reserved

[11:10]

subsampling_mode

Subsampling mode

“00”: Subsampling in x and y (VITA

compatible)

“01”: Subsampling in x, not y

“10”: Subsampling in y, not x

“11”: Subsampling in x an y

[13:12]

binning_mode

0x0

0

Binning mode

“00”: Binning in x and y (VITA compatible)

“01”: Binning in x, not y

“10”: Binning in y, not x

“11”: Binning in x an y

[14]

[15]

reserved

0x0

0

1

Reserved

reserved

0x0

Reserved

3

195

roi_active0_0

roi_active0[7:0]

0x0001

0x01

Active ROI Selection

RW

[7:0]

Active ROI Selection

[0] Roi0 Active

[1] Roi1 Active

...

[7] Roi7 Active

4

5

196

197

reserved

0x0000

0x0102

0x02

0

Reserved

RW

[15:0]

[7:0]

reserved

0

Reserved

black_lines

258

2

Black Line Configuration

Number of black lines. Minimum is 1.

Range 1-255

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66

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

(Hex)

Default

Description

Blank out first lines

Type

[12:8]

gate_first_line

0x1

1

0: no blank

1-31: blank 1-31 lines

6

7

198

199

reserved

0x0000

0x000

0

1

Reserved

RW

[11:0]

[15:0]

reserved

Reserved

mult_timer0

0x0001

Exposure/Frame Rate Configuration

RW

Mult Timer

Defines granularity (unit = 1/PLL clock) of

exposure and reset_length

8

200

fr_length0

0x0000

0

Exposure/Frame Rate Configuration

[15:0]

Frame/Reset length

Reset length when fr_mode = ‘0’, Frame

Length when fr_mode = ‘1’

Granularity defined by mult_timer

9

201

202

203

204

exposure0

0x0000

0

Exposure/Frame Rate Configuration

RW

[15:0]

Exposure Time

Granularity defined by mult_timer

10

11

12

exposure_ds0

0x0000

0

Exposure/Frame Rate Configuration

Exposure Time (Dual Slope)

Granularity defined by mult_timer

exposure_ts0

0x0000

0

Exposure/Frame Rate Configuration

Exposure Time (Triple Slope)

Granularity defined by mult_timer

gain_configuration0

mux_gainsw0

afe_gain0

0x01E3

0x03

0xF

483

3

Gain Configuration

[4:0]

[12:5]

[13]

Column Gain Setting

15

0

AFE Programmable Gain Setting

gain_lat_comp

0x0

Postpone gain update by 1 frame when ‘1’ to

compensate for exposure time updates laten-

cy.

Gain is applied at start of next frame if ‘0’

13

14

205

206

digital_gain

_configuration0

0x0080

128

Gain Configuration

RW

[11:0]

db_gain0

0x080

0x037F

0x1

128

895

1

Digital Gain

sync_configuration

sync_rs_x_length

Synchronization Configuration

[0]

[1]

[2]

[3]

[4]

[5]

[6]

Update of rs_x_length will not be sync’ed at

start of frame when ‘0’

sync_black_lines

sync_dummy_lines

sync_exposure

sync_gain

0x1

1

Update of black_lines will not be sync’ed at start

of frame when ‘0’

Update of dummy_lines will not be sync’ed at

start of frame when ‘0’

Update of exposure will not be sync’ed at start of

frame when ‘0’

Update of gain settings (gain_sw, afe_gain) will

not be sync’ed at start of frame when ‘0’

sync_roi

Update of roi updates (active_roi) will not be

sync’ed at start of frame when ‘0’

sync_ref_lines

blank_roi_switch

Update of ref_lines will not be sync’ed at start of

frame when ‘0’

[8]

[9]

0x1

1

Blank first frame after ROI switching

blank

_subsampling_ss

Blank first frame after subsampling/binning

mode.

www.onsemi.com

67

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

expos-

(Hex)

Default

Description

Type

[10]

0x0

0

When ‘0’, exposure configurations are sync’ed

at the start of FOT. When ‘1’, exposure

configurations sync is disabled (continuously

syncing). This mode is only relevant for Trig-

gered snapshot - master mode, where the ex-

posure configurations are sync’ed at the start

of exposure rather than the start of FOT. For

all other modes it should be set to ‘0’.

Note: Sync is still postponed if

ure_sync_mode

sync_exposure=‘0’.

15

16

207

208

ref_lines

0x0000

0x00

0

Reference Line Configuration

RW

[7:0]

Number of Reference Lines

0-255

reserved

0x9F00

0x00

0x9F

0x0E5B

0x1

40704

Reserved

RW

[7:0]

0

[15:8]

159

19

211

3675

[0]

[1]

1

0x1

1

[2]

0x0

0

[3]

0x1

1

[6:4]

[15:8]

0x5

5

0xE

14

20

212

0x0000

0x0

0

RW

[12:0]

[15]

0

21

22

213

214

0x03FF

0x0000

0x00

0x0

1023

RW

[12:0]

1023

0

[7:0]

0

[15:8]

0

23

215

0x0103

0x1

259

RW

[0]

[1]

1

0x1

1

[2]

0x0

0

[3]

0x0

0

[4]

0x0

0

[5]

0x0

0

[6]

0x0

0

[7]

0x0

0

[8]

0x1

1

[9]

0x0

0

[10]

[11]

[12]

[13]

[14]

0x0

0

0x0

0

0x0

0

0x0

0

0x0

0

24

216

0x7F08

0x08

32520

8

RW

[6:0]

www.onsemi.com

68

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

reserved

(Hex)

Default

127

17476

68

Description

Type

[14:8]

0x7F

Reserved

25

217

reserved

0x4444

0x44

RW

[6:0]

reserved

[14:8]

reserved

0x44

68

26

27

28

218

219

220

reserved

0x4444

0x44

17476

68

RW

[6:0]

reserved

[14:8]

reserved

0x44

68

reserved

0x0016

0x016

0x00

22

[6:0]

reserved

22

[14:8]

reserved

0

lsm_prog_base_ss

0x301F

0x1F

12319

31

Sequencer Program Configuration

[6:0]

LSM Program start for non−black lines in

Snapshot shutter mode

[14:8]

lsm_black_prog_base

_ss

0x30

48

LSM Program start for black lines in Snapshot

shutter mode

29

30

221

222

reserved

0x6245

0x45

0x62

0x6230

0x30

0x62

0x001A

0x1A

0x3E01

0x1

25157

Reserved

RW

[6:0]

69

[14:8]

98

25136

[6:0]

48

[14:8]

98

31

32

223

224

26

RW

[6:0]

26

15873

[3:0]

[7:4]

[8]

1

0x00

0x0

0

[9]

0x1

1

[10]

[11]

[12]

[13]

0x1

1

0x1

1

0x1

1

0x1

1

33

34

35

225

226

227

0x5EF1

0x11

0x17

0x0

24305

RW

[4:0]

[9:5]

17

23

[14:10]

[15]

23

0

0x6000

0x00

0x18

0x0

24576

[4:0]

[9:5]

0

[14:10]

[15]

24

0

0x0000

0x0

0

[0]

[1]

0

0x0

0

www.onsemi.com

69

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

reserved

(Hex)

Default

Description

Type

[2]

[3]

[4]

0x0

0

Reserved

reserved

roi_active0_1

roi_active1[7:0]

reserved

x_resolution

0x0

0

1

0

0x0

36

37

38

39

40

41

42

43

228

229

230

231

232

233

234

235

0x0001

0x01

Active ROI Selection

ROI Configuration

Reserved

RW

[7:0]

0x0000

RW

Reserved

0x0001

0x0000

0x01E3

0x03

1

Reserved

[15:0]

1

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

483

3

Reserved

[4:0]

Reserved

[12:5]

0xF

15

Reserved

44

45

46

47

48

236

237

238

239

240

0x0080

0x080

128

0

Reserved

RW

[11:0]

[15:0]

Reserved

0x0000

0xFFFF

0x0000

0x0

Reserved

RW

0

Reserved

65535

0

Reserved

RW

Reserved

RW

0

Reserved

0x00A0

[0x0068,

0x0054]

160

[104, 84]

Sequencer Status

Status

[7:0]

x_resolution

y_resolution

0x00A0

[0x0068,

0x0054]

160

[104, 84]

Sensor x resolution

Sequencer Status

Sensor y resolution

Sequencer Status

49

50

241

242

0x0400

[0x0268,

0x01F0]

1024

[616,

496]

Status

[12:0]

[15:0]

0x0400

[0x0268,

0x01F0]

1024

[616,

496]

mult_timer_status

mult_timer

0x0000

0

Mult Timer Status (Master Snapshot Shutter

only)

51

52

243

244

reset_length_status

reset_length

0x0000

0

Sequencer Status

Status

[15:0]

Current Reset Length (not in Slave mode)

Sequencer Status

exposure_status

exposure

Current Exposure Time (not in Slave mode)

www.onsemi.com

70

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

[15:0]

Register Name

exposure_ds_status

exposure_ds

exposure_ts_status

exposure_ts

gain_status

mux_gainsw

afe_gain

(Hex)

0x0000

0x00

Default

Description

Sequencer Status

Type

53

245

0

Status

0

Current Exposure Time (not in Slave mode)

Sequencer Status

Current Exposure Time (not in Slave mode)

Sequencer Status

Current Column Gain Setting

Current AFE Programmable Gain

Sequencer Status

Digital Gain

54

55

246

247

0

Status

[15:0]

0

[4:0]

0

[12:5]

0x00

0

56

58

248

250

digital_gain_status

db_gain

0x0000

0x000

0x0

0

Status

[11:0]

[12]

0

dual_slope

triple_slope

reserved

0

Dual Slope Enabled

Triple Slope Enabled

Reserved

[13]

0x0

0

0x0423

0x03

1059

RW

[4:0]

[9:5]

reserved

3

Reserved

reserved

0x01

1

Reserved

[14:10]

reserved

0x01

1

Reserved

59

60

61

251

252

253

reserved

0x030F

0xF

783

15

3

Reserved

RW

[7:0]

reserved

Reserved

[15:8]

reserved

0x3

Reserved

reserved

0x0601

0x1

1537

1

Reserved

[7:0]

reserved

Reserved

[15:8]

reserved

0x6

6

Reserved

roi_aec_configura-

tion0

0x0000

0

AEC ROI Configuration

[7:0]

x_start

0x00

0

AEC ROI X Start Configuration (used for AEC

statistics when roi_aec_enable=‘1’)

[15:8]

x_end

0x00

AEC ROI X End Configuration (used for AEC

statistics when roi_aec_enable=‘1’)

62

63

254

255

roi_aec_configura-

tion1

0x0000

AEC ROI Configuration

RW

[12:0]

y_start

AEC ROI Y Start Configuration (used for AEC

statistics when roi_aec_enable=‘1’)

roi_aec_configura-

tion2

AEC ROI Configuration

y_end

AEC ROI Y End Configuration (used for AEC

statistics when roi_aec_enable=‘1’)

Sequencer ROI [Block Offset: 256]

0

256

roi0_configuration0

x_start

0x9F00

0x00

40704

0

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

RW

[7:0]

[15:8]

x_end

0x9F

159

0

1

2

3

257

258

259

roi0_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi0_configuration2

y_end

1023

40704

0

roi1_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

www.onsemi.com

71

NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

[12:0]

Register Name

roi1_configuration1

y_start

(Hex)

0x0000

0x03FF

0x3FF

0x9F00

0x00

Default

Description

ROI Configuration

Type

RW

4

260

0

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

ROI Configuration

Y End Configuration

ROI Configuration

X Start Configuration

X End Configuration

ROI Configuration

Y Start Configuration

5

6

261

262

roi1_configuration2

y_end

1023

40704

0

RW

[12:0]

roi2_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

7

8

9

263

264

265

roi2_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi2_configuration2

y_end

1023

40704

0

roi3_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

10

11

12

266

267

268

roi3_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi3_configuration2

y_end

1023

40704

0

roi4_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

13

14

15

269

270

271

roi4_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi4_configuration2

y_end

1023

40704

0

roi5_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

16

17

18

272

273

274

roi5_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi5_configuration2

y_end

1023

40704

0

roi6_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

19

20

21

275

276

277

roi6_configuration1

y_start

0x0000

0x03FF

0x3FF

0x9F00

0x00

RW

[12:0]

0

roi6_configuration2

y_end

1023

40704

0

roi7_configuration0

x_start

[7:0]

[15:8]

x_end

0x9F

159

0

22

278

roi7_configuration1

y_start

0x0000

RW

[12:0]

0

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NOIP1SN1300A

Table 37. REGISTER MAP

Address

Default

Offset

Address

Bit Field

Register Name

roi7_configuration2

y_end

(Hex)

0x03FF

0x3FF

Default

1023

Description

ROI Configuration

Type

RW

23

279

[12:0]

1023

Y End Configuration

Sequencer ROI [Block Offset: 384]

0

384

reserved

…

Reserved

…

RW

[15:0]

..

…

127

511

reserved

Reserved

[15:0]

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73

NOIP1SN1300A

PACKAGE INFORMATION

Pin List

The PYTHON 300, PYTHON 500, and PYTHON 1300 image sensors are available in an LVDS output configuration

(P1−SN/SE/FN, P3−SN/SE/FN), with the PYTHON 1300 also available in a CMOS output configuration (P2−SN/SE). The

LVDS I/Os comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 3.3 V signal level. Tables 38 and 39 show

the pin list for both versions.

Table 38. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE/FN LVDS INTERFACE

Pack Pin

No.

Pin Name

I/O Type

Supply

CMOS

Supply

LVDS

Direction

Description

1

vdd_33

3.3 V Supply

2

mosi

Input

Output

Input

SPI Master Out − Slave In

SPI Master In − Slave Out

SPI Clock

3

miso

4

sck

5

gnd_18

vdd_18

clock_outn

clock_outp

doutn0

1.8 V Ground

6

1.8 V Supply

7

Output

LVDS Clock Output (Negative)

LVDS Clock Output (Positive)

LVDS Data Output Channel #0 (Negative)

LVDS Data Output Channel #0 (Positive)

LVDS Data Output Channel #1 (Negative). Not connected for P3

LVDS Data Output Channel #1 (Positive). Not connected for P3

LVDS Data Output Channel #2 (Negative)

LVDS Data Output Channel #2 (Positive)

LVDS Data Output Channel #3 (Negative). Not connected for P3

LVDS Data Output Channel #3 (Positive). Not connected for P3

LVDS Sync Channel Output (Negative)

LVDS Sync Channel Output (Positive)

3.3 V Supply

8

LVDS

9

LVDS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

doutp0

LVDS

doutn1

LVDS

doutp1

LVDS

doutn2

LVDS

doutp2

LVDS

doutn3

LVDS

doutp3

LVDS

syncn

LVDS

syncp

LVDS

vdd_33

gnd_33

gnd_18

vdd_18

lvds_clock_inn

lvds_clock_inp

clk_pll

Supply

LVDS

3.3 V Ground

1.8 V Ground

1.8 V Supply

Input

LVDS Clock Input (Negative)

LVDS Clock Input (Positive)

LVDS

CMOS

Supply

Analog

Supply

Reference Clock Input for PLL

1.8 V Supply

vdd_18

gnd_18

ibias_master

vdd_33

gnd_33

vdd_pix

gnd_colpc

vdd_pix

gnd_colpc

gnd_33

1.8 V Ground

I/O

Master Bias Reference. Connect with 47k to gnd_33.

3.3 V Supply

3.3 V Ground

Pixel Array Supply

Pixel Array Ground

Pixel Array Supply

Pixel Array Ground

3.3 V Ground

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74

NOIP1SN1300A

Table 38. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE/FN LVDS INTERFACE

Pack Pin

No.

36

37

38

39

40

41

42

43

44

45

46

47

48

Pin Name

I/O Type

Supply

CMOS

Supply

Direction

Description

vdd_33

3.3 V Supply

gnd_colpc

vdd_pix

gnd_colpc

vdd_pix

trigger0

trigger1

trigger2

monitor0

monitor1

reset_n

ss_n

Pixel Array Ground

Pixel Array Supply

Pixel Array Ground

Pixel Array Supply

Trigger Input #0

Trigger Input #1

Trigger Input #2

Monitor Output #0

Monitor Output #1

Input

Output

Input

Sensor Reset (Active Low)

SPI Slave Select (Active Low)

3.3 V Ground

Input

gnd_33

Table 39. PIN LIST FOR P2−SN/SE CMOS INTERFACE

Pack Pin

No.

Pin Name

I/O Type

Supply

CMOS

Supply

CMOS

Supply

CMOS

Supply

LVDS

Direction

Description

1

vdd_33

3.3 V Supply

2

mosi

Input

Output

Input

SPI Master Out − Slave In

SPI Master In − Slave Out

SPI Clock

3

miso

4

sck

5

gnd_18

vdd_18

dout9

1.8 V Ground

6

1.8 V Supply

7

Output

Data Output Bit #9

Data Output Bit #8

Data Output Bit #7

Data Output Bit #6

Data Output Bit #5

Data Output Bit #4

Data Output Bit #3

Data Output Bit #2

Data Output Bit #1

Data Output Bit #0

Frame Valid Output

Line Valid Output

3.3 V Supply

8

dout8

9

dout7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

dout6

dout5

dout4

dout3

dout2

dout1

dout0

frame_valid

line_valid

vdd_33

gnd_33

clk_out

vdd_18

lvds_clock_inn

lvds_clock_inp

clk_pll

3.3 V Ground

Clock output

1.8 V Supply

Input

LVDS Clock Input (Negative)

LVDS Clock Input (Positive)

CMOS Clock Input

LVDS

CMOS

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75

NOIP1SN1300A

Table 39. PIN LIST FOR P2−SN/SE CMOS INTERFACE

Pack Pin

No.

Pin Name

vdd_18

I/O Type

Supply

Analog

Supply

CMOS

Supply

Direction

Description

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

1.8 V Supply

1.8 V Ground

gnd_18

ibias_master

vdd_33

I/O

Master Bias Reference. Connect with 47k to gnd_33.

3.3 V Supply

gnd_33

3.3 V Ground

vdd_pix

gnd_colpc

vdd_pix

gnd_colpc

gnd_33

Pixel Array Supply

Pixel Array Ground

Pixel Array Supply

Pixel Array Ground

3.3 V Ground

vdd_33

3.3 V Supply

gnd_colpc

vdd_pix

gnd_colpc

vdd_pix

trigger0

trigger1

trigger2

monitor0

monitor1

reset_n

Pixel Array Ground

Pixel Array Supply

Pixel Array Ground

Pixel Array Supply

Trigger Input #0

Input

Trigger Input #1

Input

Trigger Input #2

Output

Input

Monitor Output #0

Monitor Output #1

Sensor Reset (Active Low)

SPI Slave Select (Active Low)

3.3 V Ground

ss_n

Input

gnd_33

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76

NOIP1SN1300A

Table 40. MECHANICAL SPECIFICATION

Parameter

Description

Min

Typ

Max

Units

Die

Die thickness

Die Size

725

mm

(Refer to Figure 54

and Figure 55

showing Pin 1

reference as left

center)

2

9.0 X 7.95

mm

Die center, X offset to the center of package

Die center, Y offset to the center of the package

Die position, tilt to the Die Attach Plane

−50

−225

−1

0

−175

0

50

−125

1

mm

deg

Die rotation accuracy (referenced to die scribe and lead fin-

gers on package on all four sides)

−1

0

1

Optical center referenced from the die/package center (X−dir)

Optical center referenced from the die center (Y−dir)

Optical center referenced from the package center (Y−dir)

Distance from bottom of the package to top of the die surface

Distance from top of the die surface to top of the glass lid

XY size

−179.24

1542.14

1367.14

1.260

mm

1.165

0.655

1.405

1.305

mm

0.990

2

Glass Lid

13.6 X 13.6

0.55

mm

Specification

Thickness

0.5

0.6

mm

nm

%

Spectral response range

400

1000

Transmission of glass lid (refer to Figure 53)

D263 Teco

92

Glass Lid Material

Mechanical Shock

Vibration

JESD22−B104C; Condition G

2000

260

g

JESD22−B103B; Condition 1

Hz

°C

Mounting Profile

Reflow profile according to J−STD−020D.1

Recommended

Socket

Andon Electronics Corporation

http://www.andonelect.com

680−48−SM−G10−R14−X

CTE

Coefficient of Thermal expansion of the LCC Package

7.1

mm/°C

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77

NOIP1SN1300A

Package Drawing

R.19

GLASS

Side view

Cross section view

A

SECTION A−A

Figure 53. Package Drawing for the 48−pin LCC Package

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78

NOIP1SN1300A

Table 41. OPTICAL CENTER INFORMATION

PYTHON1300

PYTHON500

PYTHON300

References*

D1

X (mm)

0

Y (mm)

9000

X (mm)

Y (mm)

9000

X (mm)

Y (mm)

9000

Die Outer

Cordinates

0

D2

7950

9000

7950

9000

7950

9000

D3

7950

0

7950

0

7950

0

D4

0

Die Center

CD

3975

4500

3975

4500

3975

4500

Pixel Area

Coordinates

A1

704.56

6886.96

704.56

3795.76

4.8

8518.94

3565.34

6042.14

4.8

704.56

6886.96

704.56

3795.76

4.8

8518.94

3565.34

6042.14

4.8

704.56

6886.96

704.56

3795.76

4.8

8518.94

3565.34

6042.14

4.8

A2

A3

A4

Active Area Center

AA

Pitch

# Pixels

# Dummy

# Active Pixels

Act_A1

Act_A2

Act_A3

Act_A4

1288

1032

1288

1032

1288

1032

8

456

400

616

520

1280

1024

832

632

672

512

Active Area Coordi-

nates

723.76

6867.76

723.76

8499.74

3584.54

1798.96

5792.56

1798.96

7558.94

4525.34

2182.96

5408.56

2182.96

7270.94

4813.34

*Refer to Figure 54.

10.617 0.13

35

40

A1

30

25

20

D1

D2

A2

45

48

AA

CC

CD

A4

A3

Pixel (0.0)

ON

5

D4

D3

10

15

5.31 0.18

6.93

Figure 54. Graphical Representation of the Optical Center for PYTHON 1300/500/300 (1 of 2)

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79

NOIP1SN1300A

Top view

6.93

7.29

Center of

optical area

Center of

package

Optical area

Die

0.18

Pixel 0,0

Pin 1

Pin 2

DETAIL E

Center of

optical area

Pin 1

Pin 2

6.275

5.917

E

0.51

1.27

DETAIL D

D

View from bottom side

NOTE: Dimensions in mm

Figure 55. Graphical Representation of the Optical Center (2 of 2)

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80

NOIP1SN1300A

Packing and Tray Specification

The PYTHON packing specification with ON Semiconductor packing labels is packed as follows:

Table 42. PACKING AND TRAY SPECIFICATION

CLCC

Leads

48

Package (mm)

Tray

Quantity / Tray

64

Restraint

Bag

Box

Length

Width

Thickness*

2.28

Tray Spec#

Strap

Tray Quantity

14.22

KS−87233

Rubber

band

Double bagged

using MBB and

pink ESD bag

5 trays + 1 cover

tray

*Includes package, glass and glue attach thickness. Cover paper to be placed on the top tray.

NOTE: Dimensions in mm (Not to scale)

Figure 56. Packing and Tray Configuration (1 of 2)

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81

NOIP1SN1300A

Figure 57. Packing and Tray Configuration (2 of 2)

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82

NOIP1SN1300A

Glass Lid

As shown in Figure 52, no infrared attenuating color filter

glass is used. Use of an IR cut filter is recommended in the

optical path when color devices are used. (source:

http://www.pgo−online.com).

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors use a glass lid without any coatings. Figure 44

shows the transmission characteristics of the glass lid.

Figure 58. Transmission Characteristics of the Glass Lid

Protective Foil

For certain size and speed options, the sensor can be

delivered with a protective foil that is intended to be

removed after assembly. The dimensions of the foil are as

illustrated in Figure 59 with the tab aligned towards pin 1 of

the package.

(units in mm)

Figure 59. Dimensions of the Protective Foil

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83

NOIP1SN1300A

SPECIFICATIONS AND USEFUL REFERENCES

The following references are available to customers

under NDA at the ON Semiconductor Image Sensor Portal:

For quality and reliability information, please download

the Quality & Reliability Handbook (HBD851/D) from

www.onsemi.com.

For information on Standard terms and Conditions of

Sale, please download Terms and Conditions from

www.onsemi.com.

For information on acronyms and a glossary of terms

used, please download Image Sensor Terminology

(TND6116/D) from www.onsemi.com.

• Product Acceptance Criteria

• Product Qualification Report

• PYTHON Developer’s Guide AND9362/D

Material Composition is available at

http://www.onsemi.com/PowerSolutions/MaterialCompos

ition.do?searchParts=PYTHON1300

Return Material Authorization (RMA)

Refer to the ON Semiconductor RMA policy procedure at

http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn

alysis.pdf

Useful References

For information on ESD handling, cover glass care and

cleanliness, mounting information, please download the

Image Sensor Handling and Best Practices Application

Note (AN52561/D) from www.onsemi.com.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

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LITERATURE FULFILLMENT:

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For additional information, please contact your local

Sales Representative

◊

NOIP1SN1300A/D

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84


型号：	NOIP1SE1300A-QTI
厂家：	ONSEMI
描述：	MegaPixels Global Shutter CMOS Image Sensors 时钟传感器换能器
文件：	总84页 (文件大小：781K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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