NOIP1SE2000A-LTI [ONSEMI]
CMOS 图像传感器，2.3 MP，全局快门;
| 型号： | NOIP1SE2000A-LTI |
| 厂家： | 
ONSEMI |
| 描述： | CMOS 图像传感器，2.3 MP，全局快门 传感器 图像传感器 |
| 文件： | 总75页 (文件大小：943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NOIP1SN5000A
PYTHON 5.0/2.0 MegaPixels
Global Shutter CMOS
Image Sensors
Features
www.onsemi.com
• Data Output Options
♦ P1: 8 LVDS Data Channels
♦ P3: 4 LVDS Data Channels
• Size Options
♦ PYTHON 2000: 1920 x 1200 Active Pixels, 2/3” Optical Format
♦ PYTHON 5000: 2592 x 2048 Active Pixels, 1” Optical Format
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with
In-pixel CDS
• Monochrome (SN), Color (SE) and NIR (FN)
• Zero Row Overhead Time Mode Enabling Higher Frame Rate
• Frame Rate at Full Resolution, 8 LVDS Data Channels (P1 only)
♦ 100/85 frames per second @ 5 MP (Zero ROT/Non−Zero ROT)
♦ 230/180 frames per second @ 2 MP (Zero ROT/Non−Zero ROT)
♦ 255/200 frames per second @ Full HD (Zero ROT/Non−Zero ROT)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• Eight/Four/Two/One LVDS High Speed Serial Outputs
• Random Programmable Region of Interest (ROI) Readout
• Serial Peripheral Interface (SPI)
• Automatic Exposure Control (AEC)
• Phase Locked Loop (PLL)
Figure 1. PYTHON 5000
Description
The PYTHON 2000 and PYTHON 5000 image sensors
utilize high sensitivity 4.8 mm x 4.8 mm pixels that support
low noise “pipelined” and “triggered” global shutter readout
modes. The sensors support correlated double sampling
(CDS) readout, reducing noise and increasing dynamic
range.
The sensor has on-chip programmable gain amplifiers and
10-bit A/D converters. The integration time and gain
parameters can be reconfigured without any visible image
artifact. Optionally the on-chip automatic exposure control
loop (AEC) controls these parameters dynamically. The
image’s black level is either calibrated automatically or can
be adjusted by adding a user programmable offset.
A high level of programmability using a four wire serial
peripheral interface enables the user to read out specific
regions of interest. Up to sixteen regions can be
programmed, achieving even higher frame rates.
The image data interface of the P1 devices consists of
eight LVDS lanes, facilitating frame rates up to 100 frames
per second in Zero ROT mode for the PYTHON 5000. Each
channel runs at 720 Mbps. A separate synchronization
channel containing payload information is provided to
facilitate the image reconstruction at the receiving end.
The P3 devices are the same as the P1 but with only four
of the eight LVDS data channels enabled, facilitating frame
rates of 45 frames per second in Non Zero ROT (NZROT)
for the PYTHON 5000.
• High Dynamic Range (HDR) Modes Possible
• Dual Power Supply (3.3 V and 1.8 V)
• −40°C to +85°C Operational Temperature Range
• 84-pin LCC
• Power Dissipation
♦ 1.45 W (P1, 8 LVDS, NZROT)
♦ 915 mW (P1, P3, 4 LVDS, NZROT)
♦ 520 mW (P1, P3, 2 LVDS, NZROT)
♦ 370 mW (P1, P3, 1 LVDS, NZROT)
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Machine Vision
• Motion Monitoring
• Security
• Intelligent Traffic Systems (ITS)
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2016 − Rev. 2
NOIP1SN5000A/D
NOIP1SN5000A
ORDERING INFORMATION
Part Number
Description
Package
PYTHON 5000
84−pin LCC
NOIP1SN5000A−QDI
NOIP1SE5000A−QDI
NOIP1FN5000A−QDI
NOIP1SN5000A−QTI
NOIP1SE5000A−QTI
NOIP1FN5000A−QTI
NOIP3SN5000A−QDI
NOIP3SE5000A−QDI
NOIP3SN5000A−QTI
NOIP3SE5000A−QTI
PYTHON 2000
5 MegaPixel, Monochrome
5 MegaPixel, Bayer Color
5 MegaPixel, Monochrome with enhanced NIR
5 MegaPixel, Monochrome, Protective Film
5 MegaPixel, Bayer Color, Protective Film
5 MegaPixel, Monochrome with enhanced NIR, Protective Film
5 MegaPixel, 4 LVDS Outputs, Monochrome
5 MegaPixel, 4 LVDS Outputs, Bayer Color
5 MegaPixel, 4 LVDS Outputs, Monochrome, Protective Film
5 MegaPixel, 4 LVDS Outputs, Bayer Color, Protective Film
84−pin LCC
NOIP1SN2000A−QDI
NOIP1SE2000A−QDI
NOIP1FN2000A−QDI
NOIP1SN2000A−QTI
NOIP1SE2000A−QTI
NOIP1FN2000A−QTI
2 MegaPixel, Monochrome
2 MegaPixel, Bayer Color
2 MegaPixel, Monochrome with enhanced NIR
2 MegaPixel, Monochrome, Protective Film
2 MegaPixel, Bayer Color, Protective Film
2 MegaPixel, Monochrome with enhanced NIR, Protective Film
The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 8 LVDS interface; the
P3−SN/SE/FN base part references the mono, color and NIR enhanced version of the 4 LVDS interface. More details on the
part number coding can be found at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Package Mark
Line 1: NOI Pyxx RRRRA where xx denotes mono micro lens (SN) or color micro lens (SE) option or NIR micro lens (FN),
RRRR is the resolution (5000), (2000); y is either 1 for 8 LVDS outputs available or 3 for 4 LVDS outputs bonded
Line 2: −QDI (without protective film), −QTI (with protective film)
Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
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2
NOIP1SN5000A
SPECIFICATIONS
Key Specifications
Table 1. GENERAL SPECIFICATIONS (Note 1)
Table 2. NOMINAL ELECTRO−OPTICAL
SPECIFICATIONS
Parameter
Pixel Type
Specification
Parameter
Specification
In−pixel CDS. Global shutter pixel architecture
Pipelined and triggered global shutter
Active Pixels
PYTHON 5000: 2592 (H) x 2048 (V)
PYTHON 2000: 1984 (H) x 1264 (V)
Shutter Type
Frame Rate
Zero ROT/ Non−Ze-
ro ROT Mode
P1−SN/SE/FN:
PYTHON 2000: 230/180 fps
PYTHON 5000: 100/85 fps
Pixel Size
4.8 mm x 4.8 mm
-,
-
Conversion Gain
Temporal Noise
0.096 LSB10/e 140 mV/e
P3−SN/SE/FN: NA/45 fps
-
< 10.7 e (Non−Zero ROT, 1x gain)
-
Master Clock
Windowing
P1,P3−SN/SE/FN:
< 9.4 e (Non−Zero ROT, 2x gain)
72 MHz when PLL is used,
360 MHz (10-bit) / 288 MHz (8-bit) when
PLL is not used
Responsivity at 550 nm
7.5 V/lux.s
<1/5000
Parasitic Light
Sensitivity (PLS)
16 Randomly programmable windows.
Normal, sub-sampled and binned readout
modes
-
Full Well Charge
10000 e
ADC Resolution
(Note 1)
10-bit, 8-bit
Quantum Efficiency
at 550 nm
57%
LVDS Outputs
P1−SN/SE/FN: 8/4/2/1 data + sync + clock
P3−SN/SE/FN: 4/2/1 data + sync + clock
Pixel FPN
PRNU
MTF
< 1.55 LSB10 (Non−Zero ROT)
< 1.35 (Zero−ROT)
< 10 LSB10 on half scale response of
525 LSB10
Data Rate
P1−SN/SE/FN:
8 x 720 Mbps (10-bit) /
8 x 576 Mbps (8-bit)
P3−SN/SE/FN:
4 x 720 Mbps (10−bit)
66% @ 535 nm − X-dir & Y-dir
-
Pixel Storage Node Leakage
(PSNL) @ 20°C
(t_int = 30 ms)
300 LSB10/s, 2800 e /s
Power Dissipation
(10−bit mode)
P1−SN/SE/FN: 1.45 W (8 data channels)
P1&P3−SN/SE/FN: 915 mW (4 data channels)
P1&P3−SN/SE/FN: 520 mW (2 data channels)
P1&P3−SN/SE/FN: 370 mW (1 data channel)
-
Dark Signal @ 20°C
9.3 e /s, 1.0 LSB10/s
Dark Current Doubling
Temperature
5.2°C
Package Type
84-pin LCC
Dynamic Range
60 dB
40 dB
Signal to Noise Ratio
(SNR max)
Table 3. RECOMMENDED OPERATING RATINGS (Note 2)
Symbol
Description
Operating junction temperature range
Min
Max
Unit
T
J
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)
Symbol
Parameter
ABS rating for 1.8 V supply group
Min
–0.5
–0.5
−40
Max
2.2
Unit
V
ABS (1.8 V supply group)
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
4.3
V
T
S
ABS storage temperature range
+150
85
°C
ABS storage humidity range at 85°C
Human Body Model (HBM): JS−001−2012
Charged Device Model (CDM): EIA/JESD22−C101, Class C1
Latch−up: JESD−78
%RH
V
Electrostatic discharge (ESD)
LU
2000
500
100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
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3
NOIP1SN5000A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for T = T
to T
, all other limits T = +30°C. (Notes 5, 6, 7, 8 and 9)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
Units
Power Supply Parameters − P1 − SN/SE/FN (ZROT)
(Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Supply voltage, 3.3 V
3.2
3.3
355
1.8
3.4
1.9
V
mA
V
Current consumption 3.3 V supply
Supply voltage, 1.8 V
1.7
Current consumption 1.8 V supply
Supply voltage, pixel
140
3.3
mA
V
3.25
3.35
Current consumption pixel supply
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
Power consumption in low power standby mode
Power consumption at lower pixel rates
10
mA
W
1.45
Pstby_lp
Popt
50
mW
Configurable
Power Supply Parameters − P3 − SN/SE/FN (NZROT)
(Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Supply voltage, 3.3 V
3.2
3.3
215
1.8
105
3.3
5
3.4
1.9
V
mA
V
Current consumption 3.3 V supply (4/2/1 LVDS)
Supply voltage, 1.8 V
1.7
Current consumption 1.8 V supply (4/2/1 LVDS)
Supply voltage, pixel
mA
V
3.25
3.35
Current consumption pixel supply (4/2/1 LVDS)
mA
mW
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
P3, 4 LVDS, NZROT
P3, 2 LVDS, NZROT
P3, 1 LVDS, NZROT
915
520
370
Pstby_lp
Popt
Power consumption in low power standby mode
Power consumption at lower pixel rates
50
mW
Configurable
I/O − P1,P3 − SN/SE/FN (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
720
360
Mbps
MHz
DDR signaling − 4 data channels, 1 synchronization channel
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
Vicm
LVDS input common mode level
0.3
1.25
1.8
50
V
Tccsk
Channel to channel skew (Training pattern should be used to correct
per channel skew)
ps
Electrical Interface − P1,P3 − SN/SE/FN
fin
Input clock rate when PLL used
72
360
55
MHz
MHz
%
fin
Input clock when LVDS input used
tidc
Input clock duty cycle when PLL used
45
50
tj
Input clock jitter
20
ps
fspi
SPI clock rate when PLL used at fin = 72 MHz
10−bit (8 LVDS channels), PLL used (fin = 72 MHz) − P1 only
10−bit (4 LVDS channels), PLL used (fin = 72 MHz)
10−bit (2 LVDS channels), PLL used (fin = 72 MHz)
10−bit (1 LVDS channel), PLL used (fin = 72 MHz)
10−bit (8 LVDS channels), LVDS input used (fin = 360 MHz)
10−bit (4 LVDS channels), LVDS input used (fin = 360 MHz)
10
MHz
ratspi (=fin/fspi)
6
12
24
48
30
60
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
www.onsemi.com
4
NOIP1SN5000A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for T = T
to T
, all other limits T = +30°C. (Notes 5, 6, 7, 8 and 9)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
Units
Electrical Interface − P1,P3 − SN/SE/FN
10−bit (2 LVDS channels), LVDS input used (fin = 360 MHz)
10−bit (1 LVDS channel), LVDS input used (fin = 360 MHz)
8−bit (8 LVDS channels), PLL used (fin = 72 MHz)
120
240
6
8−bit (4 LVDS channels), PLL used (fin = 72 MHz)
12
24
48
24
48
96
192
8−bit (2 LVDS channels), PLL used (fin = 72 MHz)
8−bit (1 LVDS channel), PLL used (fin = 72 MHz)
8−bit (8 LVDS channels), LVDS input used (fin = 288 MHz)
8−bit (4 LVDS channels), LVDS input used (fin = 288 MHz)
8−bit (2 LVDS channels), LVDS input used (fin = 288 MHz)
8−bit (1 LVDS channel), LVDS input used (fin = 288 MHz)
Frame Specifications − P1 − SN/SE/FN
Maximum
Non−Zero ROT
Zero ROT
100
Units
fps
fps_roi1
fps_roi2
fps_roi3
fps_roi4
fps_roi5
fps_roi6
fps_roi7
fps_roi8
fps_roi9
fps_roi10
fps_roi11
fps_roi12
fpix
Xres x Yres = 2592 x 2048
Xres x Yres = 2048 x 2048
Xres x Yres = 1920 x 1200
Xres x Yres = 1920 x 1080
Xres x Yres = 1600 x 1200
Xres x Yres = 1024 x 1024
Xres x Yres = 1280 x 720
Xres x Yres = 800 x 600
Xres x Yres = 640 x 480
Xres x Yres = 512 x 512
Xres x Yres = 256 x 256
Xres x Yres = 544 x 20
85
100
180
200
205
395
390
620
855
890
2065
7980
576
130
fps
230
fps
255
fps
275
fps
480
fps
550
fps
985
fps
1450
1555
2830
10345
576
fps
fps
fps
fps
Pixel rate (8 channels at 72 Mpix/s)
Mpix/s
Frame Specifications − P3 − SN/SE/FN
Typical (Non−Zero ROT)
4 LVDS
45
2 LVDS
25
1 LVDS
10
Units
fps
fps_roi1
fps_roi2
fps_roi3
fps_roi4
fps_roi5
fps_roi6
fps_roi7
fps_roi8
fps_roi9
fps_roi10
fps_roi11
fps_roi12
fpix
Xres x Yres = 2592 x 2048
Xres x Yres = 2048 x 2048
Xres x Yres = 1920 x 1200
Xres x Yres = 1920 x 1080
Xres x Yres = 1600 x 1200
Xres x Yres = 1024 x 1024
Xres x Yres = 1280 x 720
Xres x Yres = 800 x 600
Xres x Yres = 640 x 480
Xres x Yres = 512 x 512
Xres x Yres = 256 x 256
Xres x Yres = 544 x 20
55
30
15
fps
100
110
55
25
fps
60
30
fps
115
60
30
fps
195
230
385
550
590
1590
6260
288
105
125
220
320
350
990
4340
144
55
fps
65
fps
115
175
190
580
2690
72
fps
fps
fps
fps
fps
Pixel rate (8 channels at 72 Mpix/s)
Mpix/s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
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5
NOIP1SN5000A
Color Filter Array
The PYTHON color sensors are processed with a Bayer RGB color pattern as shown in Figure 2. Pixel (0,0) has a red filter
situated to the bottom left.
Y
Gb
Gr
X
pixel (0;0)
Figure 2. Color Filter Array for the Pixel Array
Quantum Efficiency
Figure 3. Quantum Efficiency Curves
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NOIP1SN5000A
Ray Angle and Microlens Array Information
An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of the
photodiodes. The combined microlens array and pixel array
has two important properties:
versus photodiode position will cause a tilted angle of peak
photoresponse, here denoted Chief Ray Angle (CRA).
Microlenses and photodiodes are aligned with 0 shift and
CRA in the center of the array, while the shift and CRA
increases radially towards its edges, as illustrated by
Figure 6.
The purpose of the shifted microlenses is to improve the
uniformity of photoresponse when camera lenses with
a finite exit pupil distance are used. In the standard version
of Python 5000, the CRA varies nearly linearly with distance
from the center as illustrated in Figure 7, with a corner CRA
of approximately 5.4 degrees. This edge CRA is matching
a lens with exit pupil distance of ~80 mm.
Angular Dependency of Photoresponse of a Pixel
The photoresponse of a pixel with microlens in the center
of the array to a fixed optical power with varied incidence
angle is as plotted in Figure 4, where definitions of angles
fx and fy are as described by Figure 5.
Microlens Shift across Array and CRA
The microlens array is fabricated with a slightly smaller
pitch than the array of photodiodes. This difference in pitch
creates a varying degree of shift of a pixel’s microlens with
regards to its photodiode. A shift in microlens position
Incidence Angle f , f
x
y
[degrees deviation from normal]
Note that the Photoresponse Peaks near Normal Incidence for Center Pixels
Figure 4. Center Pixel Photoresponse to a Fixed Optical Power with Incidence Angle Varied along fx and fy
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NOIP1SN5000A
Figure 5. Definition of Angles Used in Figure 4
Center Pixel
(aligned)
Edge Pixel
(with shift)
The center axes of the microlens and the photodiode coincide for the center pixels. For the edge pixels,
there is a shift between the axes of the microlens and the photodiode causing a Peak Response Incidence
Angle (CRA) that deviates from the normal of the pixel array.
Figure 6. Principle of Microlens Shift
6
5
4
3
2
1
0
0
2
4
6
8
Distance from center [mm]
Figure 7. Variation of Peak Responsivity Angle (CRA)
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8
NOIP1SN5000A
OVERVIEW
Figures 8 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core
Image Core Bias
Pixel Array
Column Structure
Automatic
Exposure
Control
(AEC)
16 Analog channels
Analog Front End (AFE)
16 x 10 bit
Digital channels
Control &
Registers
Clock
Distribution
Data Formatting
8 x 10 bit
Digital channels
Serializers & LVDS Interface
LVDS
PLL
Receiver
8/4/2/1 LVDS Channels
1 LVDS Sync Channel
1 LVDS Clock Channel
CMOS Clock
Input
LVDS Clock
Input
Figure 8. Block Diagram
Image Core
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz in 10−bit mode
and 288 MHz in 8−bit mode. The clock input needs to be
terminated with a 100 W resistor.
The image core consists of:
• Pixel Array
• Address Decoders and Row Drivers
• Pixel Biasing
The PYTHON 5000 pixel array contains 2592 (H) x
2048 (V) readable pixels with a pixel pitch of 4.8 mm.
The PYTHON 2000 image array contains 1984 (H) x
1264 (V) readable pixels, inclusive of 32 pixels on each side
to allow for reprocessing or color reconstruction.
The sensors use in−pixel CDS architecture, which makes
it possible to achieve a low noise read out of the pixel array
in global shutter mode with the function of the row drivers
is to access the image array to reset or read the pixel data. The
row drivers are controlled by the on−chip sequencer and can
access the pixel array.
Column Multiplexer
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 16 parallel differential outputs operating at a
frequency of 36 MHz. At this stage, the reset signal and
integrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 4x can be applied to the signal. The column
multiplexer
also
supports
read−1−skip−1
and
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
read−2−skip−2 mode. Enabling this mode increases the
frame rate, with a decrease in resolution.
Bias Generator
Phase Locked Loop
The bias generator generates all required reference
voltages and bias currents used on chip. An external resistor
of 47 kW, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operate
properly.
The PLL accepts a (low speed) clock and generates the
required high speed clock. Optionally this PLL can be
bypassed. Typical input clock frequency is 72 MHz.
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NOIP1SN5000A
Analog Front End
The AFE contains 16 channels, each containing a PGA
and a 10−bit ADC.
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.
For each of the 16 channels, a pipelined 10−bit ADC is
used to convert the analog image data into a digital signal,
which is delivered to the data formatting block. A black
calibration loop is implemented to ensure that the black level
is mapped to match the correct ADC input level.
Channel Multiplexer
The P1−SN/SE/FN LVDS channel multiplexer provides
a 8:4, 8:2 and 8:1 feature, in addition to utilizing all 8 output
channels.
The P3−SN/SE/FN LVDS channel multiplexer provides
a 4:2 and 4:1 feature, in addition to utilizing all 4 output
channels.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
Sequencer
The sequencer:
• Controls the image core. Starts and stops integration
and control pixel readout.
• Operates the sensor in master or slave mode.
• Applies the window settings. Organizes readouts so that
only the configured windows are read.
• Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
• Starts up the sensor correctly when leaving standby
mode.
A
frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Serializer and LVDS Interface
The serializer and LVDS interface block receives the
formatted (10−bit or 8−bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10−bit mode, the maximum output data rate is
720 Mbps per channel. In 8−bit mode, the maximum output
data rate is 576 Mbps per channel.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
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10
FOT
Readout Fra
e
-1
eadout Fra e N
Integration Ti
Handling
e
Reset
N
Reset
N+1
NOIP1SN5000A
OPERATING MODES
Global Shutter Mode
The PYTHON 2000 and PYTHON 5000 operates in
pipelined or triggered global shutter modes. In this mode,
light integration takes place on all pixels in parallel,
although subsequent readout is sequential. Figure 9 shows
the integration and readout sequence for the global shutter
mode. All pixels are light sensitive at the same period of
time. The whole pixel core is reset simultaneously and after
the integration time all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out
line by line after integration. Note that the integration and
readout can occur in parallel or sequentially. The integration
starts at a certain period, relative to the frame start.
Figure 9. Global Shutter Operation
Pipelined Global Shutter Mode
Overhead Time (ROT). Figure 10 shows the exposure and
readout time line in pipelined global shutter mode.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N−1. The readout of every frame starts with
a Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
Master Mode
The PYTHON 2000 and PYTHON 5000 operate in
pipelined or triggered global shuttering modes. In this mode,
light, the integration time is set through the register interface
and the sensor integrates and reads out the images
autonomously. The sensor acquires images without any user
interaction.
Exposure Time N
FOT
FOT
Exposure Time N+1
FOT
FOT
Readout
Handling
ROT
Line Readout
Figure 10. Pipelined Shutter Operation in Master Mode
Slave Mode
of reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon a
falling edge of the trigger input, the image is sampled and the
readout begins. Figure 11 shows the relation between the
external trigger signal and the exposure/readout timing.
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode and
the integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out
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11
Exposure Ti
Register Controlled
Readout -1
FOT
FOT
Exposure Ti
Readout N
e N
e
+1
FOT
FOT
FOT
Integration Ti
Handling
e
Reset
N
Reset
N+1
NOIP1SN5000A
External Trigger
Integration Time
Handling
Reset
N
Reset
N+1
Exposure Time N
FOT
FOT
Exposure T im e N+1
Readout N
FOT
FOT
Readout
Handling
FOT
Readout N−1
ROT
Line Readout
Figure 11. Pipelined Shutter Operation in Slave Mode
Triggered Global Shutter Mode
The triggered global shutter mode can also be controlled
in a master or in a slave mode.
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are:
Master Mode
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 12 shows the relation between the external trigger
signal and the exposure/readout timing.
• Upon user action, one single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
If a rising edge is applied on the external trigger before the
exposure time and FOT of the previous frame is complete,
it is ignored by the sensor.
• Integration and readout is under user control through an
external pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.
No effect on falling edge
External Trigger
Readout
Handling
ROT
Line Readout
Figure 12. Triggered Shutter Operation in Master Mode
Slave Mode
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, the
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12
NOIP1SN5000A
Non−Zero and Zero Row Overhead Time (ROT) Modes
This operation mode can be used for two reasons:
• Reduced total line time.
• Lower power due to reduced clock−rate.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
out and integration of frame N is ongoing during readout of
the previous frame N−1. The readout of every frame starts
with a Frame Overhead Time (FOT), during which the
analog value of the pixel diode is transferred to the pixel
memory element. After the FOT, the sensor is read out line
by line and the readout of each line is preceded by a Row
Overhead Time (ROT) as shown in Figure 13.
In Reduced/Zero ROT operation mode (refer to
Figure 14), the row blanking and kernel readout occur in
parallel. This mode is called reduced ROT as a part of the
ROT is done while the image row is readout. The actual ROT
can thus be longer, however the perceived ROT will be
shorter (‘overhead’ spent per line is reduced).
FOT
(
)
ROT
ys
Readout
ys
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye
Valid Data
Figure 13. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Non−Zero ROT Readout.
FOT
(
)
ROT
ys
(blanked ou)t
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye−1
ROT
dummy
Readout
ye
Valid Data
Figure 14. Integration and Readout Sequence of the Sensor operating in Pipelined Global Shutter Mode with
Zero ROT Readout.
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13
NOIP1SN5000A
SENSOR OPERATION
Flowchart
Figure 15 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval
circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.
Power Off
Power Down
Sequence
Power Up Sequence
Low-Power Standby
Disable Clock Management
Part 1
Enable Clock Management - Part 1
Poll Lock Indication
(only when PLL is enabled)
Standby (1)
Enable Clock Management - Part 2
(First Pass after Hard Reset)
Disable Clock Management
Part 2
Intermediate Standby
Required Register
Upload
Sensor (re-)configuration
(optional)
Standby (2)
Soft Power-Down
Soft Power-Up
Sensor (re-)configuration
(optional)
Idle
Enable Sequencer
Disable Sequencer
Sensor (re-)configuration
(optional)
Running
Figure 15. Sensor Operation Flowchart
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14
NOIP1SN5000A
Sensor States
clock input
Low Power Standby
In low power standby state, all power supplies are on, but
internally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
All register settings are set to their default values (see
Table 37).
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave the
low power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable Clock
Management’ action described in Enable Clock
Management − Part 1 on page 16
reset_n
vdd_18
vdd_33
vdd_pix
SPI Upload
> 10us
> 10us
> 10us
> 10us
> 10us
Figure 16. Power Up Sequence
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
Enable Clock Management − Part 1
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for P1, P3 − SN/SE/FN 10−bit serial mode, with
the PLL, and all available LVDS channels.
Note that the SPI uploads to be executed to configure the
sensor for other supported modes (P1−SN/SE 8−bit
serial,...) are available to customers under NDA at the
ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
If the PLL is not used, the LVDS clock input must be
running.
It is important to follow the upload sequence listed in
Table 6.
Standby (2)
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
Idle
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slave
modes.
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 16 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the described
sequence. Any other supply ramping sequence may lead to
high current peaks and, as consequence, a failure of the
sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
Management− Part 2’ action can be continued. When PLL
is not used, this step can be bypassed as shown in Figure 15
on page 14.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
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15
NOIP1SN5000A
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
2
2
0x0000
0x0001
0x7004
0x7014
0x0000
0x2113
0x2280
0x3D2D
0x0000
0x0003
Monochrome sensor
Color sensor
32
Configure clock management P1 only
Configure clock management P3 only
Configure clock management
Configure PLL
3
4
5
6
7
8
20
17
26
27
8
Configure PLL lock detector
Configure PLL lock detector
Release PLL soft reset
16
Enable PLL
Enable Clock Management − Part 2
The next step to configure the clock management consists
of SPI uploads which enables all internal clock distribution.
The required uploads are listed in Table 7. Note that it is
important to follow the upload sequence listed in Table 7.
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
P1, P3 − SN/SE/FN 10−bit mode with PLL
1
2
9
0x0000
0x7006
0x7016
0x0001
Release clock generator soft reset
Enable logic clock for P1 only
Enable logic clock for P3 only
Enable logic block
32
3
34
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads are listed in Table 8.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
176
177
192
193
194
197
199
200
201
204
207
208
211
215
216
219
220
224
0x00E6
0x0400
0x000C
0x4E00
0x02E4
0x0104
0x0196
0x0804
0x00B1
0x01E1
0x0000
0xA100
0x0E49
0x111F
0x7F00
0x0020
0x2434
0x3E17
0x00E6
0x0400
0x000C
0x2C00
0x02E4
0x0104
0x0174
0x0804
0x0060
0x01E1
0x0000
0xA100
0x0E39
0x111F
0x7F00
0x0020
0x2432
0x3E17
Table 8. REQUIRED REGISTER UPLOADS
P1−SN/SE/FN 10−bit
mode with PLL
P3−SN/SE/FN 10−bit
mode with PLL
Up-
Ad-
load #
dress
(8 LVDS NZROT)
(4 LVDS NZROT)
1
2
41
42
0x0854
0x0200
0x000C
0x48CB
0x53C8
0x8688
0x0085
0x0888
0x4411
0x9788
0x3330
0x4714
0x8001
0x1002
0x0080
0x0854
0x0200
0x000C
0x48CB
0x53C4
0x4544
0x0085
0x0848
0x4411
0x9788
0x3330
0x4714
0x8001
0x1002
0x0080
3
43
4
65
5
66
6
67
7
68
8
69
9
70
10
11
12
13
14
15
71
72
128
129
171
175
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16
NOIP1SN5000A
P1−SN/SE/FN 10−bit
mode with PLL
P3−SN/SE/FN 10−bit
mode with PLL
P1−SN/SE/FN 10−bit
mode with PLL
P3−SN/SE/FN 10−bit
mode with PLL
Up-
Ad-
Up-
Ad-
load #
dress
(8 LVDS NZROT)
(4 LVDS NZROT)
load #
dress
(8 LVDS NZROT)
(4 LVDS NZROT)
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
227
250
256
257
258
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
0x0000
0x2081
0xA100
0x0000
0x07FF
0xC800
0xFB1F
0xFB1F
0xFB12
0xF912
0xF902
0xF804
0xF008
0xF102
0xF30F
0xF30F
0xF30F
0xF30F
0xF30F
0xF30F
0xF102
0xF008
0xF24A
0xF264
0xF226
0xF021
0xF002
0xF40A
0xF005
0xF20F
0xF20F
0xF20F
0xF20F
0xF005
0xEC05
0xC801
0xC800
0x0000
0x2081
0xA100
0x0000
0x07FF
0xC800
0xFB1F
0xFB1F
0xFB12
0xF912
0xF902
0xF804
0xF008
0xF102
0xF30F
0xF30F
0xF30F
0xF30F
0xF30F
0xF30F
0xF102
0xF008
0xF24A
0xF264
0xF226
0xF021
0xF002
0xF40A
0xF005
0xF20F
0xF20F
0xF20F
0xF20F
0xF005
0xEC05
0xC801
0xC800
71
72
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
0xC800
0xCC0A
0xC806
0xC800
0x0030
0x2179
0x2071
0x0071
0x107F
0x1079
0x0071
0x0031
0x01B4
0x21B9
0x20B1
0x00B1
0x10BF
0x10B9
0x00B1
0x0030
0x0030
0x2079
0x2071
0x0071
0x107F
0x1079
0x0071
0x0031
0x01B4
0x21B9
0x20B1
0x00B1
0x10BF
0x10B9
0x00B1
0x0030
0xC800
0xCC0A
0xC806
0xC800
0x0030
0x2175
0x2071
0x0071
0x107C
0x0071
0x0031
0x01B2
0x21B5
0x20B1
0x00B1
0x10BC
0x00B1
0x0030
0x0030
0x2075
0x2071
0x0071
0x107C
0x0071
0x0031
0x01B2
0x21B5
0x20B1
0x00B1
0x10BC
0x00B1
0x0030
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
NOTE: Register uploads for other supported operation modes can
be accessed at the Image Sensor Portal on MyON.
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17
NOIP1SN5000A
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 9.
Table 9. SOFT POWER UP REGISTER UPLOADS
Upload #
Address
Data
Description
P1,P3 − SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NZROT)
1
2
10
32
0x0000
0x7007
0x7017
0x0001
0x0003
0x0001
0x0085
0x3337
0x0007
Release soft reset state
Enable analogue clock P1 only
Enable analogue clock P3 only
Enable biasing clock
3
4
5
6
7
8
64
40
Enable column multiplexer
Enable AFE
48
68
Enable LVDS bias
72
Enable charge pump
112
Enable LVDS transmitters
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 15.
The ‘Enable Sequencer’ action consists of a set of register
uploads. The required uploads are listed in Table 10.
Table 10. ENABLE SEQUENCER REGISTER UPLOADS
Upload #
Address
Data
1
192
0x080D
User Actions: Functional Modes to Power Down Sequences
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set of register
uploads. as listed in Table 11.
Table 11. DISABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
1
192
0x080C
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
current dissipation. This action exists of a set of SPI uploads.
The soft power down uploads are listed in Table 12.
Table 12. SOFT POWER DOWN REGISTER UPLOADS
Upload #
Address
Data
Description
P1,P3 − SN/SE/FN 10−bit mode with PLL (P1 in ZROT, P3 in NZROT)
1
2
3
4
5
6
112
72
48
40
64
32
0x0000
0x3330
0x0000
0x0000
0x0000
0x7006
0x7016
0x0999
Disable LVDS transmitters
Disable charge pump
Disable AFE
Disable column multiplexer
Disable biasing clock
Disable analogue clock P1 only
Disable analogue clock P3 only
Soft reset
7
10
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NOIP1SN5000A
Disable Clock Management − Part 2
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 13.
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
P1,P3 − SN/SE/FN 10−bit mode with PLL
1
32
0x7004
0x7014
0x0000
0x0009
Disable logic clock P1 only
Disable logic clock P3 only
Disable logic blocks
2
3
34
9
Soft reset clock generator
Disable Clock Management − Part 1
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 14.
Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
P1,P3 − SN/SE/FN 10−bit mode with PLL
1
2
8
0x0099
0x0000
Soft reset PLL
Disable PLL
16
Power Down Sequence
Figure 17 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
clock input
reset_n
vdd_18
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
vdd_33
vdd_pix
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
> 10us > 10us > 10us > 10us
(lvds_clock_inn/p) in case the PLL is bypassed.
Figure 17. Power Down Sequence
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NOIP1SN5000A
Sensor reconfiguration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 28 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 29 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
Some registers are only modified when the sensor is not
acquiring images. reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 15. STATIC READOUT PARAMETERS
Group
Clock generator
Addresses
32
Description
Configure according to recommendation
Image core
40
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
AFE
48
Bias
64–71
72
Charge Pump
LVDS
112
Sequencer mode selection
192 [6:1]
Operation modes are: • triggered_mode
• slave_mode
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
The category of registers as shown in Table 16 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[12:8]
Reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black level com-
pensation.
Sync codes
129[13]
Incorrect sync codes may be generated during the frame in which these registers are modified.
116–126
Datablock test configurations
144, 146–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
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20
NOIP1SN5000A
Dynamic Readout Parameters
shown in Table 17. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 17. DYNAMIC READOUT PARAMETERS
Group
Addresses
Description
Subsampling/binning
192[7]
192[8]
Subsampling or binning is synchronized to a new frame start.
ROI configuration
195
256–303
A ROI switch is only detected when a new window is selected as the active window
(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does not
lead to a frame blank and can cause a corrupted image.
Exposure
reconfiguration
199−203
Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unless
reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).
Gain reconfiguration
204
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be incorporated
to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Freezing Active Configurations
them for the coming frames. The freezing of the active set
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before reconfiguration. When all registers are
uploaded, re−enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
of registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
Figure 18 shows a reconfiguration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 19 shows the usage of the sync_configuration
settings. Before uploading
a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3
Frame N+4
Time Line
SPI Registers
Active Registers
Figure 18. Frame Synchronization of Configurations (no freezing)
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3ꢁꢁꢂꢀFrame N+4
Time Line
sync_configuration
SPI Registers
This configuration is not taken into
account as sync_register is inactive.
Active Registers
Figure 19. reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being
frozen.
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NOIP1SN5000A
Table 18. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_exposure
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_gain
sync_roi
mux_gainsw
afe_gain
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
roi_active0[15:0]
subsampling
binning
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration of
active windows is not gated by this setting.
Window Configuration
Black Calibration
The sensor automatically calibrates the black level for
Global Shutter Mode
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 16 columns contained
in one kernel. This implies 16 black level offsets are
generated and applied to the corresponding columns.
Configurable parameters for the black−level algorithm are
listed in Table 19.
Up to 16 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 303. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address
Black Line Generation
197[7:0]
Register Name
Description
black_lines
This register configures the number of black lines that are generated at the start of a frame. At least one
black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this register is
configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and window configu-
rations:
Each black line contains 162 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured. These blanked out
lines are not used for black calibration. It is recommended to enable this functionality, because the first
line can have a different behavior caused by boundary effects. When enabling, the number of black
lines must be set to at least two in order to have valid black samples for the calibration algorithm.
Black Value Filtering
129[0]
auto_blackcal_enable
Internal black−level calibration functionality is enabled when set to ‘1’. Required black level offset com-
pensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible to apply an
offset compensation to the image pixels, which is defined by the registers 129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
129[10]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_en-
able is set to ‘0’. The sign of the offset is determined by register 129[10] (blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is disabled.
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set to ‘1’, the
black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
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NOIP1SN5000A
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address
Black Line Generation
128[10:8]
Register Name
Description
black_samples
The black samples are low−pass filtered before being used for black level calculation. The more sam-
ples are taken into account, the more accurate the calibration, but more samples require more black
lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested (refer to register
136).
Black Level Filtering Monitoring
136 blackcal_error0
An error is reported by the device if there are requests for more samples than are available (each bit
corresponding to one data path). The black level is not compensated correctly if one of the channels
indicates an error. There are three possible methods to overcome this situation and to perform a correct
offset compensation:
• Increase the number of black lines such that enough samples are generated at the cost of increas-
ing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to
register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload. Note that
the black level can drift in function of the temperature. It is thus recommended to perform the offset
calibration periodically to avoid this drift.
NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.
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NOIP1SN5000A
Serial Peripheral Interface
first. The sck clock is passed through to the sensor
as indicated in Figure 20. The sensor samples this
address data on a rising edge of the sck clock
(mosi needs to be driven by the system on the
falling edge of the sck clock).
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
3. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 20 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON sensor
uses 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
4. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the data on
the requested address on the miso pin, most
significant bit first. The miso pin must be sampled
by the system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the
9−bit address is transferred, most significant bit
SPI − WRITE
ss_n
sck
t_sckss
t_sssck
tsck
ts _mos i
th_mosi
A8
A7
..
..
..
A1
A0
`1'
D
5
D14
..
..
..
..
D1
D0
mosi
miso
SPI − READ
ss_n
sck
t_sckss
t_sssck
tsck
ts_mosi
th_mosi
A8
A7
..
..
..
A1
A0
`0'
mosi
miso
ts _miso
th_miso
D
5
D14
..
..
..
..
D1
D0
Figure 20. SPI Read and Write Timing Diagram
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NOIP1SN5000A
Table 20. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
ns
(*)
tsck
sck clock period
100
tsssck
tsckss
ts_mosi
th_mosi
ts_miso
th_miso
tspi
ss_n low to sck rising edge
sck falling edge to ss_n high
Required setup time for mosi
Required hold time for mosi
Setup time for miso
tsck
tsck
ns
ns
20
ns
20
ns
tsck/2−10
tsck/2−20
2 x tsck
ns
Hold time for miso
ns
Minimal time between two consecutive SPI accesses (not shown in figure)
ns
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/f . See text for more information on SPI clock frequency restrictions.
SPI
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NOIP1SN5000A
IMAGE SENSOR TIMING AND READOUT
Global Shutter Mode
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure and is read as number of system
clock cycles.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 21.
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
Frame N
Frame N+1
Exposure State
Readout
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 21. Integration Control for (Pipelined) Global Shutter Mode (Master)
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NOIP1SN5000A
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 22.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Frame N+1
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Exposure State
trigger0
(No effect on falling edge)
Readout
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 22. Exposure Time Control in Triggered Shutter Mode (Master)
Notes:
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 23.
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
not used in this mode.
• The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
• If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
Triggered Global Shutter (Slave)
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
Frame N
Frame N+1
Exposure State
trigger0
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Readout
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Exposure Time Control in Global−Slave Mode
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NOIP1SN5000A
ADDITIONAL FEATURES
Multiple Window Readout
y1_end
The PYTHON 2000 and PYTHON 5000 sensor supports
multiple window readout, which means that only the
user−selected Regions Of Interest (ROI) are read out. This
allows limiting data output for every frame, which in turn
allows increasing the frame rate. In global shutter mode, up
to eight ROIs can be configured.
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 24 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
x1_end
ROI 0
Figure 25. Overlapping Multiple Window
Configuration
The sequencer analyses each line that needs to be read out
for multiple windows.
y-start
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-startꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢂx-end
Figure 24. Region of Interest Configuration
x_start_roi(i) vx_start_roi(j) AND
x_end_roi(i) vx_end_roi(j)
Where j > i
• x−start[7:0]
x−start defines the x−starting point of the desired window.
The sensor reads out 16 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 16 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 16 to find
the corresponding column in the pixel array.
• x−end[7:0]
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #15.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Figure 26 illustrates
a
practical example of
a
configuration with five windows. The current position of the
read pointer (ys) is indicated by a red line crossing the image
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 25.
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NOIP1SN5000A
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels are
scanned up to the ROI3 x−end position. From there, the
x−pointer jumps to the next window, which is ROI4 in this
illustration. When reaching ROI4’s x−end position, the read
pointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
ROI 2
ROI 4
ROI 3
ys
ROI 1
Notes:
ROI 0
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 26, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
Figure 26. Scanning the Image Array with Five
Windows
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome and NIR enhanced sensors
(P1−SN/FN and P3−SN/FN) and color sensors (P1−SE and
P3−SE).
Monochrome Sensors
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
• Each window can be activated separately. There is no
restriction on which window and how many of the 16
windows are active.
For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 27 shows which pixels are read and which
ones are skipped.
Figure 27. Subsampling Scheme for Monochrome and Color Sensors
Binning
NOTES:
Pixel binning is a technique in which different pixels
1. Register 194[13:12] needs to be configured to 0x0
for 2x2 pixel binning and to 0x1 for 2x1 binning.
Binning occurs only in x direction.
2. Binning in y-direction cannot be used in
combination with pipelined integration and
readout. The integration time and readout time
should be separated in time (do not coincide).
belonging to a rectangular bin are averaged in the analog
domain. Two−by−two pixel binning is available with the
monochrome and NIR enhanced image sensors (P1−SN/FN
and P3−SN/FN). This implies that two adjacent pixels are
averaged both in column and row. Binning is configurable
using a register setting. Pixel binning is not supported on
PYTHON 2000 and PYTHON 5000 (P1−SE and P3−SE)
color option and in Zero ROT mode.
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NOIP1SN5000A
Reverse Readout in Y−direction
channels. Using this function, one may for instance use the
device with sync+clock+8 data channels. Enabling the
channel multiplexing is done through register 32[5:4]. The
default value of 0 disables all channel multiplexing. Higher
values sets higher degree of channel multiplexing. The
channels that are used per degree of multiplexing are shown
in Table 5. The unused data channels are powered down and
will not send any data.
Reverse readout in y−direction can be done by asserting
reverse_y (reg 194[8]). The reference for y_start and y_stop
pointers is reversed.
Channel Multiplexing
The PYTHON 2000 and PYTHON 5000 image sensors
contains a function for channel multiplexing the output
Table 21. LVDS DATA OUTPUT CHANNELS USED WITH CHANNEL MULTIPLEXING
Register 32[5:4]
Data
Register 211
Data
# outputs
8 channels
4 channels
2 channels
1 channel
PYTHON 2000 / PYTHON 5000 − LVDS Channels
Ch 0
Ch 0
Ch 0
Ch 0
Ch 1
Ch 2
Ch 2
Ch 2
Ch 3
Ch 4
Ch 4
Ch 5
Ch 6
Ch 6
Ch 7
0
1
2
3
0x0E49
0x0E39
0x0E29
0x0E19
1. P1 supports 8, 4, 2, 1 LVDS outputs while P3 supports 4, 2, 1 LVDS outputs.
2. Use P3 bias uploads for P1 when operating in mux mode.
Table 22. BIAS UPLOADS FOR P1 AND P3
Bias Uploads
reg_mux_image_core_config1
Address
41
mux 8:8
mux 8:4
0x0854
0x0203
0x000C
0x48CB
0x53C4
0x4544
0x0085
0x0848
0x4411
0x3337
mux 8:2
0x0854
0x0203
0x000C
0x48CB
0x53C2
0x2322
0x0085
0x0828
0x4411
0x3337
mux 8:1
0x0854
0x0203
0x000C
0x48CB
0x53C1
0x1211
0x0085
0x0818
0x4411
0x3337
0x0854
0x0203
0x000C
0x48CB
0x53C8
0x8688
0x0085
0x0888
0x4411
0x3337
reg_mux_image_core_config2
reg_mux_image_core_config3
reg_bias_configuration
reg_bias_afe_bias
42
43
65
66
reg_bias_mux_bias
67
reg_bias_lvds_bias
68
reg_bias_adc_bias
69
reg_bias_imc_bias
70
reg_cp_configuration
72
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NOIP1SN5000A
Multiple Slope Integration
To increase the dynamic range of the sensor, a second
slope is applied in the dual slope mode (green curve). The
sensor has the same responsivity in the black as for a single
slope, but from ‘knee point 1’ on, the sensor is less
responsive to incoming light. The result is that the saturation
point is at a higher light power level.
To further increase the dynamic range, a third slope can be
applied, resulting in a second knee point.
Refer to section Global Shutter Mode on page 26 for
general notes applicable to the global shutter operation and
more particular to the use of the trigger0 pin.
‘Multiple Slope Integration’ is a method to increase the
dynamic range of the sensor. The PYTHON supports up to
three slopes.
Figure 28 shows the sensor response to light when the
sensor is used with one slope, two slopes, and three slopes.
The X−axis represents the light power; the Y−axis shows the
sensor output signal. The kneepoint of the multiple slope
curves are adjustable in both position and voltage level.
It is clear that when using only one slope (red curve), the
sensor has the same responsivity over the entire range, until
the output saturates at the point indicated with ‘single slope
saturation point’.
output
1023
‘kneepoint 2’
slope 3
slope 1
slope 2
‘kneepoint 1’
light
0
single slope
saturation point
triple slope
saturation point
dual slope
saturation point
Figure 28. Multiple Slope Operation
Kneepoint Configuration (Multiple Slope Reset Levels)
The kneepoint reset levels are configured by means of
DAC configurations in the image core. The dual slope
kneepoint is configured with the dac_ds configuration,
while the triple slope kneepoint is configured with the
dac_ts register setting. Both are located on address 41.
dual_slope_enableand triple_slope_enable and their values
are defined by the registers exposure_ds and exposure_ts.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 29 shows the frame timing for pipelined master
mode with dual and triple slope integration and
fr_mode = ‘0’ (fr_length representing the reset length).
In triggered master mode, the start of integration is
initiated by a rising edge on trigger0, while the falling edge
does not have any relevance. Exposure duration and
dual/triple slope points are defined by the registers.
Multiple Slope Integration in “Master Mode” (Pipelined
or Triggered)
In master mode, the time stamps for the double and triple
slope resets are configured in a similar way as the exposure
time. They are enabled through the registers
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NOIP1SN5000A
Figure 29. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)
Slave Mode
initiates the triple slope reset sequence. Rising edges on
In slave mode, the register settings for integration control
are ignored. The user has full control through the trigger0,
trigger1 and trigger2 pins. A falling edge on trigger1
initiates the dual slope reset while a falling edge on trigger2
trigger1 and trigger2 do not have any impact.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 30. Multiple Slope Operation in Slave Mode
Black Reference
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number, which is 0. Black reference data is
classified by a BL code.
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (162 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
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NOIP1SN5000A
Signal Path Gain
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
Analog Gain Stages
Referring to Table 23, several gain settings are available
in the analog data path to apply gain to the analog signal
before it is digitized.
The moment a gain reconfiguration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Table 23. SIGNAL PATH GAIN STAGES
Analog Gain Non−Zero
Address
204[12:0]
204[12:0]
204[12:0]
204[12:0]
204[12:0]
204[12:0]
204[12:0]
204[12:0]
Gain Setting
0x01E1
0x00A1
0x0021
0x0083
0x0085
0x0081
0x0086
0x0082
and Zero ROT
1
1.6
2
2.6
3.2
4
5.3
8
NOTE: The sensor performance specifications are tested at unity
gain. Analog gain above 2x affects noise performance.
All other gain settings shown in this table are tested for
sensor functionality.
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NOIP1SN5000A
Automatic Exposure Control
The exposure control mechanism has the shape of a
general feedback control system. Figure 31 shows the high
level block diagram of the exposure control loop.
AEC
Statistics
AEC
Filter
AEC
Enforcer
Requested Illumination Level
(Target)
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 31. Automatic Exposure Control Loop
Three main blocks can be distinguished:
calculated illumination and the target illumination the
statistics block requests a relative gain change.
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 24.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
The automatic exposure control loop is enabled by
asserting the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is not
supported in conjunction with the AEC.
AEC Statistics Block
The statistics block calculates the average illumination of
the current image. Based on the difference between the
Table 24. AEC SAMPLE SELECTION
Register
Name
Description
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined by roi_aec
253−255
roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is asserted.
Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this window at least
overlaps with one or more active windows.
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AEC Filter Block
Target Illumination
The filter block low−pass filters the gain change requests
received from the statistics block.
The target illumination value is configured by means of
register desired_intensity as shown in Table 25.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 25. AEC TARGET ILLUMINATION
CONFIGURATION
AEC Enforcer Block
Register
Name
Description
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
161[9:0]
desired_in-
tensity
Target intensity value, on 10−bit scale.
For 8−bit mode, target value is configured
on desired_intensity[9:2]
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 26 for color scale factors. For
mono sensors, configure these factors to their default value.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
Table 26. COLOR SCALE FACTORS
Register
162[9:0]
163[9:0]
Name
Description
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
red_scale_factor
green1_scale_factor
Red scale factor for AEC statistics
Green1 scale factor for AEC
statistics
164[9:0]
165[9:0]
green2_scale_factor
blue_scale_factor
Green2 scale factor for AEC
statistics
• Analog Gain
The sensor has two analog gain settings. Typically the
AEC shall only regulate the first stage.
Blue scale factor for AEC statistics
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
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NOIP1SN5000A
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 27 lists the relevant
registers.
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Table 27. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
Register
Name
Description
Exposure Control Status Registers
168[15:0]
min_exposure
Lower bound for the integration time
applied by the AEC
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 28 reflecting the
AEC and Sequencer Status registers.
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
169[3:2]
min_afe_gain
Lower bound for the second stage
analog amplifier.
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
Table 28. EXPOSURE CONTROL STATUS REGISTERS
169[15:4]
min_digital_gain
Lower bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
Register
Name
Description
AEC Status Registers
184[15:0]
186[9:0]
total_pixels
Total number of pixels taken into account
for the AEC statistics.
170[15:0]
171[1:0]
max_exposure
max_mux_gain
Upper bound for the integration time
applied by the AEC
average
Calculated average illumination
level for the current frame.
Upper bound for the first stage ana-
log amplifier.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at the
frame end.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
188[1:0]
188[3:2]
188[15:4]
mux_gain
afe_gain
AEC calculated analog gain
0x1 = 2x
st
(1 stage)
Note: this parameter is updated at the
frame end.
171[3:2]
max_afe_gain
Upper bound for the second stage
analog amplifier
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
AEC calculated analog gain
st
(2 stage)
Note: this parameter is updated at the
frame end.
171[15:4]
max_digital_
gain
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at the
frame end.
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NOIP1SN5000A
Table 28. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
Sequencer Status Registers
242[15:0]
243[15:0]
mult_timer
mult_timer for current frame
Note: this parameter is updated once it
takes effect on the image.
reset_length
Image array reset length for the
current frame.
Note: this parameter is updated once it
takes effect on the image.
244[15:0]
245[15:0]
exposure
Exposure for the current frame.
Note: this parameter is updated once it
takes effect on the image.
exposure_ds
Dual slope exposure for the current
frame. Note this parameter is not con-
trolled by the AEC.
Note: this parameter is updated once it
takes effect on the image.
246[15:0]
exposure_ts
Triple slope exposure for the
current frame. Note this parameter is not
controlled by the AEC.
Note: this parameter is updated once it
takes effect on the image.
st
247[4:0]
247[12:5]
248[11:0]
mux_gainsw
afe_gain
1
stage analog gain for the current
frame.
Note: this parameter is updated once it
takes effect on the image.
st
2
stage analog gain for the current
frame.
Note: this parameter is updated once it
takes effect on the image.
db_gain
Digital gain configuration for the current
frame (5.7 unsigned
format).
Note: this parameter is updated once it
takes effect on the image.
248[12]
248[13]
dual_slope
triple_slope
Dual slope configuration for the
current frame
Note 1: this parameter is updated once it
takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
Triple slope configuration for the current
frame.
Note 1: this parameter is updated once it
takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
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NOIP1SN5000A
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Table 29. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Corrupted
Frame
Blanked Out
Frame
Configuration
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Configurable
Configurable with blank_subsampling_ss register.
Disabling: Yes
binning
No
No
Configurable
Configurable with blank_subsampling_ss register
Frame Timing
black_lines
Exposure Control
mult_timer
fr_length
No
No
No
No
No
No
No
Latency is 1 frame
Latency is 1 frame
Latency is 1 frame
exposure
Gain
mux_gainsw
afe_gain
No
No
No
No
No
No
Latency configurable by means of gain_lat_comp register
Latency configurable by means of gain_lat_comp register.
Latency configurable by means of gain_lat_comp register.
db_gain
Window/ROI
roi_active
See Note
See Note
No
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
Black Calibration
black_samples
No
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
CRC Calculation
crc_seed
Sync Channel
bl_0
See Note
No
No
No
Manual blackcal_offset updates are instantly active.
Impacts the transmitted CRC
No
No
No
No
No
No
No
No
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
img_0
crc_0
tr_0
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NOIP1SN5000A
Temperature Sensor
Calibration using one temperature point
The PYTHON has an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8−bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of 2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of 5°C.
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
T = R (Nread − Ncalib) + Tcalib
J
T = junction die temperature
J
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Note that any process variation will result in an offset in
the bit count and that offset will remain within 5°C over the
temperature range of 0°C and 85°C. Tsensor output digital
code can be read out through the SPI interface.
Ncalib = Tsensor output reading at Tcalib
Output of the temperature sensor to the SPI:
tempd_reg_temp<7:0>: This is the 8−bit N count readout
proportional to temperature.
Monitor Pins
The internal sequencer has two monitor outputs (monitor0
and monitor1) that can be used to communicate the internal
states from the sequencer. A three−bit register configures the
assignment of the pins as shown in Table 30.
Input from the SPI:
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
Table 30. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]
192 [13:11]
monitor pin
Description
0x0
monitor0
monitor1
‘0’
‘0’
0x1
0x2
0x3
0x4
0x5
0x6
0x7
monitor0
monitor1
Integration Time
ROT Indication (‘1’ during ROT, ‘0’ outside)
monitor0
monitor1
Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)
monitor0
monitor1
Start of x−Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)
monitor0
monitor1
Frame Start Indication
Start of ROT Indication
monitor0
monitor1
First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication
monitor0
monitor1
ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X−Readout Indication
monitor0
monitor1
Start of X−readout Indication for Black Lines
Start of X−readout Indication for Image Lines
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NOIP1SN5000A
DATA OUTPUT FORMAT
The PYTHON 2000 and PYTHON 5000 image sensors
The frame format in 10−bit mode is explained by example
of the readout of two (overlapping) windows as shown in
Figure 32(a).
are available in two LVDS output configuration, P1 and P3.
The P1 configuration utilizes eight LVDS output channels
together with an LVDS clock output and an LVDS
synchronization output channel. The P3 configuration
consists of four LVDS output channels together with an
LVDS clock output and an LVDS synchronization output
channel.
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 32 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
P1,P3−SN/SE/FN: Interface Version
LVDS Output Channels
The image data output occurs through eight LVDS data
channels where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
Referring to Table 21, the eight data channels on the P1
option are used to output the image data only, while on the
P3 option, four data channel channels are utilized. The sync
channel transmits information about the data sent over these
data channels (includes codes indicating black pixels,
normal pixels, and CRC codes).
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
8−bit / 10−bit Mode
The sensor can be used in 8−bit or 10−bit mode.
In 10−bit mode, the words on data and sync channel have
a 10−bit length. The output data rate is 720 Mbps.
In 8−bit mode, the words on data and sync channel have
an 8−bit length, the output data rate is 576 Mbps.
Note that the 8−bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is not
supported to operate the sensor in 8−bit mode at a higher
clock frequency to achieve higher frame rates. The P1 option
supports 10−bit/8−bit in ZROT/NZROT mode, while the P3
option supports 10−bit NZROT mode only.
NOTES: In Figure 32, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
For additional information on the
synchronization codes, please refer to PYTHON
Image Sensor Family Developer’s Guide
AND9362/D.
Frame Format
The frame format in 8−bit mode is identical to the 10−bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.
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NOIP1SN5000A
y1_end
y0_end
y1_start
ROI 1
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Reset
N
Reset
N+1
FOT
FOT
FOT
FOT
Exposure Time N
Exposure Time N+1
Readout Frame N-1
Readout Frame N
Readout
Handling
B
L
ROI
1
B
L
ROI
1
FOT
ROI 0
ROI 0
FS0
FS1
FE1
FS0
FS1
FE1
(b)
Figure 32. P1&P3−SN/SE/FN: Frame Sync Codes
Figure 33 shows the detail of a black line readout during global or full−frame readout.
Sequencer
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
Internal State
data channels
sync channel
Training
TR
Training
TR
data channels
sync channel
LS
BL
BL
BL
BL
BL
BL LE
CRC
timeslot
0
timeslot
1
timeslot
157
timeslot
158
timeslot
159
CRC
timeslot
Figure 33. P1&P3−SN/SE/FN: Time Line for Black Line Readout
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NOIP1SN5000A
Figure 34 shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
data channels
sync channel
Training
Training
TR
data channels
sync channel
TR
FS
ID
IMG IMG
IMG
IMG IMG IMG LE
ID
CRC
timeslot
Xstart
timeslot
Xstart + 1
timeslot
Xend - 2
timeslot
Xend - 1
timeslot
Xend
CRC
timeslot
Figure 34. P1&P3−SN/SE/FN: Time Line for Single Window Readout (at the start of a frame)
Figure 35 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
line Ys+1
ROT
line Ye
data channels
sync channel
Training
TR
Training
TR
data channels
sync channel
LS
IMG IMG
LS
IDN
IMG
IMG LE
IDN
CRC
IDM
IMG
timeslot
XstartM
timeslot
XstartN
timeslot
XendN
Figure 35. P1&P3−SN/SE/FN: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization for 10−bit Mode
active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 31 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10−bit mode. If more than one window is
Table 31. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default Value
Description
9:7
9:7
9:7
9:7
6:0
N/A
N/A
0x5
0x6
Frame start (FS) indication
Frame end (FE) indication
Line start (LS) indication
Line end (LE) indication
N/A
0x1
N/A
0x2
117[6:0]
0x2A
These bits indicate that the received sync word is a frame synchronization code. The value is pro-
grammable by a register setting
Window Identification
number, ranging from 0 to 15, indicating the active window.
Frame synchronization codes are always followed by a
4−bit window identification (bits 3:0). This is an integer
If more than one window is active for the current cycle, the
highest window ID is transmitted.
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Data Classification Codes
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 32.
Table 32. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE
Sync Word Bit
Position
Register Ad- Default Val-
dress
ue
Description
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
9:0
9:0
119 [9:0]
125 [9:0]
126 [9:0]
0x035
0x059
0x3A6
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).
CRC value. The data on the data output channels is the CRC code of the finished image data line.
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Frame Synchronization in 8−bit Mode
and not sent out. Table 32 shows the structure of the frame
The frame synchronization words are configured using
the same registers as in 10−bit mode. The two least
significant bits of these configuration registers are ignored
synchronization code, together with the default value, as
specified in SPI registers. The same restriction for
overlapping windows applies in 8−bit mode.
Table 33. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE
Sync Word Bit
Position
Register Ad-
dress
Default Val-
ue
Description
7:5
7:5
7:5
7:5
4:0
N/A
N/A
0x5
0x6
Frame start (FS) indication
Frame end (FE) indication
Line start (LS) indication
Line end (LE) indication
N/A
0x1
N/A
0x2
117 [6:2]
0x0A
These bits indicate that the received sync word is a frame synchronization code.
The value is programmable by a register setting.
Window Identification
Similar to 10−bit operation mode, the frame
synchronization codes are followed by window
identification. The window ID is located in bits 5:2 (all other
bit positions are ‘0’). The same restriction for overlapping
windows applies in 8−bit mode.
Data Classification Codes
BL, IMG, CRC, and TR codes are defined by the same
registers as in 10−bit mode. Bits 9:2 of the respective
configuration registers are used as classification code with
default values shown in Table 34.
a
Table 34. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE
Sync Word Bit
Position
Register Ad-
dress
Default Val-
ue
Description
7:0
118 [9:2]
0x05
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
7:0
7:0
7:0
119 [9:2]
125 [9:2]
126 [9:2]
0x0D
0x16
0xE9
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).
CRC value. The data on the data output channels is the CRC code of the finished image data line.
Training Pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
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43
NOIP1SN5000A
Training Patterns on Data Channels
In 10−bit mode, during idle periods, the data channels
transmit training patterns, indicated on the sync channel by
a TR code. These training patterns are configurable
independent of the training code on the sync channel as
shown in Table 35.
Table 35. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE
Sync Word Bit
Position
Register Ad-
dress
Default
Value
Description
[9:0]
116 [9:0]
0x3A6
Data channel training pattern. The data output channels send out the training pattern, which can be
programmed by a register setting. The default value of the training pattern is 0x3A6, which is identical
to the training pattern indication code on the sync channel.
In 8−bit mode, the training pattern for the data channels is
defined by the same register as in 10−bit mode, where the
lower two bits are omitted; see Table 36.
Table 36. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE
Data Word Bit
Position
Register Ad-
dress
Default
Value
Description
Data Channel Training Pattern (Training pattern).
[7:0]
116 [9:2]
0xE9
Cyclic Redundancy Code
at the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;
when ‘1’ it is seeded with all−‘1’.
In 8−bit mode, the polynomial is x + x + x + x + 1.
The CRC seed is configured by means of the crc_seed
register.
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
8
6
3
2
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
The polynomial in 10−bit operation mode is
10
9
6
3
2
x
+ x + x + x + x + x + 1. The CRC encoder is seeded
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44
NOIP1SN5000A
Data Order for P1&P3−SN/SE/FN
Figure 36 indicates how the kernels are organized. The first
kernel (kernel [0, 0]) is located in the bottom left corner
(front view on top of the package). The data order of this
image data on the data output channels depends on the
subsampling mode.
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is
sixteen pixels in x−direction by one pixel in y−direction. The
data order in 8−bit mode is identical to the 10−bit mode.
kernel
(161,2047)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
13 14 15
Figure 36. Kernel Organization in Pixel Array − Top View
Figure 37 shows how a kernel is read out over the eight
• P1&P3−SN/SE/FN: Subsampling Disabled
output channels. For even positioned kernels, the kernels are
read out ascending, while for odd positioned kernels the data
order is reversed (descending).
♦ 8 LVDS Output Channels (P1 only)
The image data is read out in kernels of 16 pixels in
x−direction by one pixel in y−direction. One data channel
output delivers two pixel values of one kernel sequentially.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
2
3
4
11 12 13 14 15
pixel # (even kernel)
15 14 13 12 11
4
3
2
1
0
pixel # (odd kernel)
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 37. P1−SN/SE/FN: 8 LVDS Data Output Order when Subsampling is Disabled
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45
NOIP1SN5000A
♦ 4 LVDS Output Channels
Figure 38 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
read out ascending but in pair of even and odd pixels, while
for odd positioned kernels, the data order is reversed
(descending − in pair of even and odd pixels).
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel # (even kernel)
0
2
1
3
4
6
9
5
7
8
8
7
10
5
9
6
11 12 14 13 15
pixel # (odd kernel)
15 13 14 12 11
10
4
3
1
2
0
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 38. P1,P3−SN/SE/FN: 4 LVDS Data Output Order when Subsampling is Disabled
♦ 2 LVDS Output Channels
the kernels are read out in an ascending order but in sets of
four even and four odd pixels, while for odd positioned
kernels the data order is reversed (descending and in sets of
four odd and four even pixels).
Figure 39 shows how a kernel is read out over 2 output
channels. Each group of four adjacent channels is
multiplexed on to one channel. For even positioned kernels,
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel # (even kernel)
0
2
4
6
9
1
3
5
7
8
8
7
10 12 14
9
6
11 13 15
pixel # (odd kernel)
15 13 11
14 12 10
5
3
1
4
2
0
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 39. P1,P3−SN/SE/FN: 2 LVDS Data Output Order when Subsampling is Disabled
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46
NOIP1SN5000A
♦ 1 LVDS Output Channel
out ascending but in sets of 8 even and 8 odd pixels, while
for odd positioned kernels the data order is reversed
(descending − in sets of 8 odd and 8 even pixels).
Figure 40 shows how a kernel is read out over 1 output
channel. Eight adjacent channels are multiplexed into one
channel. For even positioned kernels, the kernels are read
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel # (even kernel)
0
2
4
6
9
8
7
10 12 14
1
3
5
7
8
9
6
11 13 15
pixel # (odd kernel)
15 13 11
5
3
1
14 12 10
4
2
0
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 40. P1,P3−SN/SE/FN: 1 LVDS Data Output Order when Subsampling is Disabled
Only the pixels at the even pixel positions inside that kernel
are read out.
• P1&P3−SN/FN: Subsampling on Monochrome Sensor
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
neighboring kernels are combined to a single kernel of
32 pixels in the x−direction and one pixel in the y−direction.
♦ 8 LVDS Output Channels (P1 only)
Figure 41 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
30
2
28
4
26
6
24
8
22 10 20 12 18 14 16
pixel #
Figure 41. P1−SN/FN: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor
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47
NOIP1SN5000A
♦ 4 LVDS Output Channels
even/odd kernel numbers, as opposed to the
Figure 42 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
2
30
28
4
6
26
24
8
10
22
20
12
14
18
16
pixel #
Figure 42. P1,P3−SN/FN: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor
♦ 2 LVDS Output Channels
even/odd kernel numbers, as opposed to the
Figure 43 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
2
4
6
30
28
26
24
8
10
12
14
22
20
18
16
pixel #
Figure 43. P1,P3−SN/FN: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor
♦ 1 LVDS Output Channel
even/odd kernel numbers, as opposed to the
Figure 44 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
2
4
6
8
10
12
14
30
28
26
24
22
20
18
16
pixel #
Figure 44. P1,P3−SN/FN: Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor
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48
NOIP1SN5000A
kernels are combined to a single kernel of 16 pixels in the
x−direction and one pixel in the y−direction. Only the pixels
0, 1, 4, 5, 8, 9, … 28, 29 are read out.
• P1&P3−SN/FN: Binning on Monochrome Sensor
The output order in binning mode is identical to the
subsampled mode.
♦ 8 LVDS Output Channels (P1 only)
• P1&P3−SN/FN: Subsampling on Color Sensor
Figure 45 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernel N−2
kernel N−1
kernel N
kernel N+1
0
29
1
28
4
25
5
24
8
21
9
20
12
17
13
16
pixel #
Figure 45. P1−SE: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 4 LVDS Output Channels
even/odd kernel numbers, as opposed to the
Figure 46 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
29
28
4
5
25
24
8
9
21
20
12
13
17
16
pixel #
Figure 46. P1,P3−SE: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 2 LVDS Output Channels
even/odd kernel numbers, as opposed to the
Figure 47 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
4
5
29
28
25
24
8
9
12
13
21
20
17
16
pixel #
Figure 47. P1,P3−SE: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor
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49
NOIP1SN5000A
♦ 1 LVDS Output Channel
even/odd kernel numbers, as opposed to the
Figure 48 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
‘no−subsampling’ readout described in previous section.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
4
5
8
9
12
13
29
28
25
24
21
20
17
16
pixel #
Figure 48. P1,P3−SE: Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor
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50
NOIP1SN5000A
REGISTER MAP
The table below represents the register map for the
NOIP1xx5000A part. Deviating default values for the
NOIP1xx2000A sensor are mentioned between brackets
(“[ ]”).
Table 37. REGISTER MAP
Address
Offset
Default
(Hex)
Address
Bit Field
Register Name
Default
Description
Type
Status
Status
Chip ID [Block Offset: 0]
0
0
chip_id
0x5032
0x5032
20530
20530
Chip ID
Chip ID
Reserved
[15:0]
id
1
1
reserved
0x0001
[0x0101]
1
[257]
[3:0]
[9:8]
reserved
0x1
1
Reserved
resolution
0x0 [0x1]
0 [1]
Sensor Resolution
‘0’: PYTHON 5000
‘1’: PYTHON 2000
[11:10]
[0]
reserved
0x0
0
0
0
Reserved
2
2
chip_configuration
color
0x0000
0x0
Chip General Configuration
RW
Colour/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[3:2]
glob_config
reserved
0x0
0
0
Sensor pinout configuration
Reserved
[15:4]
0x000
Reset Generator [Block Offset: 8]
0
8
soft_reset_pll
pll_soft_reset
0x0099
0x9
153
9
PLL Soft Reset Configuration
RW
[3:0]
[7:4]
PLL Reset
0x9: Soft Reset State
others: Operational
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
1
2
9
soft_reset_cgen
cgen_soft_reset
0x0009
0x9
9
9
Clock Generator Soft Reset
RW
RW
[3:0]
Clock Generator Reset
0x9: Soft Reset State
others: Operational
10
soft_reset_analog
mux_soft_reset
0x0999
0x9
2457
9
Analog Block Soft Reset
[3:0]
[7:4]
Column MUX Reset
0x9: Soft Reset State
others: Operational
afe_soft_reset
ser_soft_reset
0x9
0x9
9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
Serializer Reset
0x9: Soft Reset State
others: Operational
PLL [Block Offset: 16]
0 16
power_down
pwd_n
0x0004
0x0
4
0
PLL Configuration
RW
[0]
[1]
[2]
PLL Power Down
‘0’: Power Down,
‘1’: Operational
enable
bypass
0x0
0x1
0
1
PLL Enable
‘0’: disabled,
‘1’: enabled
PLL Bypass
‘0’: PLL Active,
‘1’: PLL Bypassed
1
17
reserved
reserved
0x2113
0x13
8467
19
Reserved
Reserved
RW
[7:0]
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51
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
[12:8]
Register Name
reserved
(Hex)
Default
Description
Type
0x1
1
1
Reserved
Reserved
[14:13]
reserved
0x1
I/O [Block Offset: 20]
20
0
config1
0x0000
0x0
0
0
0
0
IO Configuration
RW
[0]
clock_in_pwd_n
reserved
Power down Clock Input
Reserved
[9:8]
[10]
0x0
reserved
0x0
Reserved
PLL Lock Detector [Block Offset: 24]
0
24
pll_lock
lock
0x0000
0x0
0
PLL Lock Indication
PLL Lock Indication
Reserved
Status
RW
[0]
0
2
26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x2280
0x80
8832
128
2
[7:0]
[10:8]
[14:12]
Reserved
0x2
Reserved
0x2
2
Reserved
3
27
0x3D2D
0x2D
0x3D
15661
45
Reserved
RW
RW
[7:0]
Reserved
[15:8]
61
Reserved
Clock Generator [Block Offset: 32]
32
0
config0
0x0004
0x0
4
0
Clock Generator Configuration
[0]
[1]
[2]
[3]
enable_analog
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
enable_log
select_pll
adc_mode
0x0
0x1
0x0
0
1
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
Set operation mode of CGEN block
‘0’: divide by 5 mode (10−bit mode),
‘1’: divide by 4 mode (8−bit mode)
[5:4]
[11:8]
[14:12]
mux
0x0
0x0
0x0
0
0
0
Multiplex Mode
Reserved
reserved
reserved
Reserved
General Logic [Block Offset: 34]
0
34
config0
enable
0x0000
0x0
0
0
Clock Generator Configuration
RW
[0]
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
0
1
38
39
reserved
reserved
reserved
reserved
0x0000
0x0000
0x0000
0x0000
0
0
0
0
Reserved
Reserved
Reserved
Reserved
RW
RW
[15:0]
[15:0]
Image Core [Block Offset: 40]
40
0
image_core_config0
imc_pwd_n
0x0000
0x0
0
0
Image Core Configuration
RW
[0]
Image Core Power Down
‘0’: powered down,
‘1’: powered up
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52
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
1
41
image_core_config1
dac_ds
0x0B5A
0xA
0x5
2906
10
5
Image Core Configuration
Double Slope Reset Level
Triple Slope Reset Level
Reserved
RW
[3:0]
[7:4]
[10:8]
[12:11]
[13]
dac_ts
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x3
3
0x1
1
Reserved
0x0
0
Reserved
[14]
0x0
0
Reserved
[15]
0x0
0
Reserved
2
42
0x0001
0x1
1
Reserved
RW
[0]
[1]
1
Reserved
0x0
0
Reserved
[6:4]
[10:8]
[15:12]
0x0
0
Reserved
0x0
0
Reserved
0x0
0
Reserved
3
43
0x0000
0x0
0
Reserved
RW
[0]
[1]
0
Reserved
0x0
0
Reserved
[2]
0x0
0
Reserved
[3]
0x0
0
Reserved
[6:4]
[7]
0x0
0
Reserved
0x0
0
Reserved
[15:8]
0x0
0
Reserved
AFE [Block Offset: 48]
48
0
power_down
pwd_n
0x0000
0x0
0
0
AFE Configuration
RW
[0]
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
Bias [Block Offset: 64]
0
64
power_down
pwd_n
0x0000
0x0
0
0
Bias Power Down Configuration
RW
RW
[0]
[0]
Power down bandgap
‘0’: powered down,
‘1’: powered up
1
65
configuration
extres
0x888B
0x1
34955
1
Bias Configuration
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
[3:1]
[7:4]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x5
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x8
8
[11:8]
[15:12]
0x8
8
0x8
8
2
66
0x53C8
0x8
21448
8
RW
[3:0]
[7:4]
0xC
12
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53
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
reserved
(Hex)
Default
Description
Type
[14:8]
0x53
83
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
67
reserved
reserved
reserved
reserved
reserved
lvds_bias
lvds_ibias
lvds_iref
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x8888
0x8
34952
RW
[3:0]
[7:4]
8
0x8
8
[11:8]
[15:12]
0x8
8
0x8
8
4
5
68
69
0x0088
0x8
136
LVDS Bias Configuration
LVDS Ibias
LVDS Iref
RW
RW
[3:0]
[7:4]
8
0x8
8
0x0888
0x8
2184
Reserved
[3:0]
[7:4]
8
Reserved
0x8
8
Reserved
[11:8]
0x8
8
Reserved
6
70
0x8888
0x8
34952
Reserved
RW
[3:0]
[7:4]
8
Reserved
0x8
8
Reserved
[11:8]
[15:12]
0x8
8
Reserved
0x8
8
Reserved
7
71
0x8888
0x8888
34952
34952
Reserved
RW
RW
[15:0]
Reserved
Charge Pump [Block Offset: 72]
72
0
configuration
trans_pwd_n
0x2220
0x0
8736
0
Charge Pump Configuration
[0]
[1]
[2]
PD Trans Charge Pump Enable
‘0’: disabled,
‘1’: enabled
resfd_calib_pwd_n
sel_sample_pwd_n
0x0
0x0
0
0
FD Charge Pump Enable
‘0’: disabled,
‘1’: enabled
Select/Sample Charge Pump Enable
‘0’: disabled
‘1’: enabled
[6:4]
[10:8]
[14:12]
reserved
reserved
reserved
0x2
0x2
0x2
2
2
2
Reserved
Reserved
Reserved
Charge Pump [Block Offset: 80]
0 80
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0000
0x0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
[1:0]
[3:2]
[5:4]
[7:6]
[9:8]
0
0x0
0
0x0
0
0x0
0
0x0
0
1
81
0x8881
0x8881
34945
34945
RW
RW
[15:0]
Temperature Sensor [Block Offset: 96]
96
0
enable
enable
0x0000
0x0
0
0
Temperature Sensor Configuration
[0]
Temperature Diode Enable
‘0’: disabled,
‘1’: enabled
www.onsemi.com
54
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
[1]
Register Name
reserved
(Hex)
Default
Description
Type
0x0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
[2]
reserved
reserved
reserved
reserved
offset
0x0
[3]
0x0
[4]
0x0
[5]
0x0
[13:8]
0x0
Temperature Offset (signed)
Temperature Sensor Status
Temperature Readout
1
97
temp
0x0000
0x00
Status
[7:0]
temp
Temperature Sensor [Block Offset: 104]
0
104
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
[15:0]
1
105
0x0000
0x0
[1:0]
[6:2]
[7]
0x0
0x0
[9:8]
[14:10]
[15]
0x0
0x0
0x0
2
3
4
5
6
7
106
107
108
109
110
111
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Status
Status
Status
Status
Status
Status
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Serializers / LVDS / IO [Block Offset: 112]
0
112
power_down
0x0000
0x0
0
0
LVDS Power Down Configuration
RW
[0]
[1]
[2]
clock_out_pwd_n
Power down for Clock Output.
‘0’: powered down,
‘1’: powered up
sync_pwd_n
data_pwd_n
0x0
0x0
0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
Sync Words [Block Offset: 116]
4
116
trainingpattern
trainingpattern
0x03A6
0x3A6
934
934
Data Formating − Training Pattern
RW
RW
[9:0]
[6:0]
Training pattern sent on Data channels during
idle mode. This data is used to perform word
alignment on the LVDS data channels.
5
117
sync_code0
0x002A
0x02A
42
42
LVDS Power Down Configuration
frame_sync_0
Frame Sync Code LSBs − Even kernels
www.onsemi.com
55
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
sync_code1
bl_0
(Hex)
0x0015
0x015
Default
21
Description
Type
RW
6
118
Data Formating − BL Indication
[9:0]
21
Black Pixel Identification Sync Code − Even
kernels
7
8
119
120
sync_code2
img_0
0x0035
0x035
53
53
Data Formating − IMG Indication
RW
RW
[9:0]
[9:0]
Valid Pixel Identification Sync Code − Even
kernels
sync_code3
ref_0
0x0025
0x025
37
37
Data Formating − IMG Indication
Reference Pixel Identification Sync Code −
Even kernels
9
121
122
sync_code4
frame_sync_1
sync_code5
bl_1
0x002A
0x02A
0x0015
0x015
42
42
21
21
LVDS Power Down Configuration
Frame Sync Code LSBs − Odd kernels
Data Formating − BL Indication
RW
RW
[6:0]
[9:0]
10
Black Pixel Identification Sync Code − Odd
kernels
11
12
123
124
sync_code6
img_1
0x0035
0x035
53
53
Data Formating − IMG Indication
RW
RW
[9:0]
[9:0]
Valid Pixel Identification Sync Code − Odd
kernels
sync_code7
ref_1
0x0025
0x025
37
37
Data Formating − IMG Indication
Reference Pixel Identification Sync Code −
Odd kernels
13
14
15
125
126
127
sync_code8
crc
0x0059
0x059
89
Data Formating − CRC Indication
CRC Value Identification Sync Code
Data Formating − TR Indication
Training Value Identification Sync Code
Reserved
RW
RW
RW
[9:0]
[9:0]
[9:0]
89
sync_code9
tr
0x03A6
0x3A6
0x02AA
0x2AA
934
934
682
682
reserved
reserved
Reserved
Data Block [Block Offset: 128]
0 128
blackcal
0x4008
0x08
0x0
16392
Black Calibration Configuration
Desired black level at output
RW
[7:0]
black_offset
black_samples
8
0
[10:8]
Black pixels taken into account for black cali-
bration.
Total samples = 2**black_samples
[14:11]
[15]
reserved
crc_seed
0x8
0x0
8
0
Reserved
CRC Seed
‘0’: All−0
‘1’: All−1
1
129
general_configuration
auto_blackcal_enable
blackcal_offset
0x0001
0x1
1
1
0
0
Black Calibration and Data Formating
Configuration
RW
[0]
Automatic blackcalibration is enabled when 1,
bypassed when 0
[9:1]
[10]
0x00
0x0
Black Calibration offset used when au-
to_black_cal_en = ‘0’.
blackcal_offset_dec
blackcal_offset is added when 0, subtracted
when 1
[11]
[12]
[13]
reserved
reserved
8bit_mode
0x0
0x0
0x0
0
0
0
Reserved
Reserved
Shifts window ID indications by 4 cycles.
‘0’: 10 bit mode,
‘1’: 8 bit mode
[14]
ref_mode
0x0
0
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding data
channel
www.onsemi.com
56
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
[15]
ref_bcal_enable
0x0
0
Enable black calibration on reference lines
‘0’: Disabled
‘1’: Enabled
2
130
reserved
0x000F
0x1
15
1
Reserved
RW
[0]
[1]
[2]
[3]
[4]
[8]
reserved
Reserved
reserved
0x1
1
Reserved
reserved
0x1
1
Reserved
reserved
0x1
1
Reserved
reserved
0x0
0
Reserved
reserved
0x0
0
Reserved
8
136
blackcal_error0
blackcal_error[15:0]
0x0000
0x0000
0
Black Calibration Status
Status
[15:0]
0
Black Calibration Error. This flag is set when
not enough black samples are available.
Black Calibration shall not be valid. Channels
0−16
9
137
138
139
140
141
144
reserved
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0x0000
0x0
0
Reserved
Status
Status
Status
RW
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
reserved
0
Reserved
10
11
12
13
16
reserved
0
Reserved
reserved
0
Reserved
reserved
0
Reserved
reserved
0
Reserved
reserved
0
Reserved
reserved
0
Reserved
reserved
65535
Reserved
RW
reserved
65535
Reserved
test_configuration
testpattern_en
inc_testpattern
0
0
0
Data Formating Test Configuration
Insert synthesized testpattern when ‘1’
RW
[0]
[1]
0x0
Incrementing testpattern when ‘1’, constant
testpattern when ‘0’
[2]
[3]
prbs_en
0x0
0x0
0
0
Insert PRBS when ‘1’
frame_testpattern
Frame test patterns when ‘1’, unframed test-
patterns when ‘0’
[4]
reserved
0x0
0
Reserved
17
18
145
146
reserved
0x0000
0
Reserved
RW
RW
[15:0]
[7:0]
reserved
0
Reserved
test_configuration0
testpattern0_lsb
0x0100
0x00
256
0
Data Formating Test Configuration
Testpattern used on datapath #0 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
[7:0]
testpattern1_lsb
0x01
1
Testpattern used on datapath #1 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
19
147
test_configuration1
testpattern2_lsb
0x0302
0x02
770
2
Data Formating Test Configuration
RW
Testpattern used on datapath #2 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
www.onsemi.com
57
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
[15:8]
testpattern3_lsb
0x03
3
Testpattern used on datapath #3 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
20
148
test_configuration2
testpattern4_lsb
0x0504
0x04
1284
4
Data Formating Test Configuration
RW
[7:0]
Testpattern used on datapath #4 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern5_lsb
0x05
5
Testpattern used on datapath #5 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
21
149
test_configuration3
testpattern6_lsb
0x0706
0x06
1798
6
Data Formating Test Configuration
RW
[7:0]
Testpattern used on datapath #6 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern7_lsb
0x07
7
Testpattern used on datapath #7 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
22
150
test_configuration16
testpattern0_msb
testpattern1_msb
testpattern2_msb
testpattern3_msb
testpattern4_msb
testpattern5_msb
testpattern6_msb
testpattern7_msb
reserved
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Formating Test Configuration
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Testpattern used when testpattern_en = ‘1’
Reserved
RW
[1:0]
[3:2]
0x0
[5:4]
0x0
[7:6]
0x0
[9:8]
0x0
[11:10]
[13:12]
[15:14]
0x0
0x0
0x0
26
27
154
155
0x0000
0x0000
0x0000
0x0000
RW
RW
[15:0]
[15:0]
reserved
Reserved
reserved
Reserved
reserved
Reserved
AEC [Block Offset: 160]
0
160
configuration
enable
0x0010
0x0
16
0
AEC Configuration
RW
[0]
[1]
[2]
[3]
AEC Enable
restart_filter
freeze
0x0
0
Restart AEC filter
0x0
0
Freeze AEC filter and enforcer gains
pixel_valid
0x0
0
Use every pixel from channel when 0, every
4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0
1
2
161
162
intensity
0x60B8
0xB8
24760
184
24
AEC Configuration
Target average intensity
Reserved
RW
RW
[9:0]
desired_intensity
reserved
[15:10]
0x018
0x0080
0x80
red_scale_factor
red_scale_factor
128
128
Red Scale Factor
[9:0]
Red Scale Factor
3.7 unsigned
www.onsemi.com
58
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
green1_scale_factor
green1_scale_factor
(Hex)
0x0080
0x80
Default
128
Description
Green1 Scale Factor
Type
RW
3
163
[9:0]
128
Green1 Scale Factor
3.7 unsigned
4
5
164
165
green2_scale_factor
green2_scale_factor
0x0080
0x80
128
128
Green2 Scale Factor
RW
RW
[9:0]
[9:0]
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
blue_scale_factor
0x0080
0x80
128
128
Blue Scale Factor
Blue Scale Factor
3.7 unsigned
6
7
166
167
reserved
0x03FF
0x03FF
0x0800
0x0
1023
1023
2048
0
Reserved
RW
RW
[15:0]
reserved
Reserved
reserved
Reserved
[1:0]
[3:2]
reserved
Reserved
reserved
0x0
0
Reserved
[15:4]
reserved
0x080
0x0001
0x0001
0x0800
0x0
128
1
Reserved
8
9
168
169
min_exposure
min_exposure
min_gain
Minimum Exposure Time
Minimum Exposure Time
Minimum Gain
RW
RW
[15:0]
1
2048
0
[1:0]
[3:2]
min_mux_gain
min_afe_gain
min_digital_gain
Minimum Column Amplifier Gain
Minimum AFE PGA Gain
0x0
0
[15:4]
0x080
128
Minimum Digital Gain
5.7 unsigned
10
11
170
171
max_exposure
max_exposure
max_gain
0x03FF
0x03FF
0x100D
0x1
1023
1023
4109
1
Maximum Exposure Time
Maximum Exposure Time
Maximum Gain
RW
RW
[15:0]
[1:0]
[3:2]
max_mux_gain
max_afe_gain
max_digital_gain
Maximum Column Amplifier Gain
Maximum AFE PGA Gain
0x3
3
[15:4]
0x100
256
Maximum Digital Gain
5.7 unsigned
12
172
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0083
0x083
0x00
131
131
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
[7:0]
[13:8]
[15:14]
0x0
0
13
14
173
174
0x2824
0x024
0x028
0x2A96
0x6
10276
36
RW
RW
[7:0]
[15:8]
40
10902
6
[3:0]
[7:4]
0x9
9
[11:8]
[15:12]
0xA
10
0x2
2
15
16
175
176
0x0080
0x080
0x0100
0x100
128
128
256
256
RW
RW
[9:0]
[9:0]
www.onsemi.com
59
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
[9:0]
Register Name
reserved
(Hex)
0x0100
0x100
Default
256
256
128
128
170
170
256
256
341
341
0
Description
Type
RW
17
177
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AEC Status
reserved
18
19
20
21
24
178
179
180
181
184
reserved
0x0080
0x080
RW
[9:0]
reserved
reserved
0x00AA
0x0AA
0x0100
0x100
RW
[9:0]
reserved
reserved
RW
[9:0]
reserved
reserved
0x0155
0x155
RW
[9:0]
reserved
total_pixels0
total_pixels[15:0]
0x0000
0x0000
Status
[15:0]
0
Total number of pixels sampled for Average,
LSB
25
26
185
186
total_pixels1
0x0000
0x0
0
0
AEC Status
Status
Status
[7:0]
total_pixels[23:16]
Total number of pixels sampled for Average,
MSB
average_status
average
0x0000
0x000
0x0
0
0
0
0
0
0
0
0
0
ASE Status
[9:0]
[12]
AEC Average Status
AEC Average Lock Status
ASE Status
avg_locked
exposure_status
exposure
27
28
187
188
0x0000
0x0000
0x0000
0x0
Status
Status
[15:0]
AEC Expsosure Status
ASE Status
gain_status
mux_gain
[1:0]
[3:2]
AEC MUX Gain Status
AEC AFE Gain Status
afe_gain
0x0
[15:4]
digital_gain
0x000
AEC Digital Gain Status
5.7 unsigned
29
189
reserved
reserved
reserved
0x0000
0x000
0x0
0
0
0
Reserved
Reserved
Reserved
Status
RW
[12:0]
[13]
Sequencer [Block Offset: 192]
192
0
general_configuration
enable
0x0000
0x0
0
0
Sequencer General Cofniguration
[0]
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
[2]
reserved
0x0
0x0
0
0
Reserved
zero_rot_enable
Zero ROT mode Selection.
‘0’: Non−Zero ROT,
‘1’: Zero ROT’
[3]
[4]
reserved
0x0
0x0
0
0
Reserved
triggered_mode
Triggered Mode Selection (Snapshot Shutter
only)
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
[6]
slave_mode
0x0
0x0
0
0
Master/Slave Selection (Snapshot Shutter
only)
‘0’: master,
‘1’: slave
nzrot_xsm_delay_
enable
Insert delay between end of ROT and start of
readout in Non−Zero ROT readout mode if ‘1’.
ROT delay is defined by register xsm_delay
www.onsemi.com
60
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
[8]
binning
0x0
0x0
0
0
Binning mode selection
‘0’: no binning,
‘1’: binning
[10]
roi_aec_enable
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
[14]
monitor_select
reserved
0x0
0x0
0x0
0
0
0
Control of the monitor pins
Reserved
[15]
sequence
Enable a sequenced readout with different
parameters for even and odd frames.
1
193
delay_configuration
reserved
0x0000
0x00
0
0
0
Sequencer delay configuration
Reserved
RW
[7:0]
[15:8]
xsm_delay
0x00
Delay between ROT end and X−readout
(Non−Zero ROT and Zero ROT mode)
Delay between ROT end and X−readout
(Normal ROT mode with
nzrot_xsm_delay_enable = ‘1’)
2
194
integration_control
dual_slope_enable
triple_slope_enable
fr_mode
0x00E4
0x0
228
0
Integration Control
Enable Dual Slope
Enable Triple Slope
RW
[0]
[1]
[2]
0x0
0
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[3]
[4]
reserved
0x0
0x0
0
0
Reserved
int_priority
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over frame
readout
[5]
[6]
[7]
[8]
halt_mode
fss_enable
fse_enable
reverse_y
0x1
0x1
0x1
0x0
1
1
1
0
The current frame will be completed when the
sequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately when
disabled, without finishing the current frame.
Generation of Frame Sequence Start Sync
code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
Generation of Frame Sequence End Sync
code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
[9]
reserved
0x0
0x0
0
0
Reserved
[11:10]
subsampling_mode
Subsampling mode
0x0: Subsampling in x and y (VITA
compatible)
0x1: Subsampling in x, not y
0x2: Subsampling in y, not x
0x3: Subsampling in x an y
[13:12]
binning_mode
0x0
0
Binning mode
0x0: Binning in x and y (VITA compatible)
0x1: Binning in x, not y
0x2: Binning in y, not x
0x3: Binning in x an y
[14]
[15]
reserved
reserved
0x0
0x0
0
0
Reserved
Reserved
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61
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
roi_active0_0
roi_active0
(Hex)
0x0001
0x01
Default
Description
Active ROI Selection
Type
RW
3
195
1
1
[15:0]
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
4
5
196
197
reserved
0x0000
0x0000
0x0102
0x02
0
Reserved
RW
RW
[15:0]
reserved
0
Reserved
black_lines
black_lines
258
2
Black Line Configuration
[7:0]
Number of black lines. Minimum is 1.
Range 1−255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1−31: blank 1−31 lines
6
7
198
199
reserved
0x0000
0x000
0
0
1
1
Reserved
RW
RW
[11:0]
[15:0]
reserved
Reserved
mult_timer0
mult_timer0
0x0001
0x0001
Exposure/Frame Rate Configuration
Mult Timer
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length
8
200
fr_length0
fr_length0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
RW
[15:0]
Frame/Reset length
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer
9
201
202
203
204
exposure0
exposure0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
RW
RW
RW
RW
[15:0]
[15:0]
[15:0]
Exposure Time
Granularity defined by mult_timer
10
11
12
exposure_ds0
exposure_ds0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
Exposure Time (Dual Slope)
Granularity defined by mult_timer
exposure_ts0
exposure_ts0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
Exposure Time (Triple Slope)
Granularity defined by mult_timer
gain_configuration0
mux_gainsw0
afe_gain0
0x01E3
0x03
0xF
483
3
Gain Configuration
[4:0]
[12:5]
[13]
Column Gain Setting
15
0
AFE Programmable Gain Setting
gain_lat_comp
0x0
Postpone gain update by 1 frame when ‘1’ to
compensate for exposure time updates
latency.
Gain is applied at start of next frame if ‘0’
13
14
205
206
digital_gain_
0x0080
128
Gain Configuration
RW
RW
configuration0
[11:0]
db_gain0
0x080
0x037F
0x1
128
895
1
Digital Gain
sync_configuration
sync_rs_x_length
Synchronization Configuration
[0]
[1]
[2]
[3]
[4]
Update of rs_x_length will not be sync’ed at
start of frame when ‘0’
sync_black_lines
sync_dummy_lines
sync_exposure
sync_gain
0x1
0x1
0x1
0x1
1
1
1
1
Update of black_lines will not be sync’ed at
start of frame when ‘0’
Update of dummy_lines will not be sync’ed at
start of frame when ‘0’
Update of exposure will not be sync’ed at start
of frame when ‘0’
Update of gain settings (gain_sw, afe_gain)
will not be sync’ed at start of frame when ‘0’
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62
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
sync_roi
(Hex)
Default
Description
Type
[5]
0x1
1
Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’
[6]
sync_ref_lines
0x1
1
Update of ref_lines will not be sync’ed at start
of frame when ‘0’
[8]
[9]
blank_roi_switch
0x1
0x1
1
1
Blank first frame after ROI switching
blank_
subsampling_ss
Blank first frame after subsampling/binning
mode switching
‘0’: No blanking
‘1’: Blanking
[10]
exposure_sync_
mode
0x0
0
When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure con-
figurations sync is disabled (continuously
syncing). This mode is only relevant for
Triggered snapshot − master mode, where the
exposure configurations are sync’ed at the
start of exposure rather than the start of FOT.
For all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
15
36
207
228
ref_lines
ref_lines
0x0000
0x00
0
0
Reference Line Configuration
RW
[7:0]
[7:0]
Number of Reference Lines
0−255
roi_active0_1
roi_active1
0x0001
0x01
1
1
Active ROI Selection
RW
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
48
49
50
240
241
242
x_resolution
x_resolution
y_resolution
y_resolution
0x00A2
162
Sequencer Status
Sensor x resolution
Sequencer Status
Sensor y resolution
Sequencer Status
Status
Status
Status
[0x007C]
[124]
[7:0]
0x000A2
[0x007C]
162
[124]
0x0800
[0x04F0]
2048
[1264]
[12:0]
[15:0]
0x0800
[0x04F0]
2048
[1264]
mult_timer_status
mult_timer
0x0000
0x0000
0
0
Mult Timer Status (Master Snapshot Shutter
only)
51
52
53
54
55
243
244
245
246
247
reset_length_status
reset_length
exposure_status
exposure
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sequencer Status
Status
Status
Status
Status
Status
[15:0]
[15:0]
[15:0]
[15:0]
Current Reset Length (not in Slave mode)
Sequencer Status
Current Exposure Time (not in Slave mode)
Sequencer Status
exposure_ds_status
exposure_ds
exposure_ts_status
exposure_ts
Current Exposure Time (not in Slave mode)
Sequencer Status
Current Exposure Time (not in Slave mode)
Sequencer Status
gain_status
[4:0]
mux_gainsw
afe_gain
Current Column Gain Setting
Current AFE Programmable Gain
Sequencer Status
[12:5]
0x00
56
248
digital_gain_status
db_gain
0x0000
0x000
0x0
Status
[11:0]
[12]
Digital Gain
dual_slope
Dual Slope Enabled
[13]
triple_slope
0x0
Triple Slope Enabled
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63
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
roi_aec_
(Hex)
Default
Description
AEC ROI Configuration
Type
RW
61
253
0x0000
0
configuration0
[7:0]
x_start
0x00
0
0
0
0
0
0
AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
[15:8]
x_end
0x00
AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
62
63
254
255
roi_aec_
configuration1
0x0000
0x0000
0x0000
0x0000
AEC ROI Configuration
RW
RW
[12:0]
[12:0]
y_start
AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi_aec_
configuration2
AEC ROI Configuration
y_end
AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
Sequencer ROI [Block Offset: 256]
0
256
roi0_configuration0
x_start
0xA100
0x00
41216
0
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
RW
[7:0]
[15:8]
x_end
0xA1
161
0
1
2
3
257
258
259
roi0_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi0_configuration2
y_end
2047
2047
41216
0
roi1_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
4
5
6
260
261
262
roi1_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi1_configuration2
y_end
2047
2047
41216
0
roi2_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
7
8
9
263
264
265
roi2_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi2_configuration2
y_end
2047
2047
41216
0
roi3_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
10
11
12
266
267
268
roi3_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi3_configuration2
y_end
2047
2047
41216
0
roi4_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
13
269
roi4_configuration1
0x0000
RW
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64
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
270
Bit Field
Register Name
y_start
(Hex)
0x0000
0x07FF
0x7FF
0xA100
0x00
Default
0
Description
Y Start Configuration
Type
[12:0]
14
roi4_configuration2
y_end
2047
2047
41216
0
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
RW
[12:0]
15
271
roi5_configuration0
x_start
RW
[7:0]
[15:8]
x_end
0xA1
161
0
16
17
18
272
273
274
roi5_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi5_configuration2
y_end
2047
2047
41216
0
roi6_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
19
20
21
275
276
277
roi6_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi6_configuration2
y_end
2047
2047
41216
0
roi7_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
22
23
24
278
279
280
roi7_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi7_configuration2
y_end
2047
2047
41216
0
roi8_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
25
26
27
281
282
283
roi8_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi8_configuration2
y_end
2047
2047
41216
0
roi9_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
28
29
30
284
285
286
roi9_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi9_configuration2
y_end
2047
2047
41216
0
roi10_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
31
287
roi10_configuration1
y_start
0x0000
0x0000
RW
[12:0]
0
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65
NOIP1SN5000A
Table 37. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
roi10_configuration2
y_end
(Hex)
0x07FF
0x7FF
0xA100
0x00
Default
2047
2047
41216
0
Description
ROI Configuration
Type
RW
32
288
[12:0]
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
33
289
roi11_configuration0
x_start
RW
[7:0]
[15:8]
x_end
0xA1
161
0
34
35
36
290
291
292
roi11_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi11_configuration2
y_end
2047
2047
41216
0
roi12_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
37
38
39
293
294
295
roi12_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi12_configuration2
y_end
2047
2047
41216
0
roi13_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
40
41
42
296
297
298
roi13_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi13_configuration2
y_end
2047
2047
41216
0
roi14_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
43
44
45
299
300
301
roi14_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
0xA100
0x00
RW
RW
RW
[12:0]
[12:0]
0
roi14_configuration2
y_end
2047
2047
41216
0
roi15_configuration0
x_start
[7:0]
[15:8]
x_end
0xA1
161
0
46
47
302
303
roi15_configuration1
y_start
0x0000
0x0000
0x07FF
0x7FF
RW
RW
[12:0]
[12:0]
0
roi15_configuration2
y_end
2047
2047
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66
NOIP1SN5000A
Selectable Pin−Out
Table 38. OPTIONS FOR PIN−OUT IN THE 84 PIN LCC
PACKAGE
The PYTHON sensor has a built−in possibility to route
some of the internal signals to different pads at the side of the
chip.
Pin Name
Pin Name
Pin No.
(84−pin LCC)
(84−pin LCC)
(84−pin LCC)
The pin−out is controlled by glob_config in the
chip_configuration register, located at address 2. The two
possible pin outs in the 84 pin package are listed in Table 38.
By default, 0x3 setting is selected.
glob_config = 0x3
glob_config = 0x1
clock_outn
clock_outp
doutn1
doutn1
8
doutp1
9
clock_outn
clock_outp
syncn
14
15
29
30
35
36
doutp1
doutn6
syncp
doutp6
doutn6
syncn
doutp6
syncp
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67
NOIP1SN5000A
Pin List
(P1&P3−SN/SE/FN). The LVDS I/Os comply to the
TIA/EIA−644−A Standard and the CMOS I/Os have 3.3 V
signal level. Table 39 shows the pin list.
The PYTHON 2000 and PYTHON 5000 image sensors
are available in LVDS output configuration
Table 39. PIN LIST FOR P1,P3−SN/SE/FN
Package Pin No.
Pin Name
vdd_33
nc
I/O Type
Direction
Description
1
Supply
3.3 V Supply
2
No connect
3
mosi
CMOS
CMOS
CMOS
Supply
Supply
LVDS
Input
Output
Input
SPI Master Out − Slave In
SPI Master In − Slave Out
SPI Input Clock
1.8 V Ground
4
miso
5
sck
6
gnd_18
vdd_18
doutn1
doutp1
doutn0
doutp0
nc
7
1.8 V Supply
8
Output
Output
Output
Output
LVDS Data Output Channel #1 (Negative), Not connected for P3
LVDS Data Output Channel #1 (Positive), Not connected for P3
LVDS Data Output Channel #0 (Negative)
LVDS Data Output Channel #0 (Positive)
No connect
9
LVDS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
LVDS
LVDS
nc
No connect
clock_outn
clock_outp
doutn2
doutp2
doutn3
doutp3
gnd_18
vdd_18
nc
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Supply
Supply
Output
Output
Output
Output
Output
Output
LVDS Clock Output (Negative)
LVDS Clock Output (Positive)
LVDS Data Output Channel #2 (Negative)
LVDS Data Output Channel #2 (Positive)
LVDS Data Output Channel #3 (Negative), Not connected for P3
LVDS Data Output Channel #3 (Positive), Not connected for P3
Supply 1.8 V Ground
Supply 1.8 V Supply
No connect
vdd_33
gnd_33
doutn4
doutp4
doutn5
doutp5
syncn
Supply
Supply
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Supply 3.3 V Supply
Supply 3.3 V Ground
Output
Output
Output
Output
Output
Output
LVDS Data Output Channel #4 (Negative)
LVDS Data Output Channel #4 (Positive)
LVDS Data Output Channel #5 (Negative), Not connected for P3
LVDS Data Output Channel #5 (Positive), Not connected for P3
LVDS Sync Channel Output (Negative)
LVDS Sync Channel Output (Positive)
No connect
syncp
nc
nc
No connect
doutn7
doutp7
doutn6
doutp6
vdd_33
gnd_33
gnd_18
vdd_18
lvds_clock_inn
lvds_clock_inp
nc
LVDS
LVDS
LVDS
LVDS
Supply
Supply
Supply
Supply
LVDS
LVDS
Output
Output
Output
Output
LVDS Data Output Channel #7 (Negative), Not connected for P3
LVDS Data Output Channel #7 (Positive), Not connected for P3
LVDS Data Output Channel #6 (Negative)
LVDS Data Output Channel #6 (Positive)
Supply 3.3 V Supply
Supply 3.3 V Ground
Supply 1.8 V Ground
Supply 1.8 V Supply
Input
Input
LVDS Clock Input (Negative)
LVDS Clock Input (Positive)
No connect
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68
NOIP1SN5000A
Table 39. PIN LIST FOR P1,P3−SN/SE/FN
Package Pin No.
Pin Name
clk_pll
vdd_18
gnd_18
ibias_master
nc
I/O Type
CMOS
Supply
Supply
Analog
Direction
Description
Reference Clock Input for PLL
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Input
1.8 V Supply
Supply 1.8 V Ground
Master Bias Reference
No connect
vdd_33
gnd_33
nc
Supply
Supply
3.3 V Supply
3.3 V Ground
No connect
nc
No connect
nc
No connect
nc
No connect
nc
No connect
nc
No connect
vdd_pix
gnd_colpc
nc
Supply
Supply
Pixel Array Supply
Pixel Array Ground
No connect
vdd_pix
gnd_colpc
gnd_33
vdd_33
nc
Supply
Supply
Supply
Supply
Pixel Array Supply
Pixel Array Ground
3.3 V Ground
3.3 V Supply
No connect
gnd_colpc
vdd_pix
gnd_colpc
vdd_pix
nc
Supply
Supply
Supply
Supply
Pixel Array Ground
Pixel Array Supply
Pixel Array Ground
Pixel Array Supply
No connect
trigger0
trigger1
nc
CMOS
CMOS
Input
Input
Trigger Input #0
Trigger Input #1
No connect
nc
No connect
nc
No connect
nc
No connect
nc
No connect
trigger2
monitor0
vdd_33
gnd_33
monitor1
reset_n
ss_n
CMOS
CMOS
Supply
Supply
CMOS
CMOS
CMOS
Supply
Input
Trigger Input #2
Monitor Output #0
Supply 3.3 V supply
Supply 3.3 V Ground
Monitor Output #1
Sensor Reset (Active Low)
SPI Slave Select.
Supply 3.3 V Ground
Output
Output
Input
Input
gnd_33
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NOIP1SN5000A
Table 40. MECHANICAL SPECIFICATION FOR P1,P3−SN/SE/FN
Parameter
Description
Min
Typ
Max
Units
Die
(with Pin 1 to the left center)
Die thickness
Die Size
725
mm
2
14.7 x 14.25
mm
Die center, X offset to the center of package
Die center, Y offset to the center of the package
Die position, tilt to the Die Attach Plane
−50
−50
−1
0
0
0
0
50
50
1
mm
mm
deg
deg
Die rotation accuracy (referenced to die scribe and lead
fingers on package on all four sides)
−1
1
Optical center referenced from the die/package center (X−dir)
Optical center referenced from the die/package center (Y−dir)
Distance from bottom of the package to top of the die surface
Distance from top of the die surface to top of the glass lid
XY size
−231
1697
1.25
mm
mm
mm
mm
mm
mm
nm
%
1.145
0.745
1.405
1.495
1.13
Glass Lid Specification
19 x 19
0.55
Thickness
0.45
400
0.65
Spectral response range
1000
Transmission of glass lid (refer to Figure 52)
D263 Teco
92
Glass Lid Material
Mechanical Shock
Vibration
JESD22−B104C; Condition G
2000
2000
260
g
Hz
JESD22−B103B; Condition 1
Mounting Profile
CTE
Reflow profile according to J−STD−020D.1
Coefficient of Thermal expansion of the LCC Package
°C
7.6
mm/°C
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NOIP1SN5000A
Package Drawing
NOTE: Unless noted otherwise, all dimensions represent nominal values.
Figure 49. Package Drawing for the 84−pin LCC Package
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NOIP1SN5000A
Optical Center Information
• Active Area outer dimensions
♦ A1 is the at (881, 13754) mm
♦ A2 is at (13356, 13754) mm
♦ A3 is at (13356, 3890) mm
♦ A4 is at (881, 3890) mm
• Center of the Active Area
♦ AA is at (7119, 8822) mm
• Center of the Die
The Center of the Die (CD) is the center of the cavity.
The center of the die is exactly at 50% between the
outsides of the two outer seal rings
The center of the cavity is exactly at 50% between the
insides of the finger pads.
• Die outer dimensions:
♦ B4 is the reference for the Die (0,0) in mm
♦ B1 is at (0, 14250) mm
♦ CD is at (7350, 7125) mm
♦ B2 is at (14700, 14250) mm
♦ B3 is at (14700, 0) mm
PYTHON5000 − Pixel (0,0)
NOTE: Unless noted otherwise, all dimensions represent nominal values.
Figure 50. Graphical Representation of the Optical Center
Packing and Tray Specification
The PYTHON packing specification with ON Semiconductor packing labels is packed as follows:
Table 41. PACKING AND TRAY INFORMATION FOR P1,P3−SN/SE/FN
LCC
Leads
84
Package size typical (mm)
Tray
Quantity / Tray
42
Restraint
Bag
Box
Length
19
Width
Thickness
2.33
Tray Spec#
Strap
Tray Quantity
19
KS−870541
Rubber
band
Double bagged using
MBB and pink ESD
bag
5 trays + 1 cover
tray
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NOIP1SN5000A
Figure 51. Packing and Tray Configuration
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NOIP1SN5000A
Glass Lid
As shown in Figure 52, no infrared attenuating color filter
glass is used. A filter must be provided in the optical path
The PYTHON 2000 and PYTHON 5000 sensor uses a
glass lid without any coatings. Figure 52 shows the
transmission characteristics of the glass lid.
when
color
devices
are
used
(source:
http://www.pgo−online.com).
Figure 52. Transmission Characteristics of the Glass Lid
Protective Film Option (−QTI Versions)
For certain size and speed options, the sensor can be
delivered with a protective foil that is intended to be
removed after assembly. The dimensions of the foil are as
illustrated in Figure 53 with the tab aligned towards one
corner of the package as illustrated in Fig 54.
Figure 54. Location of Pull Tab in Relation to Pin 1
of the Package
Figure 53. Dimensions of the Tape
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NOIP1SN5000A
SPECIFICATIONS AND USEFUL REFERENCES
Useful References
The following references are available to customers under
NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
• Product Acceptance Criteria
• Product Qualification Report
• PYTHON Developer’s Guide AND9362/D
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology
(TND6116/D) from www.onsemi.com.
Material Composition is available at:
http://www.onsemi.com/PowerSolutions/MaterialCompos
ition.do?searchParts=PYTHON5000
Return Material Authorization (RMA)
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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