NOIP1SF0480A-STI [ONSEMI]
Megapixel Global Shutter CMOS Image Sensor;
| 型号： | NOIP1SF0480A-STI |
| 厂家： | 
ONSEMI |
| 描述： | Megapixel Global Shutter CMOS Image Sensor 时钟 传感器 换能器 |
| 文件： | 总69页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PYTHONꢀ480
PYTHON 0.48 Megapixel
Global Shutter CMOS
Image Sensor
www.onsemi.com
FEATURES
• 808 x 608 Active Pixels, 1/3.6” Optical Format
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with
In-pixel CDS
DESCRIPTION
• Monochrome (SN, SP), Color (SE, SF)
• Wide CRA Options (SP, SF)
The PYTHON 480 image sensor utilizes high sensitivity
4.8 mm x 4.8 mm pixels that support low noise “pipelined”
and “triggered” global shutter readout modes. In global
shutter mode, the sensors support correlated double
sampling (CDS) readout, reducing noise and increasing
dynamic range.
The image sensors have on−chip programmable gain
amplifiers and 10−bit A/D converters. The integration time
and gain parameters can be reconfigured without any visible
image artifact. Optionally the on−chip automatic exposure
control loop (AEC) controls these parameters dynamically.
The image’s black level is either calibrated automatically or
can be adjusted by a user programmable offset.
A high level of programmability using a four wire serial
peripheral interface enables the user to read out specific
regions of interest. Up to four regions can be programmed,
achieving even higher frame rates.
The image data interface consists of one LVDS data lane,
facilitating frame rate up to 120 frames per second.
A separate synchronization channel containing payload
information is provided to facilitate the image
reconstruction at the receiving end. The device also provides
a parallel CMOS output interface at the same frame rate.
The PYTHON 480 is packaged in a 67−pin CSP package
and is available in monochrome and Bayer color
configurations with standard and wide CRA options.
• Frame Rate up to 120 fps at Full Resolution
• On−chip 10−bit Analog−to−Digital Converter (ADC)
• 10−bit Output Mode
• One Low Voltage Differential Signaling (LVDS)
High Speed Serial Output or Parallel CMOS Output
• Random Programmable Region of Interest (ROI)
Readout
• Serial Peripheral Interface (SPI)
• Automatic Exposure Control (AEC)
• Phase Locked Loop (PLL)
• Dual Power Supply (3.3 V and 1.8 V)
• −40°C to +85°C Operational Temperature Range
• 67 pin CSP
• 265 mW / 185 mW Power Dissipation (LVDS 120 fps /
60 fps)
• These Devices are Pb−Free and are RoHS Compliant
APPLICATIONS
• Machine Vision
• Motion Monitoring
• Security
• Bar Code Scanning
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2017 − Rev. 1
NOIP1SN0480A/D
PYTHON 480
ORDERING INFORMATION
Part Number
Description
Prod. Status
Production
Production
Engineering
Engineering
Production
Production
Engineering
Engineering
MPQ
Package
NOIP1SN0480A−STI
NOIP1SE0480A−STI
NOIP1SP0480A−STI
NOIP1SF0480A−STI
NOIP1SN0480A−STI1
NOIP1SE0480A−STI1
NOIP1SP0480A−STI1
NOIP1SF0480A−STI1
0.48 MegaPixel, Monochrome, CRA 1.65
0.48 MegaPixel, Bayer Color, CRA 1.65
0.48 MegaPixel, Monochrome, CRA 23.59
0.48 MegaPixel, Bayer Color, CRA 23.59
0.48 MegaPixel, Monochrome, CRA 1.65
0.48 MegaPixel, Bayer Color, CRA 1.65
0.48 MegaPixel, Monochrome, CRA 23.59
0.48 MegaPixel, Bayer Color, CRA 23.59
100
67−ball CSP
10
NOTE: More details on the part coding can be found at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
PRODUCTION MARK
Part Number
NOIP1SN0480A−STI/STI1
NOIP1SE0480A−STI/STI1
NOIP1SP0480A−STI/STI1
NOIP1SF0480A−STI/STI1
10−Digit Package Mark
SN480 YM NNN
SE480 YM NNN
SP480 YM NNN
SF480 YM NNN
where Y is 1−digit year, M is the 1−digit month, NNN is the 3−digit serial number for wafer identification
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2
PYTHON 480
SPECIFICATIONS
Key Specifications
Table 1. GENERAL SPECIFICATIONS
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Parameter
Pixel type
Specification
Parameter
Active pixels
Specification
808 (H) x 608 (V)
In−pixel CDS. Global shutter pixel
architecture
Pixel size
4.8 mm x 4.8 mm
Shutter type
Frame rate
Master clock
Pipelined and triggered global shutter
up to 120fps (Full Frame readout)
−
Conversion gain
0.096 LSB10/e
140 mV/e
−
−
LVDS Mode:
Dark temporal noise
< 11 e
68 MHz when PLL is used,
340 MHz (10−bit) / 272 MHz (8−bit)
when PLL is not used
Responsivity at 550 nm
7.7 V/lux.s
<1/6300
Parasitic Light
Sensitivity (PLS)
CMOS Mode: 68 MHz
Windowing
4 Randomly programmable windows.
Normal, sub−sampled and binned
readout modes
−
Full Well Charge
10000 e
Quantum Efficiency at
550 nm
56%
ADC resolution
LVDS outputs
CMOS outputs
10−bit
Pixel FPN
< 1.0 LSB10
data + sync + clock
PRNU
< 1%
10−bit parallel output, frame_valid,
line_valid, clock
MTF
62% @ 535 nm − X−dir & Y−dir
−
Data rate
LVDS Mode:
PSNL at 20°C
Dark signal at 20°C
Dynamic Range
200 LSB10/s, 2000 e /s
1 x 680 Mbps (10−bit)
−
5 e /s, 0.5 LSB10/s
CMOS Mode: 68 MHz
> 59 dB
40 dB
Power dissipation
Package type
LVDS mode: 265 mW,
CMOS mode: 185 mW
Signal to Noise Ratio
(SNR max)
67−pin CSP
NOTE: All numbers listed are for 1x analog gain condition unless
otherwise noted.
NOTE: All numbers listed are for 1x gain condition unless
otherwise noted.
Table 3. RECOMMENDED OPERATING RATINGS (Note 1)
Symbol
Description
Operating temperature range
Min
Max
Unit
T
J
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Performance parameters may degrade above 60°C.
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 4)
Symbol
Parameter
ABS rating for 1.8 V supply group
Min
–0.5
–0.5
−40
Max
2.2
3.8
150
85
Unit
V
ABS (1.8 V supply group)
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
ABS storage temperature range
ABS storage humidity range at 85°C
Human Body Model (HBM): JS−001
Charged Device Model (CDM): JESD22−C101
Latch−up: JESD−78
V
T
S
°C
%RH
V
Electrostatic discharge (ESD)
500
500
100
LU
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
3. Operating ratings are conditions in which operation of the device is intended to be functional.
4. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
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3
PYTHON 480
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for T = T
to T
, all other limits T = +30°C. (Notes 5, 6, 7, 8)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
Unit
Power Supply Parameters − LVDS
(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Supply voltage, 3.3 V
3.2
3.3
3.4
1.9
V
mA
V
Current consumption 3.3 V supply
Supply voltage, 1.8 V
48
1.7
1.8
Current consumption 1.8 V supply
Supply voltage, pixel
59
3.3
mA
V
3.25
3.35
Current consumption pixel supply
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
Power consumption in low power standby mode
Power consumption at lower pixel rates
0.04
mA
mW
mW
265
Pstby_lp
Popt
< 1
Configurable
Power Supply Parameters − CMOS
vdd_33
Idd_33
vdd_18
Idd_18
vdd_pix
Idd_pix
Ptot
Supply voltage, 3.3 V
3.2
1.7
3.3
3.4
1.9
V
mA
V
Current consumption 3.3 V supply
Supply voltage, 1.8 V
33
1.8
Current consumption 1.8 V supply
Supply voltage, pixel
37
mA
V
3.25
3.3
3
3.35
Current consumption pixel supply
Total power consumption
mA
mW
mW
185
Pstby_lp
Popt
Power consumption in low power standby mode
Power consumption at lower pixel rates
< 0.5
Configurable
I/O − LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling − 1 data channel, 1 synchronization channel
680
340
1.8
Mbps
MHz
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
Vicm
LVDS input common mode level
0.3
1.25
50
V
Tccsk
Channel to channel skew (Training pattern allows per channel
skew correction)
ps
I/O − CMOS 1.8 V Signal levels (Note 9)
fpardata
ViL
Data rate on parallel channels (10−bit)
68
0.8
3.6
Mbps
CMOS input low level
CMOS input high level
−0.2
V
V
ViH
1.2
Electrical Interface − LVDS
fin
MHz
Input clock rate when PLL used
Input clock rate when PLL used
68
340
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON480 available at the Image Sensor Portal for detailed acceptance criteria specifications.
9. CMOS inputs are compatible with 3.3 V signal levels.
10.Longer integration times are possible, but with possible image quality trade−offs.
11. Data is clocked on the rising edge of the output clock. This can be changed to the falling edge by register 130[8]
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4
PYTHON 480
Table 5. ELECTRICAL SPECIFICATIONS (continued)
Boldface limits apply for T = T
to T
, all other limits T = +30°C. (Notes 5, 6, 7, 8)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
Unit
Electrical Interface − LVDS
tidc
Input clock duty cycle when PLL used
10−bit, PLL used (fin = 68 MHz)
45
6
50
55
%
ratspi
(= fin/fspi)
10−bit, LVDS input used (fin = 340 MHz)
30
Electrical Interface − CMOS
Cout
Tr
Output load (only capacitive load)
10
6.5
5
pF
ns
Output Rise Time
Output Fall Time
2.5
2
4.5
3.5
Tf
ns
fin
Input clock rate
68
MHz
%
tidc
Input clock Duty Cycle
10−bit (fin = 58 MHz)
45
6
50
55
ratspi
(= fin/fspi)
todc
CLK_OUT duty cycle
40
50
60
4
%
ns
ns
ns
ns
ns
t
t
t
t
t
CLK_OUT to DOUTx (Note 11)
CLK_OUT to FRAME_VALID HIGH
CLK_OUT to FRAME_VALID LOW
CLK_OUT to LINE_VALID HIGH
CLK_OUT to LINE_VALID LOW
CD
4
CFH
CFL
CLH
CLL
4
4
4
Frame Specifications − LVDS
T_int
Integration Time range
0.035
100
(Note 10)
ms
fps
Frame rate at full resolution (800 x 600 pixels)
Frame rate at 640 x 480 pixels resolution
Pixel rate
120
180
68
fps
fps
fps_roi
fpix
Mpix/s
Frame Specifications − CMOS
fps Frame rate at full resolution (800 x 600 pixels)
120
fps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON480 available at the Image Sensor Portal for detailed acceptance criteria specifications.
9. CMOS inputs are compatible with 3.3 V signal levels.
10.Longer integration times are possible, but with possible image quality trade−offs.
11. Data is clocked on the rising edge of the output clock. This can be changed to the falling edge by register 130[8]
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5
PYTHON 480
Color Filter Array
The sensor is processed with a Bayer RGB color pattern as shown in Figure 1. Pixel (0,0) has a red filter situated to the bottom
left.
Y
Gb
Gr
X
pixel (0;0)
Figure 1. Color Filter Array for the Pixel Array
Quantum Efficiency
60.0%
Red
Gr
Gb
Blue
Mono
50.0%
40.0%
30.0%
20.0%
10.0%
0.0%
300
400
500
600
700
800
900
1000
1100
Wavelength [nm]
Figure 2. Quantum Efficiency Curve for Mono and Color
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6
PYTHON 480
Ray Angle and Microlens Array Information
versus photodiode position will cause a tilted angle of peak
photoresponse, here denoted Chief Ray Angle (CRA).
Microlenses and photodiodes are aligned with 0 shift and
CRA in the center of the array, while the shift and CRA
increases radially towards its edges, as illustrated by
Figure 5.
The purpose of the shifted microlenses is to improve the
uniformity of photoresponse when camera lenses with a
finite exit pupil distance are used. The CRA varies nearly
linearly with distance from the center as illustrated in Figure
6, with a corner CRA of approximately 1.65 degrees. This
edge CRA is matching a lens with exit pupil distance of
~ 60 mm.
An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of the
photodiodes. The combined microlens array and pixel array
has two important properties:
1. Angular dependency of photoresponse of a pixel
The photoresponse of a pixel with microlens in the center
of the array to a fixed optical power with varied incidence
angle is as plotted in Figure 3, where definitions of angles fx
and fy are as described by Figure 4.
2. Microlens shift across array and CRA
The microlens array is fabricated with a slightly smaller
pitch than the array of photodiodes. This difference in pitch
creates a varying degree of shift of a pixel’s microlens with
regards to its photodiode. A shift in microlens position
Another CRA option targetting 23.59 degrees is available
for both mono and color versions. The corresponding curves
for this version is shown in figures 8 and 9.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
fy = 0
fx = 0
−30
−20
−10
0
10
20
30
Incidence Angle f , f
x
y
[degrees deviation from normal]
Note that the photoresponse peaks near normal incidence for center pixels.
Figure 3. Central Pixel Photoresponse to a Fixed Optical Power with Incidence Angle varied along fx and fy (Low
CRA Version)
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7
PYTHON 480
Figure 4. Definition of Angles used in Figure 3.
Shift
CRA
Center pixel
(aligned)
Edge pixel
(with shift)
The Center Axes of the Microlens and the Photodiode Coincide for the Center Pixels.
For the Edge Pixels, there is a Shift between the Axes of the Microlens and the Photodiode
causing a Peak Response Incidence Angle (CRA) that deviates from the Normal of the
Pixel Array.
Figure 5. Principles of Microlens Shift
2.5
2.3 deg
2
1.8 deg
1.5
1.4 deg
1
x direction
y direction
diagonal
0.5
0
0
0.5
1
1.5
2
2.5
Distance from center [mm]
Figure 6. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array (Low
CRA Version)
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8
PYTHON 480
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
fy = 0
fx = 0
−30
−20
−10
0
10
20
30
Incidence Angle f , f
x
y
[degrees deviation from normal]
Note that the photoresponse peaks near normal incidence for center pixels.
Figure 7. Central Pixel Photoresponse to a Fixed Optical Power with Incidence Angle varied along fx and fy (High
CRA Version)
25
24.1 deg
20
19.4 deg
15
14.4 deg
10
x direction
y direction
diagonal
5
0
0
0.5
1
1.5
2
2.5
Distance from center [mm]
Figure 8. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array (High
CRA Version)
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9
PYTHON 480
LVDS receiver
LVDS receiver
LVDS receiver
CLOCK_OUTP
CLOCK_OUTN
VDD_33
VDD_18
C1
C2
VDD_3.3 V
VDD_1.8 V
VDD_pix
VDD_pix
C3
C4
SYNCP
SYNCN
Vref_botplate
VSS_colpc
VSS_33
Vref_botplate
DOUTP
DOUTN
VSS_18
SS_N
MISO
MOSI
SCK
LVDS clock Input
LVDS_CLOCK_INP
LVDS_CLOCK_INN
CLK_OUT
DOUT0
RESET_N
DOUT1
TRIGGER0
DOUT2
DOUT3
TR1
TR2
DOUT4
DOUT5
DOUT6
SCAN_EN
TEST_ENABLE
DOUT7
DOUT8
DOUT9
FRAME_VALID
LINE_VALID
68 MHz
CLK_PLL
MONITOR0
MONITOR1
MONITOR2
LOCK_DETECT
47.7 kW
NOTES:
− Vref_botplate power needs to allow source and sink; load is < 20 mA
− vdd_pix is 3.3 V low noise power supply. Verify tolerance allowed in Table 5.
− Place low inductance bypass capacitors as close as possible to all power pins (10 mF and 100 nF)
− LVDS lines: Route the differential output traces close together to maximize common−mode rejection
with the 100 W termination resistor close to the receiver. User should pay attention to printed circuit
board (PCB) trace lengths to minimize any delay skew.
Figure 9. Typical Application Diagram
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10
PYTHON 480
5 V
5 V
FB
0.1 mF
16 V
BLM18AG601
3.2 kW
1.8 kW
−
Vref_botplate
1.8 V
+
LMV321
4.7 mF
0.1 mF
16 V
16 V
Figure 10. Recommended Circuit for Vref_botplate Signal Generation
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11
PYTHON 480
OVERVIEW
Figure 11 gives an overview of the major functional blocks of the sensor.
Image Core
Image Core Bias
Pixel Array
Column Structure
Automatic
Exposure
Control
(AEC)
2 analog channels
Analog Front End (AFE)
2 x 10 bit
digital channels
Control &
Registers
Data Formatting
Clock
Distribution
1 x 10 bit
digital channels
Serializers & LVDS
CMOS Interface
LVDS
Interface
PLL
Receiver
CMOS Interface
(Data, frame_valid,
line_valid)
LVDS Interface
CMOS Clock
Input
LVDS Clock
Input
(Data, Sync, Clock)
Figure 11. Block Diagram
Image Core
The function of the row drivers is to access the image array
line by line, or all lines together, to reset or read the pixel
data. The row drivers are controlled by the on−chip
sequencer and can access the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
The image core consists of:
• Pixel Array
• Address Decoders and Row Drivers
• Pixel Biasing
The PYTHON 480 pixel array contains 808 (H) x 608 (V)
readout pixels with a pixel pitch of 4.8 mm, inclusive of 8
pixel rows and 8 pixel columns at every side to allow for
reprocessing or color reconstruction. The sensors use
in−pixel CDS architecture, which makes it possible to
achieve a low noise read out of the pixel array in global
shutter mode with CDS.
Phase Locked Loop
The PLL accepts a (low speed) clock and generates the
required high speed clock. Input clock frequency is 68 MHz.
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PYTHON 480
LVDS Clock Receiver
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Input clock frequency is 340 MHz. The clock input needs
to be terminated with a 100 W resistor.
Serializer and LVDS Interface (LVDS Mode only)
The serializer and LVDS interface block receives the
formatted data from the data formatting block. This data is
serialized and transmitted by the LVDS 340 MHz output
driver.
The maximum output data rate is 680 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.
Column Multiplexer
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 2 parallel differential outputs operating at a
frequency of 34 MHz. At this stage, the reset signal and
integrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 3.5x can be applied to the signal. The column
CMOS Interface
multiplexer
also
supports
read−1−skip−1
and
Frame synchronization information is communicated by
means of frame and line valid strobes. Both CMOS and
LVDS outputs are active at the same time. LVDS channels
can be powered down through SPI control when using the
CMOS outputs.
read−2−skip−2 mode. Enabling this mode increases the
frame rate, with a decrease in resolution but same field of
view.
Bias Generator
The bias generator generates all required reference
voltages and bias currents used on chip. An external resistor
of 47 kW, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operate
properly.
Sequencer
The sequencer:
• Controls the image core. Starts and stops integration
and control pixel readout.
• Operates the sensor in master or slave mode.
Analog Front End
The AFE contains 2 channels, each containing a PGA and
a 10−bit ADC.
For each of the 2 channels, a pipelined 10−bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
• Applies the window settings. Organizes readouts so that
only the configured windows are read.
• Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
• Starts up the sensor correctly when leaving standby
mode.
Data Formatting
Automatic Exposure Control
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
A
frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
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13
FOT
Readout Fra
e
-1
eadout Fra e N
Integration Ti
Handling
e
Reset
N
Reset
N+1
PYTHON 480
OPERATING MODES
Global Shutter Mode
simultaneously and after the integration time all pixel values
are sampled together on the storage node inside each pixel.
The pixel core is read out line by line after integration. Note
that the integration and readout can occur in parallel or
sequentially. The integration starts at a certain period,
relative to the frame start.
The PYTHON 480 operates in pipelined or triggered
global shuttering modes. In this mode, light integration takes
place on all pixels in parallel, although subsequent readout
is sequential. Figure 12 shows the integration and readout
sequence for the global shutter. All pixels are light sensitive
at the same period of time. The whole pixel core is reset
Figure 12. Global Shutter Operation
Pipelined Global Shutter Mode
Overhead Time (ROT). Figure 13 shows the exposure and
readout time line in pipelined global shutter mode.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N−1. The readout of every frame starts with
a Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
Master Mode
In this mode, the integration time is set through the
register interface and the sensor integrates and reads out the
images autonomously. The sensor acquires images without
any user interaction.
Exposure Time N
FOT
FOT
Exposure Time N+1
FOT
FOT
Readout
Handling
ROT
Line Readout
Figure 13. Integration and Readout for Pipelined Shutter
Slave Mode
of reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon a
falling edge of the trigger input, the image is sampled and the
readout begins. Figure 14 shows the relation between the
external trigger signal and the exposure/readout timing.
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode and
the integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out
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14
Exposure Ti
Register Controlled
Readout -1
FOT
FOT
Exposure Ti
Readout N
e N
e
+1
FOT
FOT
FOT
Integration Ti
Handling
e
Reset
N
Reset
N+1
PYTHON 480
External Trigger
Integration Time
Handling
Reset
N
Reset
N+1
Exposure Time N
FOT
FOT
Exposure T im e N+1
Readout N
FOT
FOT
Readout
Handling
FOT
Readout N−1
ROT
Line Readout
Figure 14. Pipelined Shutter Operated in Slave Mode
Triggered Global Shutter Mode
The triggered global mode can also be controlled in a
master or in a slave mode.
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are:
Master Mode
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 15 shows the relation between the external trigger
signal and the exposure/readout timing.
• Upon user action, one single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
If a rising edge is applied on the external trigger before the
exposure time and FOT of the previous frame is complete,
it is ignored by the sensor.
• Integration and readout is under user control through an
external pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.
No effect on falling edge
External Trigger
Readout
Handling
ROT
Line Readout
Figure 15. Triggered Shutter Operated in Master Mode
Slave Mode
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, the
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PYTHON 480
SENSOR OPERATION
Flowchart
Figure 16 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval
circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.
Power Off
Power Down
Sequence
Power Up Sequence
Low-Power Standby
Disable Clock Management
Part 1
Enable Clock Management - Part 1
Poll Lock Indication
(only when PLL is enabled)
Standby (1)
Enable Clock Management - Part 2
(First Pass after Hard Reset)
Disable Clock Management
Part 2
Intermediate Standby
Required Register
Upload
Sensor (re-)configuration
(optional)
Standby (2)
Soft Power-Down
Soft Power-Up
Sensor (re-)configuration
(optional)
Idle
Enable Sequencer
Disable Sequencer
Sensor (re-)configuration
(optional)
Running
Figure 16. Sensor Operation Flowchart
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PYTHON 480
Sensor States
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slave
modes.
Low Power Standby
In low power standby state, all power supplies are on, but
internally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave the
low power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable Clock
Management’ action described in Enable Clock
Management − Part 1 on page 18
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 17 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the described
sequence. Any other supply ramping sequence may lead to
high current peaks and, as consequence, a failure of the
sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
Standby (2)
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
NOTE: The ‘clock input’ can be LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Idle
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
SPI Upload
> 10us
> 10us
> 10us
> 10us
> 10us
Figure 17. Power Up Sequence
Enable Clock Management − Part 1
In the serial modes, if the PLL is not used, the LVDS clock
input must be running.
It is important to follow the upload sequence listed in
Table 6.
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for LVDS 10−bit serial mode, with the PLL.
Note that the SPI uploads to be executed to configure the
sensor for other supported modes are available to customers
under NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
NOTE: Since the PLL is not used in CMOS mode, the
lock detect status must not be checked for the
CMOS Mode sensor.
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PYTHON 480
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
is not used, this step can be bypassed as shown in Figure 16
on page 16.
Management− Part 2’ action can be continued. When PLL
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1
Upload #
Address
Data
Description
LVDS Mode with PLL
1
2
0x0000
0x0001
0x0000
0x0003
0x2113
0x0000
0x2280
0x3D2D
0x7014
Monochrome sensor
Color sensor
2
3
4
5
6
7
8
8
Release PLL soft reset
Enable PLL
16
17
20
26
27
32
Configure PLL
Configure clock management
Configure PLL lock detector
Configure PLL lock detector
Configure clock management
Enable Clock Management − Part 2
The next step to configure the clock management consists
of SPI uploads which enables all internal clock distribution.
The required uploads are listed in Table 4. Note that it is
important to follow the upload sequence listed in Table 7.
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2
Upload #
Address
Data
Description
LVDS Mode with PLL
1
2
3
9
0x0000
0x7007
0x0001
Release clock generator soft reset
32
34
Enable logic clock
Enable logic blocks
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads can be downloaded from the MyON website.
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PYTHON 480
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power up uploads are listed in Table 8.
Table 8. SOFT POWER UP REGISTER UPLOAD
Upload #
Address
Data
Description
LVDS Mode with PLL
1
2
3
4
5
6
7
8
10
32
40
42
48
64
72
112
0x0000
0x7007
0x0003
0x4113
0x0001
0x0001
0x0127
0x0007
Release soft reset state
Enable analog clock
Enable column multiplexer
Configure image core
Enable AFE
Enable biasing block
Enable charge pump
Enable LVDS transmitters
CMOS Mode with PLL
1
2
3
4
5
6
7
10
32
40
42
48
64
72
0x0000
0x7007
0x0003
0x4113
0x0001
0x0001
0x0127
Release soft reset state
Enable analog clock
Enable column multiplexer
Configure image core
Enable AFE
Enable biasing block
Enable charge pump
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PYTHON 480
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 17.
The ‘Enable Sequencer’ action consists of a set of register
uploads. The required uploads are listed in Table 9.
Table 9. ENABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data (ZROT)
Description
1
192
0x0803
Enable Sequencer
User Actions: Functional Modes to Power Down Sequences
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set of register
uploads. as listed in Table 10.
Table 10. DISABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data (ZROT)
Description
1
192
0x0802
Disable sequencer
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
current dissipation. This action exists of a set of SPI uploads.
The soft power down uploads are listed in Table 12.
Table 11. SOFT POWER DOWN REGISTER UPLOAD
Upload #
Address
Data
Description
LVDS Mode with PLL
1
112
72
64
48
42
40
32
10
0x0999
0x7006
0x0000
0x4110
0x0000
0x0000
0x0010
0x0000
Soft reset
2
Disable analog clock
Disable column multiplexer
Image core config
3
4
5
Disable AFE
6
Disable biasing block
Disable charge pump
Disable LVDS transmitters
7
8
CMOS Mode with PLL
1
2
3
4
5
6
7
72
64
48
42
40
32
10
0x0999
0x7006
0x0000
0x4110
0x0000
0x0000
0x0010
Soft reset
Disable analog clock
Disable column multiplexer
Image core config
Disable AFE
Disable biasing block
Disable charge pump
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PYTHON 480
Disable Clock Management − Part 2
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 13.
Table 12. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2
Upload #
Address
Data
Description
LVDS Mode with PLL
1
2
3
34
32
9
0x0000
0x7004
0x0000
Soft reset clock generator
Disable logic clock
Disable logic blocks
Disable Clock Management − Part 1
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 13.
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1
Upload #
Address
Data
Description
LVDS Mode with PLL
1
2
16
8
0x0099
0x0000
Soft reset PLL
Disable PLL
Power Down Sequence
Figure 18 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
clock input
reset_n
vdd_18
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
vdd_33
vdd_pix
NOTE: The ‘clock input’ can be the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
> 10us > 10us > 10us > 10us
Figure 18. Power Down Sequence
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PYTHON 480
Sensor Reconfiguration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 29 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 30 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
Some registers are only modified when the sensor is not
acquiring images. Reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 14 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 14. STATIC READOUT PARAMETERS
Group
Clock generator
Addresses
32
Description
Configure according to recommendation
Image core
40
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
AFE
48
Bias
64–71
112
LVDS
Sequencer mode selection
192 [5:4]
Operation modes are: • triggered_mode
• slave_mode
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the
recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
The category of registers as shown in Table 15 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
Table 15. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[12:8]
reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black
level compensation.
Sync codes
129[13]
116–126
Incorrect sync codes may be generated during the frame in which these registers
are modified.
Datablock test configurations
144
Modification of these registers may generate incorrect test patterns during
a transient frame.
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PYTHON 480
Dynamic Readout Parameters
shown in Table 16. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 16. DYNAMIC READOUT PARAMETERS
Group
Subsampling
Addresses
Description
192[7]
Subsampling is synchronized to a new frame start.
ROI configuration
195
256–265
A ROI switch is only detected when a new window is selected as the active window
(reconfiguration of register 195). reconfiguration of the ROI dimension of the active win-
dow does not lead to a frame blank and can cause a corrupted image.
Exposure
199−203
204−205
Exposure reconfiguration does not cause artifact. However, a latency of one frame is ob-
served unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (mas-
ter).
reconfiguration
Gain reconfiguration
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Freezing Active Configurations
registers and uses them for the coming frames. Freezing of
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
the active configurations can be frozen while altering the
SPI registers by disabling synchronization for the
corresponding functionality before reconfiguration. When
all registers are uploaded, re−enable the synchronization.
The sensor’s sequencer then updates its active set of
the active set of registers can be programmed in the
sync_configuration registers, which can be found at the SPI
address 206.
Figure 19 shows a reconfiguration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 20 shows the usage of the sync_configuration
settings. Before uploading
a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3
Frame N+4
Time Line
SPI Registers
Active Registers
Figure 19. Frame Synchronization of Configurations (no freezing)
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PYTHON 480
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3ꢁꢁꢂꢀFrame N+4
Time Line
sync_configuration
SPI Registers
This configuration is not taken into
account as sync_register is inactive.
Active Registers
Figure 20. reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 17 lists the several sync_configuration possibilities along with the respective registers being
frozen.
Table 17. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_dummy_lines
sync_exposure
dummy_lines
Update of dummy line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_gain
sync_roi
mux_gainsw
afe_gain
db_gain
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
roi_active0[3:0]
subsampling
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration of
active windows is not gated by this setting.
Window Configuration
Black Calibration
Up to 4 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 265. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 2 columns contained
in one kernel. This implies 2 black level offsets are generated
and applied to the corresponding columns. Configurable
parameters for the black−level algorithm are listed in
Table 18.
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PYTHON 480
Table 18. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Group
Addresses
Description
Black Line Generation
197[7:0]
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Each black line contains 404 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured. These
blanked out lines are not used for black calibration. It is recommended to enable this func-
tionality, because the first line can have a different behavior caused by boundary effects.
Black Value Filtering
129[0]
auto_blackcal_enable Internal black−level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when au-
to_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled. The calculated black calibration factors are frozen when this register is set to
0x1FF (all−‘1’) in auto calibration mode. Any value different from 0x1FF re−enables the
black calibration algorithm. This freezing option can be used to prevent eventual frame to
frame jitter on the black level as the correction factors are recalculated every frame. It is
recommended to enable the black calibration regularly to compensate for temperature
changes.
129[10]
blackcal_offset_dec
black_samples
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
128[10:8]
The black samples are low−pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^black_samples.
Note: An error is reported by the device if more samples than available are requested
(refer to register 136).
Black Level Filtering Monitoring
136 blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determina-
tion (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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PYTHON 480
Serial Peripheral Interface
The sck clock is passed through to the sensor as
indicated in Figure 21. The sensor samples this
data on a rising edge of the sck clock (mosi needs
to be driven by the system on the falling edge of
the sck clock).
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
5. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 21 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON 480 image
sensors use 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 21,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
6. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
7. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
3. Select the sensor for read or write by pulling down
the ss_n line.
4. One SPI clock cycle after selecting the sensor, the
9−bit data is transferred, most significant bit first.
SPI − WRITE
ss_n
sck
t_sckss
t_sssck
tsck
ts _mos i
th_mosi
A8
A7
..
..
..
A1
A0
`1'
D
5
D14
..
..
..
..
D1
D0
mosi
miso
SPI − READ
ss_n
sck
t_sckss
t_sssck
tsck
ts_mosi
th_mosi
A8
A7
..
..
..
A1
A0
`0'
mosi
miso
ts _miso
th_miso
D
5
D14
..
..
..
..
D1
D0
Figure 21. SPI Read and Write Timing Diagram
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26
PYTHON 480
Table 19. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
ns
(*)
tsck
sck clock period
100
tsssck
tsckss
ts_mosi
th_mosi
ts_miso
th_miso
tspi
ss_n low to sck rising edge
sck falling edge to ss_n high
Required setup time for mosi
Required hold time for mosi
Setup time for miso
tsck
tsck
ns
ns
20
ns
20
ns
tsck/2−10
tsck/2−20
2 x tsck
ns
Hold time for miso
ns
Minimal time between two consecutive SPI accesses (not shown in figure)
ns
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/f . See text for more information on SPI clock frequency restrictions.
SPI
IMAGE SENSOR TIMING AND READOUT
The following sections describe the configurations for
single slope reset mechanism. Extra integration time
registers are available.
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure. It is read as number of system
clock cycles (14.706 ns nominal at 68 MHz).
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 22.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
Frame N
Frame N+1
Exposure State
Readout
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 22. Integration Control for (Pipelined) Global Shutter Mode (Master)
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27
PYTHON 480
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 23.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Frame N+1
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Exposure State
trigger0
(No effect on falling edge)
Readout
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Exposure Time Control in Triggered Shutter Mode (Master)
Notes:
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 24.
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
not used in this mode.
• The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
• If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
Triggered Global Shutter (Slave)
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
Frame N
Frame N+1
Exposure State
trigger0
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Readout
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 24. Exposure Time Control in Global−Slave Mode
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28
PYTHON 480
ADDITIONAL FEATURES
Multiple Window Readout
y1_end
The PYTHON 480 image sensors support multiple
window readout, which means that only the user−selected
Regions Of Interest (ROI) are read out. This allows limiting
data output for every frame, which in turn allows increasing
the frame rate. Up to four ROIs can be configured.
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 25 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
x1_end
ROI 0
Figure 26. Overlapping Multiple Window
Configuration
y-start
The sequencer analyses each line that need to be read out
for multiple windows.
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-startꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢂx-end
Figure 25. Region of Interest Configuration
x_start_roi(i) vx_start_roi(j) AND
x_end_roi(i) vx_end_roi(j)
Where j > i
• x−start[8:0]
x−start defines the x−starting point of the desired window.
The sensor reads out 2 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 2 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 2 to find
the corresponding column in the pixel array.
• x−end[8:0]
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #3.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to four windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 26.
NOTE: The least significant configuration bits for x and
y parameters are located in separate registers
(refer to registers 264−265). One may decide not
to reconfigure these bits, in which case the
configuration granularity becomes 4 pixels for
both x− and y−configurations.
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PYTHON 480
Figure 27 illustrates
a
practical example of
a
configuration with four windows. The current position of
the read pointer (ys) is indicated by a red line crossing the
image array. For this position of the read pointer, three
windows need to be read out. The initial start position for the
x−kernel pointer is the x−start configuration of ROI0.
Kernels are scanned up to the ROI2 x−end position. From
there, the x−pointer jumps to the next window, which is
ROI3 in this illustration. When reaching ROI3’s x−end
position, the read pointer is incremented to the next line and
xs is reinitialized to the starting position of ROI0.
ROI 1
ROI 2
ROI 3
ys
ROI 0
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
Figure 27. Scanning the Image Array with
Four Windows
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 27, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
• Each window can be activated separately. There is no
restriction on which window and how many of the 4
windows are active.
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome sensors (LVDS/CMOS) and
color sensors (LVDS/CMOS).
Monochrome Sensors
For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 28 shows which pixels are read and which
ones are skipped.
Figure 28. Subsampling Scheme for Monochrome and Color Sensors
Reverse Readout
Reverse readout in x−direction can be done by toggling
Reverse readout in y−direction can be done by toggling
reverse_y (reg 194[8]). The reference for y_start and y_end
pointers is reversed.
reverse_x (reg 194[9]).
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30
PYTHON 480
Black Reference
lines are indicated on the output interface by means of a
dedicated Sync pattern (REF).
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (404 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
The black calibration block can be configured to either
perform black level correction and compression or not. In
the latter case, the LSB is discarded from the ADC word.
Optionally, the black level calibration processor can be
configured to transmit the average black level on the
reference lines. In this mode, the reference pixel data are
replaced by the average black level, as calculated by the
black calibration block. Channel differences can easily be
observed
in
this
mode
(See
register
reg_db_ref_bcal_enable).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number, which is 0. Black reference data is
classified by a BL code.
Signal Path Gain
Analog Gain Stages
Referring to Table 20, three gain settings are available in
the analog data path to apply gain to the analog signal before
it is digitized. The gain amplifier can apply a gain of
approximately 1x to 3.5x to the analog signal.
The moment a gain reconfiguration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Reference Lines
The sensor optionally reads out one or more reference
lines after the black lines. The number of reference lines to
be generated is programmable. No reference lines shall be
generated when set to 0. As for the black lines, the length of
the reference lines depends on the operation mode.
The reference lines are not used internally in the sensor.
The ROT for these lines can be configured such that these
lines contain particular reference data, such as a grey level,
in order to perform PRNU correction off−chip. Reference
Table 20. SIGNAL PATH GAIN STAGES
Address
204[12:0]
204[12:0]
204[12:0]
Gain Setting
0x00E1
Gain Stage 1 (204[4:0])
Gain Stage 2 (204[12:5])
Overall Gain
1
2
2
1
1
1
2
0x00E4
0x0024
1.75
3.5
NOTE: The sensor performance specifications are tested at unity gain. Analog gain above 2x affects noise performance. All other gains
settings shown in this table are tested for sensor functionality only.
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
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PYTHON 480
Automatic Exposure Control
The exposure control mechanism has the shape of a
general feedback control system. Figure 29 shows the high
level block diagram of the exposure control loop.
AEC
Statistics
AEC
Filter
AEC
Enforcer
Requested Illumination Level
(Target)
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 29. Automatic Exposure Control Loop
AEC Statistics Block
Three main blocks can be distinguished:
The statistics block calculates the average illumination of
the current image. Based on the difference between the
calculated illumination and the target illumination the
statistics block requests a relative gain change.
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 21.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
The automatic exposure control loop is enabled by asserting
the aec_enable configuration in register 160.
Table 21. AEC SAMPLE SELECTION
Register
Name
Description
192[10]
roi_aec_enable When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined
by roi_aec
253−255 roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is
asserted. Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this
window at least overlaps with one or more active windows.
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PYTHON 480
AEC Filter Block
Target Illumination
The filter block low−pass filters the gain change requests
received from the statistics block.
The target illumination value is configured by means of
register desired_intensity as shown in Table 22.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 22. AEC TARGET ILLUMINATION
CONFIGURATION
AEC Enforcer Block
Register
Name
Description
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
161[9:0] desired_in- Target intensity value, on 10−bit scale.
tensity
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 23 for color scale factors. For
mono sensors, configure these factors to their default value.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
Table 23. COLOR SCALE FACTORS
Register
Name
Description
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
162[9:0] red_scale_factor
Red scale factor for AEC
statistics
163[9:0] green1_scale_fa
ctor
Green1 scale factor for AEC
statistics
• Analog Gain
164[9:0] green2_scale_fa
ctor
Green2 scale factor for AEC
statistics
The sensor has two analog gain stages, configurable
independently from each other. Typically the AEC shall only
regulate the first stage.
165[9:0] blue_scale_factor Blue scale factor for AEC
statistics
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
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PYTHON 480
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 24 lists the relevant
registers.
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Table 24. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
Register
Name
Description
Exposure Control Status Registers
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 25 reflecting the
AEC and Sequencer Status registers.
168[15:0] min_exposure
Lower bound for the integration
time applied by the AEC
169[1:0]
169[3:2]
min_mux_gain
min_afe_gain
Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x1 = 1x
0x4 = 2x
Lower bound for the second
stage analog amplifier.
This stage has two
configurations with the following
approximative gain settings:
0x7 = 1x
Table 25. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
0x1 = 1.75x
AEC Status Registers
184[15:0] total_pixels
169[15:4] min_digital_gain Lower bound for the digital gain
stage. This configuration
Total number of pixels taken into
account for the AEC statistics.
specifies the effective gain in 5.7
unsigned format
186[9:0]
average
Calculated average illumination
level for the current frame.
170[15:0] max_exposure
Upper bound for the integration
time applied by the AEC
187[15:0] exposure
AEC calculated exposure.
Note: this parameter is updated at
the frame end.
171[1:0]
171[3:2]
max_mux_gain
max_afe_gain
Upper bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x1 = 1x
188[1:0]
188[3:2]
mux_gain
afe_gain
AEC calculated analog gain
st
(1 stage)
Note: this parameter is updated at
the frame end.
0x4 = 2x
AEC calculated analog gain
Upper bound for the second
stage analog amplifier
st
(2 stage)
Note: this parameter is updated at
the frame end.
This stage has two
configurations with the following
approximative gain settings:
0x7 = 1x
188[15:4] digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at
the frame end.
0x1 = 1.75x
171[15:4] max_digit-
al_gain
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
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PYTHON 480
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Table 26. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Corrupted
Frame
Blanked Out
Frame
Configuration
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Disabling: Yes
Configurable
No
Configurable with blank_subsampling_ss register.
Frame Timing
black_lines
Exposure Control
mult_timer
fr_length
No
No
No
No
No
No
No
Latency is 1 frame
Latency is 1 frame
Latency is 1 frame
exposure
Gain
mux_gainsw
afe_gain
No
No
No
No
No
No
Latency configurable by means of gain_lat_comp register
Latency configurable by means of gain_lat_comp register.
Latency configurable by means of gain_lat_comp register.
db_gain
Window/ROI
roi_active
See Note
See Note
No
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
Black Calibration
black_samples
No
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
CRC Calculation
crc_seed
Sync Channel
bl_0
See Note
No
No
No
Manual blackcal_offset updates are instantly active.
Impacts the transmitted CRC
No
No
No
No
No
No
No
No
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
img_0
crc_0
tr_0
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PYTHON 480
Monitor Pins
states from the sequencer. A three−bit register configures the
The internal sequencer has two monitor outputs (Pin 44
and Pin 45) that can be used to communicate the internal
assignment of the pins as shown in Table 27.
Table 27. MONITOR SELECT
Monitor Select
Monitor Output
Description
0x0
monitor0: ‘0’
monitor1: ‘0’
monitor2: ‘0’
No information is provided on the output pins. All outputs are
driven to logic ‘0’
0x1
0x2
0x3
0x4
0x5
0x6
0x7
monitor0: Integration time indication
monitor1: ROT indication
High during integration
High when ROT is active, low outside ROT
High during dummy lines, low during all other lines
High during integration
monitor2: Dummy line indication
monitor0: Integration time indication
monitor1: N/A
N/A
monitor2: N/A
N/A
monitor0: Start of X-readout
monitor1: Black line indication
monitor2: Dummy line indication
monitor0: Frame start
Pulse indicating the start of X-readout
High during black lines, low during all other lines
High during dummy lines, low during all other lines
Pulse indicating the start of a new frame
Pulse indicating the start of ROT
monitor1: Start of ROT
monitor2: Start of X-readout
monitor0: First line indication
monitor1: Start of ROT indication
monitor2: ROT inactive
Pulse indicating the start of X-readout
High during the first line of each frame, low for all others
Pulse indicating the start of ROT
Low when ROT is active, high outside ROT
High when ROT is active, low outside ROT
Pulse indicating the start of X-readout
Low during X-readout, high outside X-readout
Pulse indicating the start of X-readout for black lines
Pulse indicating the start of X-readout for image lines
Pulse indicating the start of X-readout for dummy lines
monitor0: ROT indication
monitor1: Start of X-readout
monitor2: X-readout inactive
monitor0: Start of X-readout for black lines
monitor1: Start of X-readout for image lines
monitor2: Start of X-readout for dummy lines
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36
PYTHON 480
Sequences of Frame Acquisition with Different
Configurations
Frame dependent configurations require multiple
contexts, which are sync’ed upon a start of a new frame. The
following configurations are context switchable:
When the sequenced readout is not enabled, the first set of
configurations (‘Even configurations’) is applicable. The
second set (‘Odd configurations’) is ignored by the
sequencer.
• FOT program
Table 28. ODD/EVEN CONFIGURATION
• ROT programs (only for regular ROT in Global Shutter
Mode (no muxing for black reference ROT programs))
• Integration Time
Configuration
Even Frames
Odd Frames
Integration
Time
reg_seq_exposure0
reg_seq_exposure1
• Gain (both digital and analog)
FR Length
Mult Timer
Gain Stage 1
reg_seq_fr_length0
reg_seq_fr_length1
• Active ROI Configuration (not the window
reg_seq_mult_timer0 reg_seq_mult_timer1
configuration themselves)
reg_seq_mux_gains reg_seq_mux_gainsw1
w0
When enabled, the sequencer shall automatically select
one set of parameters for the even frames and the other set
of parameters for the odd frames.
This operation mode is enabled by means of the
reg_seq_sequence register and can be used in global shutter
modes.
Gain Stage 2
Digital Gain
reg_seq_afe_gain0
reg_seq_db_gain0
reg_seq_afe_gain1
reg_seq_db_gain1
ROI Active
Configuration
reg_seq_roi_active0 reg_seq_roi_active1
The configurations used for even odd frames are
summarized in Table 28.
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37
PYTHON 480
DATA OUTPUT FORMAT
The PYTHON 480 image sensor can be configured in LVDS
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
output mode, which includes one LVDS output channel
together with an LVDS clock output and an LVDS
synchronization output channel. The PYTHON 480 is also
configurable in a CMOS output configuration, which
includes a 10−bit parallel CMOS output together with a
CMOS clock output and ‘frame valid’ and ‘line valid’
CMOS output signals.
LVDS Interface Mode
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
LVDS Output Channels
The image data output occurs through one LVDS data
channel where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
The one data channel is used to output the image data only.
The sync channel transmits information about the data sent
over the data channel (includes codes indicating black
pixels, normal pixels, and CRC codes).
Frame Format
The frame format is explained by example of the readout
of two (overlapping) windows as shown in Figure 30(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 30 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
NOTE: In Figure 30, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
For additional information on the
synchronization codes, refer to
Application Note AND5001.
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38
PYTHON 480
y1_end
y0_end
y1_start
ROI 1
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Reset
N
Reset
N+1
FOT
FOT
FOT
FOT
Exposure Time N
Exposure Time N+1
Readout Frame N-1
Readout Frame N
Readout
Handling
B
L
ROI
1
B
L
ROI
1
FOT
ROI 0
ROI 0
FS0
FS1
FE1
FS0
FS1
FE1
(b)
Figure 30. LVDS Mode: Frame Sync Codes
Figure 31 shows the detail of a black line readout during global or full−frame readout.
Sequencer
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
Internal State
data channels
sync channel
Training
TR
Training
TR
data channels
sync channel
LS
BL
BL
BL
BL
BL
BL LE
CRC
timeslot
0
timeslot
1
timeslot
157
timeslot
158
timeslot
159
CRC
timeslot
Figure 31. LVDS Mode: Time Line for Black Line Readout
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39
PYTHON 480
Figure 32 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
data channels
sync channel
Training
Training
TR
data channels
sync channel
TR
FS
ID
IMG IMG
IMG
IMG IMG IMG LE
ID
CRC
timeslot
Xstart
timeslot
Xstart + 1
timeslot
Xend - 2
timeslot
Xend - 1
timeslot
Xend
CRC
timeslot
Figure 32. LVDS Mode: Time Line for Single Window Readout (at the start of a frame)
Figure 33 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
line Ys+1
ROT
line Ye
data channels
sync channel
Training
TR
Training
TR
data channels
sync channel
LS
IMG IMG
LS
IDN
IMG
IMG LE
IDN
CRC
IDM
IMG
timeslot
XstartM
timeslot
XstartN
timeslot
XendN
Figure 33. LVDS Mode: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization
Table 29 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable). If more than one window is active at the
same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 29. FRAME SYNCHRONIZATION CODE DETAILS
Sync Word Bit
Position
Register
Address
Default
Value
Description
Frame Sequence Start (FSS). Only sent out when reg_seq_fss_enable is asserted.
Frame Sequence End (FSE). Only sent out when reg_seq_fse_enable is asserted.
Frame start indication
9:7
9:7
9:7
9:7
9:7
9:7
6:0
N/A
N/A
0x4
0x7
0x5
0x6
0x1
0x2
0x2A
N/A
N/A
Frame end indication
N/A
Line start indication
N/A
Line end indication
117[6:0]
These bits indicate that the received sync word is a frame synchronization code. The
value is programmable by a register setting
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40
PYTHON 480
• Window Identification
• Data Classification Codes
Frame synchronization codes are always followed by a
3−bit window identification (bits 2:0). This is an integer
number, ranging from 0 to 7, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 30.
Table 30. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES
Sync Word Bit
Position
Register
Address
Default
Value
Description
9:0
9:0
9:0
9:0
118 [9:0]
119 [9:0]
125 [9:0]
126 [9:0]
0x015
0x035
0x059
0x3A6
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the
image).
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Training Patterns on Data Channels
training patterns are configurable independent of the
During idle periods, the data channels transmit training
patterns, indicated on the sync channel by a TR code. These
training code on the sync channel as shown in Table 31.
Table 31. TRAINING CODE ON SYNC CHANNEL IN
Sync Word Bit
Position
Register
Address
Default
Value
Description
[9:0]
116 [9:0]
0x3A6
Data channel training pattern. The data output channels send out the training pattern,
which can be programmed by a register setting. The default value of the training pattern
is 0x3A6, which is identical to the training pattern indication code on the sync channel.
Cyclic Redundancy Code
indicates how the kernels are organized. The first kernel
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
(kernel [0, 0]) is located in the bottom left corner. The pixel
data is transmitted in order. The figures in the following
paragraphs represent the data order for a non−mirrored
readout (i.e. left−to−right readout).
kernel
(403,607)
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
pixel array
10
9
6
3
2
The polynomial is x + x + x + x + x + x + 1. The
CRC encoder is seeded at the start of a new line and updated
for every (valid) data word received. The CRC seed is
configurable using the crc_seed register. When ‘0’, the CRC
is seeded by all−‘0’; when ‘1’ it is seeded with all−‘1’.
ROI
kernel (x_start,y_start)
kernel
(0,0)
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
0
1
Data Order: LVDS Interface Version
Figure 34. Kernel Organization in Pixel Array
(Top View)
To read out the image data through the output channel, the
pixel array is organized in kernels. The kernel size is two
pixels in x−direction by one pixel in y−direction. Figure 34
www.onsemi.com
41
PYTHON 480
• Subsampling disabled
Figure 35 shows how a kernel is read out. The pixels are
transferred in order, or in ascending order for normal readout
and descending order for mirrored readout.
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel # (even kernel)
pixel # (odd kernel)
0
3
1
2
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 35. P1−SN/SE/FN: Data Output Order when Subsampling is Disabled
• Subsampling on Monochrome Sensor
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
neighboring kernels are combined to a single kernel of
4 pixels in the x−direction and one pixel in the y−direction.
Only the pixels at the even pixel positions inside that kernel
are read out.
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel #
0
2
Figure 36. Data Output Order in Subsampling Mode on a Monochrome Sensor
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42
PYTHON 480
kernels are combined to a single kernel of 4 pixels in the
x−direction and one pixel in the y−direction. Only the pixels
0 and 1 are read out.
• Subsampling on Color Sensor
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernel N−4
kernel N−2
kernel N
kernel N+2
pixel #
0
1
Figure 37. Data Output Order for the LVDS Output Channel in Subsampling Mode on a Color Sensor
CMOS Interface Mode
• The line_valid indication serves the following needs:
♦ While the line_valid indication is asserted, the data
channels contain valid pixel data.
CMOS Output Signals
The image data output occurs through a single 10−bit
parallel CMOS data output. A CMOS clock output, ‘frame
valid’ and ‘line valid’ signal synchronizes the output data.
No windowing information is sent out by the sensor.
♦ The line valid communicates frame timing as it is
asserted at the start of each line and it is de−asserted
at the end of the line. Low periods indicate the idle
time between lines (ROT).
♦ The data channels transmit the calculated CRC code
after each line. This can be detected as the data
words right after the falling edge of the line valid.
Frame Format
Frame timing is indicated by means of two signals:
frame_valid and line_valid.
• The frame_valid indication is asserted at the start of a
new frame and remains asserted until the last line of the
frame is completely transmitted.
Sequencer
Internal State
FOT ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
FOT ROT
black
line Ys
data channels
frame_valid
line_valid
Figure 38. CMOS Mode: Frame Timing Indication
www.onsemi.com
43
x1_sꢀt
(a)
x1_eꢀnd
t
x0_start
x0_
aꢀr
end
PYTHON 480
The frame format is explained with an example of the
readout of two (overlapping) windows as shown in
Figure 39 (a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top. Figure 39
(a) and (b) indicate that, after the FOT is finished, a number
of lines which include information of ‘ROI 0’ are sent out,
starting at position y0_start. When the line at position
y1_start is reached, a number of lines containing data of
‘ROI 0’ and ‘ROI 1’ are sent out, until the line position of
y0_end is reached. Then, only data of ‘ROI 1’ appears on the
data output until line position y1_end is reached. The
line_valid strobe is not shown in Figure 39.
1280 pixels
y1_end
y0_eꢀnꢀd
y1 ꢀstart
ROI1
ROI0
y0 ꢀstart
Reset
N
Reset
Integration Time
Handling
FOT
FOT
FOT
Exposure Time N
Exposure Time N +1
N+1
Readout Frame N
Readout Frame N -1
Readout
Handling
ROI1
ROI1
FOT
ROI0
FOT
ROI0
Frame valid
(b)
Figure 39. CMOS Mode: Frame Format to Read Out Image Data
Black Lines
possible to ‘mute’ the frame and/or line valid indications for
the black lines. Refer to Table 32 for black line, frame_valid
and line_valid settings.
Black pixel data is also sent through the data channels. To
distinguish these pixels from the regular image data, it is
Table 32. BLACK LINE FRAME_VALID AND LINE_VALID SETTINGS
bl_frame
bl_line
_valid_enable
_valid_enable
Description
0x1
0x1
The black lines are handled similar to normal image lines. The frame valid indication is asserted
before the first black line and the line valid indication is asserted for every valid (black) pixel.
0x1
0x0
The frame valid indication is asserted before the first black line, but the line valid indication is not
asserted for the black lines. The line valid indication indicates the valid image pixels only. This
mode is useful when one does not use the black pixels and when the frame valid indication needs
to be asserted some time before the first image lines (for example, to precondition ISP pipelines).
0x0
0x0
0x1
0x0
In this mode, the black pixel data is clearly unambiguously indicated by the line valid indication,
while the decoding of the real image data is simplified.
Black lines are not indicated and frame and line valid strobes remain de−asserted. Note however
that the data channels contains the black pixel data and CRC codes (Training patterns are
interrupted).
www.onsemi.com
44
PYTHON 480
Data order: CMOS Interface Mode
• No Subsampling
To read out the image data through the parallel CMOS
output, the pixel array is divided in kernels. The kernel size
is two pixels in x−direction by one pixel in y−direction.
Figure 34 on page 41 indicates how the kernels are
organized.
Figure 40 shows the pixel sequence of a kernel which is
read out over the single CMOS output channel. The pixels
are transmitted in order or ascending for a normal readout
and descending for a mirrored readout.
The pixel data is transmitted in order. The figures in the
following paragraphs represent the data order for a
non−mirrored readout (i.e. left−to−right readout).
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
pixel #
Figure 40. CMOS Mode: Data Output Order without Subsampling
one pixel in the y−direction. Only the pixels at the even pixel
positions inside that kernel are read out. Figure 41 shows the
data order.
• Subsampling On Monochrome Sensor
To read out the image data with subsampling enabled on
a monochrome sensor, two neighboring kernels are
combined to a single kernel of 4 pixels in the x−direction and
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel #
0
2
Figure 41. CMOS Mode: Data Output Order with Subsampling on a Monochrome Sensor
single kernel of 4 pixels in the x−direction and one pixel in
the y−direction. Figure 42 shows the data order.
• Subsampling On Color Sensor
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
kernel N−4
kernel N−2
kernel N
kernel N+2
pixel #
0
1
Figure 42. CMOS Mode: Data Output Order with Subsampling on a Color Sensor
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45
PYTHON 480
REGISTER MAP
Table 33. REGISTER MAP
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
Status
Status
Chip ID [Block Offset: 0]
0
1
0
1
chip_id
0x5004
0x5004
0x0000
0x0
20484
Chip ID
[15:0]
id
20484
Chip ID
reserved
reserved
Resolution
reserved
chip_configuration
color
0
0
0
0
0
0
Reserved
Reserved
Chip Resolution
Reserved
[3:0]
[9:8]
0x0
[11:10]
0x0
2
2
0x0000
0x0
Chip General Configuration
RW
[0]
Color/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[1]
reserved
reserved
0x0
0x0
0
0
Reserved
Reserved
[15:2]
Reset Generator [Block Offset: 8]
0
8
soft_reset_pll
pll_soft_reset
0x0099
0x9
153
9
PLL Soft Reset Configuration
RW
[3:0]
[7:4]
PLL Reset
0x9: Soft Reset State
others: Operational
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
1
2
9
soft_reset_cgen
cgen_soft_reset
0x0009
0x9
9
9
Clock Generator Soft Reset
RW
RW
[3:0]
Clock Generator Reset
0x9: Soft Reset State
others: Operational
10
soft_reset_analog
mux_soft_reset
0x0999
0x9
2457
9
Analog Block Soft Reset
[3:0]
[7:4]
Column MUX Reset
0x9: Soft Reset State
others: Operational
afe_soft_reset
ser_soft_reset
0x9
0x9
9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
Serializer Reset
0x9: Soft Reset State
others: Operational
PLL [Block Offset: 16]
0 16
power_down
pwd_n
0x0004
0x0
4
0
PLL Configuration
RW
[0]
[1]
[2]
PLL Power Down
’0’: Power Down,
’1’: Operational
enable
bypass
0x0
0x1
0
1
PLL Enable
’0’: disabled,
’1’: enabled
PLL Bypass
’0’: PLL Active,
’1’: PLL Bypassed
1
17
reserved
reserved
reserved
reserved
0x2113
0x13
0x1
8467
19
1
Reserved
Reserved
Reserved
Reserved
RW
[7:0]
[12:8]
[14:13]
0x1
1
www.onsemi.com
46
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Type
I/O [Block Offset: 20]
20
0
config1
0x0000
0x0
0
IO Configuration
RW
[0]
clock_in_pwd_n
reserved
0
0
0
Power down Clock Input
Reserved
[9:8]
[10]
0x0
reserved
0x0
Reserved
PLL Lock Detector [Block Offset: 24]
0
24
pll_lock
lock
0x0000
0x0
0
PLL Lock Indication
PLL Lock Indication
Reserved
Status
RW
[0]
0
2
26
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x2280
0x80
8832
128
2
[7:0]
[10:8]
[14:12]
Reserved
0x2
Reserved
0x2
2
Reserved
3
27
0x3D2D
0x2D
0x3D
15661
45
Reserved
RW
RW
[7:0]
Reserved
[15:8]
61
Reserved
Clock Generator [Block Offset: 32]
32
0
config0
0x2014
0x0
8212
0
Clock Generator Configuration
[0]
[1]
[2]
enable_analog
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
enable_log
select_pll
0x0
0x1
0
1
Enable logic clock
‘0’: disabled,
‘1’: enabled
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
[4]
adc_mode
0x0
0x1
0
1
Set operation mode of CGEN block
‘0’: divide by 5 mode (10-bit mode)
enable_clkgate
Clock gate on master distribution
‘0’: Clock active
‘1’: Clock inactive (gated)
[11:8]
reserved
reserved
0x0
0x2
0
2
Reserved
Reserved
[14:12]
General Logic [Block Offset: 34]
0
34
config0
enable
0x0000
0x0
0
0
Clock Generator Configuration
RW
RW
RW
[0]
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
0
38
reserved
reserved
0x0000
0x0000
0
0
Reserved
Reserved
[15:0]
Image Core [Block Offset: 40]
0 40
image_core_config0
imc_pwd_n
0x0000
0x0
0
0
Image Core Configuration
[0]
[1]
[2]
Image Core Power Down
‘0’: powered down,
‘1’: powered up
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
colbias_enable
image_core_config1
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
1
41
0x085A
2138
Image Core Configuration
RW
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47
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
[3:0]
Register Name
reserved
(Hex)
Default
Description
Type
0xA
10
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[7:4]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x5
0x0
0x1
0x0
0x0
0x0
0x0003
0x1
0x1
0x0
0x0
0x0
0x0508
0x0
0x0
0x0
0x1
0x0
0x0
0x5
0x0
[10:8]
[12:11]
[13]
0
1
0
[14]
0
[15]
0
2
42
3
RW
[0]
[1]
1
1
[6:4]
[10:8]
[15:12]
0
0
0
3
43
1288
0
RW
[0]
[1]
0
[2]
0
[3]
1
[6:4]
[7]
0
0
[11:8]
[15:12]
5
0
AFE [Block Offset: 48]
48
0
power_down
pwd_n
0x0000
0x0
0
0
AFE Configuration
RW
[0]
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
Bias [Block Offset: 64]
0
64
power_down
pwd_n
0x0000
0x0
0
0
Bias Power Down Configuration
RW
RW
[0]
[0]
Power down bandgap
‘0’: powered down,
‘1’: powered up
1
65
configuration
extres
0xF8CB
0x1
63691
1
Bias Configuration
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
[3:1]
[7:4]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x5
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xC
12
[11:8]
[15:12]
0x8
8
0xF
15
2
3
66
67
0x53C8
0x8
21448
RW
RW
[3:0]
[7:4]
8
0xC
12
[14:8]
0x53
0x8788
0x8
83
34696
[3:0]
[7:4]
8
8
0x8
www.onsemi.com
48
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
[11:8]
Register Name
reserved
(Hex)
Default
Description
Type
RW
0x7
7
Reserved
Reserved
[15:12]
reserved
lvds_bias
lvds_ibias
lvds_iref
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x8
8
4
5
68
0x0085
0x5
133
LVDS Bias Configuration
LVDS Ibias
LVDS Iref
[3:0]
[7:4]
5
0x8
8
69
0x0088
0x8
2184
Reserved
RW
[3:0]
[7:4]
8
Reserved
0x8
8
Reserved
[11:8]
0x8
8
Reserved
6
70
0x4111
0x1
16657
Reserved
RW
[3:0]
[7:4]
1
Reserved
0x1
1
Reserved
[11:8]
[15:12]
0x1
1
Reserved
0x4
4
Reserved
7
71
0x9788
0x9788
38792
38792
Reserved
RW
RW
[15:0]
Reserved
Charge Pump [Block Offset: 72]
0
72
configuration
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x3330
0x0
13104
Charge Pump Configuration
Reserved
[0]
[1]
0
0x0
0
Reserved
[2]
0x0
0
Reserved
[6:4]
[10:8]
[14:12]
0x3
3
Reserved
0x3
3
Reserved
0x3
3
Reserved
0
80
0x0000
0x0
0
Reserved
RW
[1:0]
[3:2]
[5:4]
[7:6]
[9:8]
0
Reserved
0x0
0
Reserved
0x0
0
Reserved
0x0
0
Reserved
0x0
0
Reserved
1
81
0x8881
0x8881
34945
34945
Reserved
RW
RW
[15:0]
Reserved
Temperature Sensor [Block Offset: 96]
0
96
enable
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
0
Temperature Sensor Configuration
Reserved
[0]
[1]
reserved
reserved
reserved
reserved
reserved
reserved
offset
0x0
Reserved
[2]
0x0
Reserved
[3]
0x0
Reserved
[4]
0x0
Reserved
[5]
0x0
Reserved
[13:8]
0x0
Temperature Offset (signed)
Temperature Sensor Status
Temperature Readout
Reserved
1
0
97
temp
0x0000
0x00
0x0000
Status
RW
[7:0]
temp
104
reserved
www.onsemi.com
49
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
reserved
(Hex)
Default
Description
Type
[15:0]
0x0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
105
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
0
RW
[1:0]
[5:2]
[7]
0x0
0x0
[9:8]
[13:10]
[15]
0x0
0x0
0x0
2
3
106
107
0x0000
0x0000
0x0000
0x0000
RW
RW
[15:0]
[10:0]
Serializers/LVDS/IO [Block Offset: 112]
112
0
power_down
0x0000
0x0
0
0
LVDS Power Down Configuration
RW
[0]
[1]
[2]
clock_out_pwd_n
Power down for Clock Output.
‘0 ’: powered down,
‘1’: powered up
sync_pwd_n
data_pwd_n
0x0
0x0
0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
Sync Words [Block Offset: 116]
4
116
trainingpattern
trainingpattern
0x03A6
0x3A6
934
934
Data Formating - Training Pattern
RW
[9:0]
Training pattern sent on Data channels during
idle mode. This data is used to perform word
alignment on the LVDS data channels.
5
6
117
118
sync_code0
frame_sync_0
sync_code1
bl_0
0x002A
0x02A
0x0015
0x015
42
42
21
21
LVDS Power Down Configuration
Frame Sync Code LSBs - Even kernels
Data Formating - BL Indication
RW
RW
[6:0]
[9:0]
Black Pixel Identification Sync Code - Even
kernels
7
8
119
120
sync_code2
img_0
0x0035
0x035
53
53
Data Formating - IMG Indication
RW
RW
[9:0]
[9:0]
Valid Pixel Identification Sync Code - Even
kernels
sync_code3
ref_0
0x0025
0x025
37
37
Data Formating - IMG Indication
Reference Pixel Identification Sync Code -
Even kernels
9
121
122
sync_code4
frame_sync_1
sync_code5
bl_1
0x002A
0x02A
0x0015
0x015
42
42
21
21
LVDS Power Down Configuration
Frame Sync Code LSBs - Odd kernels
Data Formating - BL Indication
RW
RW
[6:0]
[9:0]
10
Black Pixel Identification Sync Code -
Odd kernels
11
12
123
124
sync_code6
img_1
0x0035
0x035
53
53
Data Formating - IMG Indication
RW
RW
[9:0]
[9:0]
Valid Pixel Identification Sync Code -
Odd kernels
sync_code7
ref_1
0x0025
0x025
37
37
Data Formating - IMG Indication
Reference Pixel Identification Sync Code -
Odd kernels
www.onsemi.com
50
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
[9:0]
Register Name
sync_code8
(Hex)
0x0059
0x059
Default
89
Description
Data Formating - CRC Indication
CRC Value Identification Sync Code
Data Formating - TR Indication
Training Value Identification Sync Code
Reserved
Type
13
125
RW
crc
89
14
15
126
127
sync_code9
tr
0x03A6
0x3A6
934
934
682
682
RW
RW
[9:0]
reserved
reserved
0x02AA
0x2AA
[9:0]
Reserved
Data Block [Block Offset: 128]
0 128
blackcal
0x4714
0x014
0x7
18196
20
Black Calibration Configuration
Desired black level at output
RW
[7:0]
black_offset
black_samples
[10:8]
7
Black pixels taken into account for black
calibration.
Total samples = 2**black_samples
[14:11]
[15]
reserved
crc_seed
0x8
0x0
8
0
Reserved
CRC Seed
‘0’: All-0
‘1’: All-1
1
129
general_configuration
auto_blackcal_enable
blackcal_offset
0x0001
0x1
1
1
0
0
Black Calibration and Data Formating
Configuration
RW
[0]
Automatic blackcalibration is enabled when 1,
bypassed when 0
[9:1]
[10]
0x00
0x0
Black Calibration offset used when au-
to_black_cal_en = ‘0’.
blackcal_offset_dec
blackcal_offset is added when 0, subtracted
when 1
[11]
[12]
[13]
[14]
reserved
reserved
reserved
ref_mode
0x0
0x0
0x0
0x0
0
0
0
0
Reserved
Reserved
Reserved
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding data
channel
[15]
ref_bcal_enable
0x0
0
Enable black calibration on reference lines
‘0’: Disabled
‘1’: Enabled
2
130
general_configuration1
0x000F
0x1
15
1
Data Formating - Training Pattern
RW
bl_frame_valid_en-
able
Assert frame_valid for black lines when ‘1’,
gate frame_valid for black lines when ‘0’.
Parallel output mode only.
[0]
[1]
bl_line_valid_enable
0x1
0x1
0x1
0x0
1
1
1
0
Assert line_valid for black lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
ref_frame_valid_en-
able
Assert frame_valid for ref lines when ‘1’, gate
frame_valid for black lines when ‘0’.
Parallel output mode only.
[2]
[3]
ref_line_valid_enable
frame_valid_mode
Assert line_valid for ref lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
[4]
Behaviour of frame_valid strobe between
overhead lines when [0] and/or [1] is
deasserted:
‘0’: retain frame_valid deasserted between
lines
‘1’: assert frame_valid between lines
[5]
invert_bitstream
0x0
0
Negative Image
‘0’: Normal
‘1’: Negative
www.onsemi.com
51
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
(Hex)
Default
Description
Clock−Data Relation
Type
[8]
data_negedge
0x0
0
‘0’: data is clocked out on the rising edge of
the related clock
‘1’: data is clocked out on the falling edge of
the related clock
[9]
reserved
0x0
0
0
0
Reserved
8
136
blackcal_error0
blackcal_error[1:0]
0x0000
0x0000
Black Calibration Status
Status
[1:0]
Black Calibration Error. This flag is set when
not enough black samples are availlable.
Black Calibration shall not be valid.
12
16
140
144
reserved
0x0000
0x0000
0x0010
0x0
0
Reserved
RW
RW
[15:0]
reserved
0
Reserved
test_configuration
testpattern_en
inc_testpattern
16
0
Data Formating Test Configuration
Insert synthesized testpattern when ‘1’
[0]
[1]
0x0
0
Incrementing testpattern when ‘1’, constant
testpattern when ’0’
[2]
[3]
prbs_en
0x0
0x0
0
0
Insert PRBS when ‘1’
frame_testpattern
Frame test patterns when ‘1’, unframed
testpatterns when ‘0’
[13:4]
testpattern
0x1
1
Testpattern used when testpatterns_en = ‘1’
AEC [Block Offset: 160]
0 160
configuration
enable
0x0010
0x0
16
0
AEC Configuration
RW
[0]
[1]
[2]
[3]
AEC Enable
restart_filter
freeze
0x0
0
Restart AEC filter
0x0
0
Freeze AEC filter and enforcer gains
pixel_valid
0x0
0
Use every pixel from channel when 0, every
4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0
1
161
intensity
0x60B8
0xB8
24760
184
24
AEC Configuration
Target average intensity
Reserved
RW
[9:0]
desired_intensity
reserved
[15:10]
0x018
0x0080
0x80
2
3
4
5
162
163
164
165
red_scale_factor
red_scale_factor
128
128
Red Scale Factor
RW
RW
RW
RW
[9:0]
[9:0]
[9:0]
[9:0]
[15:0]
Red Scale Factor
3.7 unsigned
green1_scale_factor
green1_scale_factor
0x0080
0x80
128
128
Green1 Scale Factor
Green1 Scale Factor
3.7 unsigned
green2_scale_factor
green2_scale_factor
0x0080
0x80
128
128
Green2 Scale Factor
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
blue_scale_factor
0x0080
0x80
128
128
Blue Scale Factor
Blue Scale Factor
3.7 unsigned
6
7
166
167
reserved
reserved
reserved
reserved
reserved
reserved
0x03FF
0x03FF
0x0800
0x0
1023
1023
2048
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
[1:0]
[3:2]
0x0
0
[15:4]
0x080
128
www.onsemi.com
52
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
min_exposure
min_exposure
min_gain
(Hex)
0x0001
0x0001
0x0800
0x0
Default
Description
Minimum Exposure Time
Type
8
168
1
RW
[15:0]
1
Minimum Exposure Time
Minimum Gain
9
169
2048
0
RW
[1:0]
[3:2]
min_mux_gain
min_afe_gain
min_digital_gain
Minimum Column Amplifier Gain
Minimum AFE PGA Gain
0x0
0
[15:4]
0x080
128
Minimum Digital Gain
5.7 unsigned
10
11
170
171
max_exposure
max_exposure
max_gain
0x03FF
0x03FF
0x1001
0x1
1023
1023
4097
1
Maximum Exposure Time
Maximum Exposure Time
Maximum Gain
RW
RW
[15:0]
[1:0]
[3:2]
max_mux_gain
max_afe_gain
max_digital_gain
Maximum Column Amplifier Gain
Maximum AFE PGA Gain
0x0
0
[15:4]
0x100
256
Maximum Digital Gain
5.7 unsigned
12
172
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
total_pixels0
total_pixels[15:0]
0x0083
0x083
0x00
131
131
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AEC Status
RW
[7:0]
[13:8]
[15:14]
0x0
0
13
14
173
174
0x2824
0x024
0x028
0x2A96
0x6
10276
36
RW
RW
[7:0]
[15:8]
40
10902
6
[3:0]
[7:4]
0x9
9
[11:8]
[15:12]
0xA
10
0x2
2
15
16
17
18
19
20
21
24
175
176
177
178
179
180
181
184
0x0080
0x080
0x00F1
0xF1
128
128
241
241
256
256
128
128
170
170
256
256
341
341
0
RW
RW
RW
RW
RW
RW
RW
Status
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[15:0]
0x0100
0x100
0x0080
0x080
0x00AA
0x0AA
0x0100
0x100
0x0155
0x155
0x0000
0x0000
0
Total number of pixels sampled for Average,
LSB
25
185
total_pixels1
0x0000
0x0
0
0
AEC Status
Status
[7:0]
total_pixels[23:16]
Total number of pixels sampled for Average,
MSB
www.onsemi.com
53
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
average_status
average
(Hex)
0x0000
0x000
0x0
Default
Description
Type
26
186
0
ASE Status
Status
[9:0]
[12]
0
0
0
0
0
0
0
0
AEC Average Status
AEC Average Lock Status
ASE Status
avg_locked
exposure_status
exposure
27
28
187
188
0x0000
0x0000
0x0000
0x0
Status
Status
[15:0]
AEC Exposure Status
ASE Status
gain_status
mux_gain
[1:0]
[3:2]
AEC MUX Gain Status
AEC AFE Gain Status
afe_gain
0x0
[15:4]
digital_gain
0x000
AEC Digital Gain Status
5.7 unsigned
29
189
reserved
reserved
reserved
0x0000
0x000
0x0
0
0
0
Reserved
Reserved
Reserved
Status
RW
[12:0]
[13]
Sequencer [Block Offset: 192]
0 192
general_configuration
enable
0x0002
0x0
2
0
Sequencer General Configuration
[0]
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
fast_startup
0x1
1
Fast startup
‘0’: First frame is full frame (blanked out)
‘1’: Reduced startup time
[2]
[3]
[4]
reserved
0x0
0x0
0x0
0
0
0
Reserved
Reserved
reserved
triggered_mode
Triggered Mode Selection
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection
‘0’: master,
‘1’: slave
[6]
[7]
reserved
0x0
0x0
0
0
Reserved
subsampling
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
[8]
reserved
0x0
0x0
0
0
Reserved
[10]
roi_aec_enable
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
[14]
monitor_select
reserved
0x0
0x0
0x0
0
0
0
Control of the monitor pins
Reserved
[15]
sequence
Enable a sequenced readout with different
parameters for even and odd frames
2
194
integration_control
reserved
0x00E4
0x0
228
0
Integration Control
Reserved
RW
[0]
[1]
[2]
reserved
0x0
0
Reserved
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[3]
[4]
reserved
0x0
0x0
0
0
Reserved
int_priority
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over frame
readout
www.onsemi.com
54
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
halt_mode
(Hex)
Default
Description
Type
[5]
0x1
1
The current frame will be completed when the
sequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately when
disabled, without finishing the current frame.
[6]
[7]
fss_enable
fse_enable
0x1
0x1
1
1
Generation of Frame Sequence Start Sync
code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
Generation of Frame Sequence End Sync
code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
[8]
[9]
reverse_y
0x0
0x0
0x0
0
0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
reverse_x
Reverse readout (X−direction)
‘0’: left to right
‘1’: right to left
[11:10]
subsampling_mode
Subsampling mode
“00”: Subsampling in x and y (VITA
compatible)
“01”: Subsampling in x, not y
“10”: Subsampling in y, not x
“11”: Subsampling in x an y
[13:12]
[14]
reserved
0x0
0
0
0
1
1
Reserved
reserved
0x0
Reserved
[15]
reserved
0x0
Reserved
3
5
195
197
roi_active0_0
roi_active0
0x0001
0x01
Active ROI Selection
RW
RW
[3:0]
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[3] Roi3 Active
black_lines
black_lines
0x0104
0x04
260
4
Black Line Configuration
[7:0]
Number of black lines. Minimum is 1.
Range 1-255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1-31: blank 1-31 lines
6
7
198
199
init_reset_length
init_reset_length
0x0040
0x0040
64
64
Initial Reset Length
RW
RW
[15:0]
[15:0]
Initial Reset Length in Fast Startup Mode
(reg_sec_fast_startup = 0x1)
mult_timer0
mult_timer0
0x0001
0x0001
1
1
Exposure/Frame Rate Configuration
Mult Timer (Global shutter only)
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length
8
9
200
201
fr_length0
fr_length0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
RW
RW
[15:0]
[15:0]
Frame/Reset length (Global shutter only)
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer
exposure0
exposure0
0x0000
0x0000
0
0
Exposure/Frame Rate Configuration
Exposure Time
Granularity defined by mult_timer
10
11
202
203
reserved
reserved
reserved
reserved
0x0000
0x0000
0x0000
0x0000
0
0
0
0
Reserved
Reserved
Reserved
Reserved
RW
RW
[15:0]
[15:0]
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55
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
gain_configuration0
mux_gainsw0
(Hex)
0x01E1
0x01
Default
Description
Gain Configuration
Type
12
204
481
1
RW
[4:0]
[12:5]
[13]
Column Gain Setting
afe_gain0
0xF
15
0
AFE Programmable Gain Setting
gain_lat_comp
0x0
Postpone gain update by 1 frame when ‘1’ to
compensate for exposure time updates
latency.
Gain is applied at start of next frame if ‘0’
13
14
205
206
digital_gain
0x0080
128
Gain Configuration
RW
RW
_configuration0
[11:0]
db_gain0
0x080
0x037A
0x1
128
890
1
Digital Gain
sync_configuration
sync_black_lines
Synchronization Configuration
[1]
[3]
[4]
[5]
[6]
Update of black_lines will not be sync’ed at start
of frame when ‘0’
sync_exposure
sync_gain
0x1
0x1
0x1
0x1
1
1
1
1
Update of exposure will not be sync’ed at start of
frame when ‘0’
Update of gain settings (gain_sw, afe_gain) will
not be sync’ed at start of frame when ‘0’
sync_roi
Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’
sync_ref_lines
blank_roi_switch
Update of ref_lines will not be sync’ed at start of
frame when ‘0’
[8]
[9]
0x1
0x1
1
1
Blank first frame after ROI switching
blank
_subsampling_ss
Blank first frame after subsampling mode
‘0’: No blanking
‘1’: Blanking
[10]
exposure_sync_mode
0x0
0
When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure
configurations sync is disabled (continuously
syncing). This mode is only relevant for Trig-
gered Global - master mode, where the ex-
posure configurations are sync’ed at the start
of exposure rather than the start of FOT. For
all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
15
16
207
208
ref_lines
ref_lines
0x0000
0x00
0
0
Reference Line Configuration
RW
RW
[7:0]
Number of Reference Lines
0-255
reserved
reserved
reserved
reserved
reserved
reserved
xsm_delay
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0xC900
0x00
0xC9
0x0004
0x0
51456
Reserved
[7:0]
0
Reserved
[15:8]
201
4
Reserved
17
19
209
211
Reserved
RW
RW
[0]
[2]
0
Reserved
0x1
1
Reserved
[15:8]
0x00
0x0049
0x1
0
Delay between ROT end and X−readout
Reserved
73
1
[0]
[1]
Reserved
0x0
0
Reserved
[2]
0x0
0
Reserved
[3]
0x1
1
Reserved
[6:4]
[15:8]
0x4
4
Reserved
0x0
0
Reserved
20
212
0x0000
0x0000
0
Reserved
RW
[9:0]
0
Reserved
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56
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
213
Bit Field
Register Name
reserved
(Hex)
Default
Description
Type
RW
[15]
0x00
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
21
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x025F
0x025F
0x0100
0x00
0x191F
0x1
607
607
256
0
[9:0]
[7:0]
22
214
RW
23
215
6431
1
RW
[0]
[1]
0x1
1
[2]
0x1
1
[3]
0x1
1
[4]
0x1
1
[5]
0x0
0
[6]
0x0
0
[8]
0x1
1
[9]
0x0
0
[10]
[11]
[12]
[13]
[14]
0x0
0
0x1
1
0x1
1
0x0
0
0x0
0
24
25
26
27
28
29
216
217
218
219
220
221
0x0000
0x00
0
RW
RW
RW
RW
RW
RW
[6:0]
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x4848
0x48
18504
72
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[6:0]
[14:8]
0x48
72
0x4848
0x48
18504
72
[6:0]
[14:8]
0x48
72
0x005C
0x05C
0x00
92
[6:0]
92
[14:8]
0
0x3624
0x24
13860
36
[6:0]
[14:8]
0x36
54
0x0036
0x36
54
[6:0]
54
[14:8]
0x0
0
30
32
0x0
RW
RW
[14:8]
0x0
0
224
0x3E07
0x7
15879
[3:0]
[7:4]
[8]
7
0
0
0x00
0x0
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57
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
[9]
Register Name
reserved
(Hex)
Default
Description
Type
0x1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[10]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
roi_active0_1
roi_active1
0x1
1
[11]
0x1
1
[12]
0x1
1
[13]
0x1
1
33
34
35
225
226
227
0x5EF1
0x11
0x17
0x17
0x0
24305
RW
RW
RW
[4:0]
[9:5]
17
23
[14:10]
[15]
23
0
0x6000
0x00
0x00
0x18
0x0
24576
[4:0]
[9:5]
0
0
24
0
0
0
0
0
0
0
1
1
[14:10]
[15]
0x0000
0x0
[0]
[1]
[2]
[3]
[4]
0x0
0x0
0x0
0x0
36
228
0x0001
0x01
Active ROI Selection
RW
[3:0]
Active ROI Selection
[0] ROI0 Active
[1] ROI1 Active
[2] ROI2 Active
[3] ROI3 Active
38
39
40
41
42
43
230
231
232
233
234
235
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0001
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x01E3
0x03
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
1
0
0
0
0
0
0
0
0
483
3
[4:0]
[12:5]
0xF
15
128
128
0
44
47
58
236
239
250
0x0080
0x080
0x0000
0x0
RW
RW
RW
[11:0]
[1:0]
[4:0]
0
0x1081
0x01
4225
1
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58
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
[9:5]
Register Name
reserved
(Hex)
Default
Description
Type
RW
0x04
4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[14:10]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x04
0x030F
0xF
4
59
251
783
15
[7:0]
[15:8]
0x3
3
60
252
0x0601
0x1
1537
1
RW
[7:0]
[15:8]
0x6
6
61
253
roi_aec_configura-
tion0
0xC900
51456
AEC ROI Configuration
RW
[7:0]
x_start
0x00
0x0C9
0x9700
0x00
0x97
0x00C4
0x0
0
AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 8..1)
[15:8]
x_end
201
0
AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 8..1)
62
63
254
255
roi_aec_configura-
tion1
AEC ROI Configuration
RW
RW
[7:0]
y_start
0
AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 9..2)
[15:8]
x_end
151
0
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 9..2)
roi_aec_configura-
tion2
AEC ROI Configuration
[0]
[2]
x_start(0)
0
AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bit 0)
x_end(0)
0x1
1
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bit 0)
[5:4]
[7:6]
y_start(1:0)
y_end(1:0)
0x0
0
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 1..0)
0x3
3
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 1..0)
Sequencer ROI [Block Offset: 256]
0
1
2
3
4
5
256
257
258
259
260
261
roi0_configuration0
x_start
0xC900
0x00
51456
0
ROI Configuration
RW
RW
RW
RW
RW
RW
[7:0]
ROI 0 − X Start Configuration (bits 8..1)
ROI 0 − X End Configuration (bits 8..1)
ROI Configuration
[15:8]
x_end
0xC9
201
38656
0
roi0_configuration1
y_start
0x9700
0x00
[7:0]
ROI 0 − Y Start Configuration (bits 9..2)
ROI 0 − Y End Configuration (bits 9..2)
ROI Configuration
[15:8]
y_end
0x97
151
51456
0
roi1_configuration0
x_start
0xC900
0x00
[7:0]
ROI 1 − X Start Configuration (bits 8..1)
ROI 1 − X End Configuration (bits 8..1)
ROI Configuration
[15:8]
x_end
0xC9
201
38656
0
roi1_configuration1
x_start
0x9700
0x00
[7:0]
ROI 1 − Y Start Configuration (bits 9..2)
ROI 1 − Y End Configuration (bits 9..2)
ROI Configuration
[15:8]
x_end
0x97
151
51456
0
roi2_configuration0
x_start
0xC900
0x00
[7:0]
ROI 2 − X Start Configuration (bits 8..1)
ROI 2 − X End Configuration (bits 8..1)
ROI Configuration
[15:8]
x_end
0xC9
201
38656
0
roi2_configuration1
y_start
0x9700
0x00
[7:0]
ROI 2 − Y Start Configuration (bits 9..2)
ROI 2 − Y End Configuration (bits 9..2)
[15:8]
y_end
0x97
151
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59
PYTHON 480
Table 33. REGISTER MAP (continued)
Address
Default
Offset
Address
Bit Field
Register Name
roi3_configuration0
x_start
(Hex)
0xC900
0x00
0xC9
0x9700
0x00
0x97
0xC4C4
0x0
Default
Description
ROI Configuration
Type
6
262
51456
RW
[7:0]
0
ROI 3 − X Start Configuration (bits 8..1)
ROI 3 − X End Configuration (bits 8..1)
ROI Configuration
[15:8]
x_end
201
7
8
263
264
roi3_configuration1
y_start
38656
RW
RW
[7:0]
0
ROI 3 − Y Start Configuration (bits 9..2)
ROI 3 − Y End Configuration (bits 9..2)
ROI Configuration
[15:8]
y_end
151
roi_configuration_lsb0
x_start0(0)
50372
[0]
[2]
0
ROI 0 − X Start Configuration (bit 0)
ROI 0 − X End Configuration (bit 0)
ROI 0 − Y Start Configuration (bits 1..0)
ROI 0 − Y End Configuration (bits 1..0)
ROI 1 − X Start Configuration (bit 0)
ROI 1 − X End Configuration (bit 0)
ROI 1 − Y Start Configuration (bits 1..0)
ROI 1 − Y End Configuration (bits 1..0)
ROI Configuration
x_end0(0)
0x1
1
[5:4]
[7:6]
[8]
y_start0(1:0)
y_end0(1:0)
x_start1(0)
0x0
0
0x3
3
0x0
0
[10]
x_end1(0)
0x1
1
[13:12]
[15:14]
y_start1(1:0)
y_end1(1:0)
roi_configuration_lsb1
x_start0(0)
0x0
0
0x3
3
9
265
0xC4C4
0x0
50372
RW
[0]
[2]
0
1
0
3
0
1
0
3
ROI 2 − X Start Configuration (bit 0)
ROI 2 − X End Configuration (bit 0)
ROI 2 − Y Start Configuration (bits 1..0)
ROI 2 − Y End Configuration (bits 1..0)
ROI 3 − X Start Configuration (bit 0)
ROI 3 − X End Configuration (bit 0)
ROI 3 − Y Start Configuration (bits 1..0)
ROI 3 − Y End Configuration (bits 1..0)
x_end0(0)
0x1
[5:4]
[7:6]
[8]
y_start0(1:0)
y_end0(1:0)
x_start1(0)
0x0
0x3
0x0
[10]
x_end1(0)
0x1
[13:12]
[15:14]
y_start1(1:0)
y_end1(1:0)
0x0
0x3
Sequencer ROI [Block Offset: 384]
0
384
reserved
reserved
…
Reserved
Reserved
…
RW
RW
RW
[15:0]
…
…
…
…
95
479
reserved
reserved
Reserved
Reserved
[15:0]
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60
PYTHON 480
PACKAGE INFORMATION
Pin List
The LVDS I/Os comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 1.8 V signal level.
Table 34. PIN LIST
Pin Map
A1
B1
C1
D1
E1
F1
Pin Name
VDD_PIX
I/O Type
Supply
Supply
CMOS
CMOS
Analog
Analog
Analog
Analog
Supply
Supply
CMOS
Supply
Supply
CMOS
Supply
Analog
CMOS
CMOS
CMOS
Supply
Analog
CMOS
CMOS
CMOS
CMOS
Analog
CMOS
CMOS
CMOS
CMOS
CMOS
Supply
Supply
CMOS
Supply
Supply
CMOS
CMOS
Direction
Description
Pixel Array Supply
3.3 V Supply
VDD_33
MONITOR0
MONITOR1
IBIAS_MASTER
CP_RESPD
CP_CALIB
MBSINOUT_1
VDD_18
Output
Output
I/O
Monitor Output #0
Monitor Output #1
Master Bias Reference. Connect with 47kOhm to VSS_33
For Test Only − Do not connect
For Test Only − Do not connect
For Test Only − Do not connect
1.8 V Supply
Output
Output
I/O
G1
H1
A2
B2
C2
D2
E2
F2
VSS_COLPC
SCAN_EN
VSS_18
Pixel Array Ground
Input
For Test Only − Connect to VSS_18
1.8 V Ground
VSS_33
3.3 V Ground
MONITOR2
VSS_33
Output
Monitor Output #2
G2
H2
A3
B3
C3
G3
H3
A4
B4
C4
G4
H4
A5
B5
C5
G5
H5
A6
B6
C6
G6
H6
A7
B7
3.3 V Ground
MBSINOUT_1
TR2
I/O
For Test Only − Do not connect
Connect to VSS_18
Input
Input
Input
TR1
Connect to VSS_18
TRIGGER0
VDD_33
Trigger Input #0
3.3 V Supply
MBSINOUT_2
SS_N
I/O
For Test Only − Do not connect
SPI Slave Select (Active Low)
SPI Clock
Input
SCK
Input
RESET_N
MISO
Input
Sensor Reset (Active Low)
SPI Master In − Slave Out
For Test Only − Do not connect
Frame Valid Output
Output
Output
Output
Output
Output
Input
CP_SEL_SAMPLE
FRAME_VALID
LINE_VALID
DOUT9
Line Valid Output
Data Output #9
MOSI
SPI Master Out − Slave In
For Test Only − Connect to VSS_18
Pixel Array Ground
TEST_ENABLE
VSS_COLPC
VDD_PIX
DOUT8
Input
Pixel Array Supply
Output
Data Output #8
VSS_18
1.8 V Ground
VREF_BOTPLATE
DOUT7
Input
Output
Output
1.8 V Supply for Sample and Hold
Data Output #7
DOUT6
Data Output #6
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61
PYTHON 480
Table 34. PIN LIST (continued)
Pin Map
C7
Pin Name
DOUT5
I/O Type
CMOS
Supply
Supply
CMOS
CMOS
CMOS
Supply
Supply
CMOS
CMOS
CMOS
CMOS
Supply
Supply
Supply
LVDS
Direction
Description
Output
Data Output #5
1.8 V Ground
3.3 V Ground
Clock Output
G7
VSS_18
H7
VSS_33
A8
CLK_OUT
DOUT4
Output
Output
Output
B8
Data Output #4
Data Output #3
1.8 V Ground
3.3 V Ground
Data Output #2
Data Output #0
Data Output #1
C8
DOUT3
G8
VSS_18
H8
VSS_33
A9
DOUT2
Output
Output
Output
Input
B9
DOUT0
C9
DOUT1
G9
CLK_PLL
VDD_18
Reference Clock Input for PLL
1.8 V Supply
H9
A10
B10
C10
D10
E10
F10
G10
H10
A11
B11
C11
D11
E11
F11
G11
H11
VDD_18
1.8 V Supply
VDD_PIX
CLOCK_OUTN
DOUTN
Pixel Array Supply
Output
Output
Output
Input
LVDS Clock Output (Negative)
LVDS Data Output (Negative)
LVDS Sync Channel Output (Negative)
LVDS Clock Input (Negative)
Lock Detect Output
LVDS
SYNCN
LVDS
LVDS_CLOCK_INN
LOCK_DETECT
VDD_33
LVDS
CMOS
Supply
Supply
LVDS
Output
3.3 V Supply
VSS_COLPC
CLOCK_OUTP
DOUTP
Pixel Array Ground
Output
Output
Output
Input
LVDS Clock Output (Positive)
LVDS Data Output (Positive)
LVDS Sync Channel Output (Positive)
LVDS Clock Input (Positive)
3.3 V Supply
LVDS
SYNCP
LVDS
LVDS_CLOCK_INP
VDD_33
LVDS
Supply
Supply
Supply
VSS_18
1.8 V Ground
VDD_33
3.3 V Supply
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62
PYTHON 480
Mechanical Specifications
Mechanical Specifications
Symbol
Min
6105
4905
631.2
100
Typ
6130
4930
691.2
130
561.2
445
250
67
Max
6155
4955
751.2
160
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Package Body
Package Body Dimension X
Package Body Dimension Y
Package Height
A
B
Dimensions (Top View,
Bumps down, with Pin
A1 top left corner)
C
Ball Height
C1
C2
C3
D
Package Body Thickness
Thickness fo Glass surface to wafer
Ball Diameter
516.2
425
606.2
465
220
280
Total Pin Count
N
Pin Count X−axis
N1
N2
J1
J2
S1
S2
11
Pin Count Y−axis
8
Pins Pitch X−axis
500
500
565
715
0
Pins Pitch Y−axis
Edge to Pin Center Distance along X
Edge to Pin Center Distance along Y
535
685
595
745
Optical center referenced from package
center (X−dir)
Optical center referenced from package
center (Y−dir)
−175
mm
Glass Lid
Glass Thickness
400
mm
g
Mechanical shock
Vibration
JESD22−B104C; Condition G
JESD22−B103B; Condition 1
2000
2000
Hz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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63
PYTHON 480
Pixel (0,0)
Figure 43. Mechanical Diagram
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64
PYTHON 480
Package Drawing
Figure 44. Package Drawing for the ODCSP67 Package
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65
PYTHON 480
Packing and Tray Specification
The PYTHON480 packing specification with ON Semiconductor packing labels is packed as follows:
Figure 45. Tray Drawing
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66
PYTHON 480
Figure 46. Pin 1 Location
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67
PYTHON 480
Glass Lid
The PYTHON 480 image sensors use a glass lid without
any coatings. Figure 44 shows the transmission
characteristics of the glass lid.
optical path when color devices are used. (source:
http://www.pgo−online.com).
As shown in Figure 42, no infrared attenuating color filter
glass is used. Use of an IR cut filter is recommended in the
Figure 47. Transmission Characteristics of the Glass Lid
Protective Foil
The sensor is delivered with protective foil that is intended
to be removed after assembly. The dimensions of the foil are
as illustrated in Figure 48 with tab aligned left center with
Pin A1 to the bottom left.
(units in mm)
Figure 48. Dimensions of the Protective Foil
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68
PYTHON 480
SPECIFICATIONS AND USEFUL REFERENCES
The following references are available to customers under
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology
(TND6116/D) from www.onsemi.com.
NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
• Product Acceptance Criteria
• Product Qualification Report
• PYTHON Developer’s Guide AND9362/D
Useful References
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
Return Material Authorization (RMA)
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
ON Semiconductor and
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