NOIP1SE016KA-GTI [ONSEMI]
CMOS 图像传感器，16.8 MP，全局快门;
| 型号： | NOIP1SE016KA-GTI |
| 厂家： | 
ONSEMI |
| 描述： | CMOS 图像传感器，16.8 MP，全局快门 传感器 图像传感器 |
| 文件： | 总87页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NOIP1SN025KA,
NOIP1SN016KA,
NOIP1SN012KA,
NOIP1SN010KA
PYTHON 25K/16K/12K/10K
Global Shutter CMOS Image
Sensors
www.onsemi.com
Features
• A Pin-compatible Family with Multiple Resolutions:
♦ 25K = 5120 x 5120 Active Pixels
♦ 16K = 4096 x 4096 Active Pixels
♦ 12K = 4096 x 3072 Active Pixels
♦ 10K = 3840 x 2896 Active Pixels
• 4.5 mm x 4.5 mm Low Noise Global Shutter Pixels with
In-pixel Correlated Double Sampling (CDS)
• APS−H Optical Format (32.6 mm Diagonal) for 25K
• Monochrome (SN), Color (SE) and NIR (FN)
• Random Programmable Region of Interest (ROI) Readout
• Pipelined and Triggered Global Shutter
• On-chip Fixed Pattern Noise (FPN) Correction
• 10-bit Analog-to-Digital Converter (ADC)
• 32 Low-voltage Differential Signaling (LVDS) High-speed
Serial Outputs
• Serial Peripheral Interface (SPI)
• High-speed: 80 Frames per Second (fps) at 25 Mpix
• 4.6 W Power Dissipation at Full Resolution, x32 LVDS
Mode
Figure 1. PYTHON XK Photograph
Applications
• Machine Vision
• Motion Monitoring
• Intelligent Traffic Systems (ITS)
• Pick and Place Machines
• Inspection
• Operational Range: −40°C to +85°C
• 355-pin mPGA Package
• Metrology
• These Devices are Pb−Free and are RoHS Compliant
Description
The PYTHON xK family of CMOS image sensors provide high resolution with very high bandwidth (up to 80 frame per
second readout for 25 megapixel readout) in a pin−compatible family of devices.
The high sensitivity 4.5 mm pixels support both pipelined and triggered global shutter readout modes. The sensor also
supports correlated double sampling (CDS) readout in global shutter mode, reducing noise and increasing dynamic range.
The sensor is programmed using a four−wire serial peripheral interface. Black level can be calibrated automatically, or
adjusted using a user programmable offset. The sensor also supports readout of up to 32 separate regions of interest (ROI) to
increase frame rate. Image data is accessed through 32, 16, 8, or 4 LVDS channels, each running at 720 Mbps, and a separate
synchronization channel is provided to facilitate image reconstruction.
The PYTHON xK family is packaged in a 355-pin mPGA package and is available in a monochrome, Bayer color, and
extended near−infrared (NIR) configurations.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
September, 2015 − Rev. 0
NOIP1SN025KA/D
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
ORDERING INFORMATION
Part Number
NOIP1SN025KA-GDI
NOIP1SE025KA-GDI
NOIP1FN025KA-GDI
NOIP1SN016KA-GDI
NOIP1SE016KA-GDI
NOIP1FN016KA-GDI
NOIP1SN012KA-GDI
NOIP1SE012KA-GDI
NOIP1FN012KA-GDI
NOIP1SN010KA-GDI
NOIP1SE010KA-GDI
NOIP1FN010KA-GDI
Family
Description
Package
Product Status
PYTHON 25K
25 MegaPixel, LVDS mono micro lens
25 MegaPixel, LVDS color micro lens
25 MegaPixel, LVDS mono micro lens, NIR
16 MegaPixel, LVDS mono micro lens
16 MegaPixel, LVDS color micro lens
16 MegaPixel, LVDS mono micro lens, NIR
12 MegaPixel, LVDS mono micro lens
12 MegaPixel, LVDS color micro lens
12 MegaPixel, LVDS mono micro lens, NIR
10 MegaPixel, LVDS mono micro lens
10 MegaPixel, LVDS color micro lens
10 MegaPixel, LVDS mono micro lens, NIR
PYTHON 16K
PYTHON 12K
PYTHON 10K
355−pin
mPGA
Production
The P1−SN/SE/FN base part is used to reference the mono, color and NIR enhanced versions of the LVDS interface. More
details on the part number coding can be found at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Package Mark
Side 1 near Pin 1: NOIP1xx0RRKA−GDI where xx denotes mono micro lens (SN) or color micro lens (SE) or NIR mono
micro lens (FN), RR is the resolution of the sensor in MP (25, 16, 12 or 10)
Side 2: AWLYYWW, where AWL is Production lot traceability, and YYWW is the 4−digit date code
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
SPECIFICATIONS
Key Specifications
Table 1. GENERAL SPECIFICATIONS
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Parameter
Pixel Type
Specification
Parameter
Active Pixels
Specification
Global shutter pixel architecture
25K: 5120 (H) x 5120 (V)
16K: 4096 (H) x 4096 (V)
12K: 4096 (H) x 3072 (V)
10K: 3840 (H) x 2896 (V)
Shutter Type
Pipelined and triggered global
shutter
Optical Format
25K: APS−H
16K: APS−H
12K: 4/3”
Pixel Size
4.5 mm x 4.5 mm
-
-
Conversion Gain
Temporal Noise
Responsivity at 550 nm
0.085 LSB10/e , 130 mV/e
10K: 4/3”
-
< 14 e (Non−Zero ROT, 1x gain)
5.8 V/lux.s
Frame Rate at Full
Resolution
80 frames per second @ 25K
120 frames per second @ 16K
160 frames per second @ 12K
175 frames per second @ 10K
Parasitic Light
< 1/5000
Sensitivity (PLS)
Master Clock
Windowing
360 MHz
-
Full Well Charge
> 12000 e
32 Randomly programmable
windows. Normal, sub-sampled
and binned readout modes
Quantum Efficiency
(QE) x FF
50% at 550 nm
(Note 1)
ADC Resolution
LVDS Outputs
Data Rate
10-bit
(Note 2)
Pixel FPN
< 0.9 LSB10
32 data + 1 sync + 1 clock
32 x 720 Mbps
4.6 W
(Note 2)
PRNU
< 1%
MTF
68% @ 535 nm − X−dir & Y−dir
68% @ 535 nm − X−dir & Y−dir
(NIR)
Power Consumption
Package Type
Color
355 mPGA
-
PSNL @ 20°C
(t_int = 30 ms)
91 LSB10/s, 1100 e /s
RGB color, mono
1. The ADC is 11-bit, down-scaled to 10-bit. The PYTHON XK uses
a larger word-length internally to provide 10-bit on the output.
-
Dark signal @ 20°C
3.9 e /s, 0.33 LSB10/s
Dynamic range
59 dB
41 dB
Signal-to-Noise
Ratio (SNR max)
2. Only includes high−frequency component
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 3. RECOMMENDED OPERATING RATINGS (Note 3)
Symbol
Description
Operating temperature range
Min
Max
Units
T
J
−40
+85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 4)
Symbol
Parameter
ABS rating for 1.0 V supply
Min
–0.5
–0.5
–0.5
–0.5
–0.5
0
Max
1.2
2.2
4.3
4.6
5.0
150
85
Units
V
ABS (1.0 V supply)
ABS (1.8 V supply group)
ABS (3.3 V supply group)
ABS (4.2 V supply)
ABS (4.5 V supply)
ABS rating for 1.8 V supply group
ABS rating for 3.3 V supply group
ABS rating for 4.2 V supply
V
V
V
ABS rating for 4.5 V supply
V
T
S
(Notes 4 and 5)
ABS storage temperature range
ABS storage humidity range at 85°C
Human Body Model (HBM): JS−001−2010
Charged Device Model (CDM): JESD22−C101
Latch-up: JESD−78
°C
%RH
V
Electrostatic discharge (ESD)
(Notes 3 and 4)
2000
500
LU
140
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Operating ratings are conditions in which operation of the device is intended to be functional.
4. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
5. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
Table 5. ELECTRICAL SPECIFICATIONS
Boldface Limits apply for T = T
to T
, all other limits T = +30°C (Notes 6, 7, 8 and 9)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
3.4
Units
Power Supply Parameters
vdda_33
Idda_33
vddd_33
Iddd_33
vdd_18
Analog supply - 3.3 V domain. gnda_33 is connected to substrate
Current consumption from analog supply
3.2
3.2
3.3
910
3.3
90
V
mA
V
Digital supply - 3.3 V domain. gndd_33 is connected to substrate
Current consumption from 3.3 V digital supply
Digital supply - 1.8 V domain. gndd_18 is connected to substrate
Current consumption 1.8 V digital supply
3.4
mA
V
1.7
1.8
540
3.3
115
4.2
0
1.9
Idd_18
mA
V
vdd_pix
Idd_pix
Pixel array supply
3.25
3.35
Current consumption from pixel supply
mA
V
vdd_resfd
gnd_resfd
Floating diffusion reset supply
Floating diffusion reset ground. Not connected to substrate
V
Note This is a sinking power supply with 200 mA range.
vdd_trans
gnd_trans
Pixel transfer supply
3.3
0
V
V
Pixel transfer ground. Not connected to substrate.
Note This is a sinking power supply with 200 mA range.
6. All parameters are characterized for DC conditions after thermal equilibrium is established.
7. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance
circuit.
8. Minimum and maximum limits are guaranteed through test and design.
9. Vref_colmux supply should be able to source and sink current
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 5. ELECTRICAL SPECIFICATIONS
Boldface Limits apply for T = T
to T
, all other limits T = +30°C (Notes 6, 7, 8 and 9)
J
MIN
MAX
J
Parameter
Description
Min
Typ
4.2
0
Max
Units
vdd_calib
gnd_calib
vdd_sel
Pixel calibration supply
V
V
V
V
V
V
V
Pixel calibration ground. Not connected to substrate
Pixel select supply
4.2
0
gnd_sel
Pixel select ground. Not connected to substrate.
Cascode supply
0
0
vdd_casc
vref_colmux
gnd_colbias
1.0
1.0
0
[9]
Column multiplexer reference supply
Column biasing ground. Dedicated ground signal for pixel biasing.
Connected to substrate
gnd_colpc
Column precharge ground. Dedicated ground signal for pixel biasing.
Not connected to substrate
0
V
Ptot
Total power consumption
4600
mW
Popt
Power consumption at lower pixel rates
Configurable
I/O - LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
720
360
Mbps
MHz
DDR signaling - 32 data channels, 1 synchronization channel
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
Vicm
LVDS input common mode level
0.3
45
1.25
2.2
50
V
Tccsk
Channel to channel skew (training pattern allows per-channel skew
correction)
ps
LVDS Electrical/Interface
fin
Input clock rate
360
55
MHz
%
tidc
tj
Input clock duty cycle
50
20
Input clock jitter
ps
fspi
ratspi
SPI clock rate
10
MHz
10-bit (32 LVDS channels): ratio: fin/fspi
10-bit (16 LVDS channels): ratio: fin/fspi
10-bit (8 LVDS channels): ratio: fin/fspi
10-bit (4 LVDS channels): ratio: fin/fspi
30
60
120
240
6. All parameters are characterized for DC conditions after thermal equilibrium is established.
7. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance
circuit.
8. Minimum and maximum limits are guaranteed through test and design.
9. Vref_colmux supply should be able to source and sink current
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 5. ELECTRICAL SPECIFICATIONS
Boldface Limits apply for T = T
to T
, all other limits T = +30°C (Notes 6, 7, 8 and 9)
J
MIN
MAX
J
Parameter
Description
Min
Typ
Max
Units
Sensor Requirements
FOT
ROT
fpix
Frame overhead time
Row overhead time
50
1
ms
ms
Pixel rate (32 channels at 72 Mpix/s)
2304
Mpix/s
Frame Specifications
Typical
Non−Zero
ROT
Zero ROT
Max
Units
fps
fps_roi1
fps_roi2
fps_roi3
fps_roi4
fps_roi5
fps_roi6
fps_roi7
fpix
Xres x Yres = 5120 x 5120
47
80
Xres x Yres = 4096 x 4096
Xres x Yres = 4096 x 3072
Xres x Yres = 3840 x 2896
Xres x Yres = 3840 x 2160
Xres x Yres = 2880 x 2896
Xres x Yres = 2048 x 2048
Pixel rate (32 channels at 72 Mpix/s)
65
120
fps
85
160
fps
95
175
fps
125
105
170
235
fps
175
fps
250
fps
2304
Mpix/s
6. All parameters are characterized for DC conditions after thermal equilibrium is established.
7. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance
circuit.
8. Minimum and maximum limits are guaranteed through test and design.
9. Vref_colmux supply should be able to source and sink current
Disclaimer: Image sensor products and specifications are subject to change without notice. Products are warranted to meet
the production data sheet and acceptance criteria specifications only.
Color Filter Array
The PYTHON XK color sensor is processed with a Bayer
RGB color pattern as shown in Figure 2. Pixel (0,0) has a red
filter situated to the bottom left. Green1 and green2 have a
slightly different spectral response due to (optical) cross talk
Y
from neighboring pixels. Green1 pixels are located on a
green-red row, green2 pixels are located on a blue-green
row.
X
pixel (0;0)
Figure 2. Color Filter Array for the Pixel Array
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Quantum Efficiency
60
50
40
30
20
10
0
MONO
Red
Green1
Green2
Blue
300
400
500
600
700
800
900
1000
1100
Wavelength [nm]
Figure 3. Quantum Efficiency Curve for Mono and Color
60
50
40
30
20
10
0
MONO
NIR
300
400
500
600
700
800
900
1000
1100
Wavelength [nm]
Figure 4. Quantum Efficiency Curve for Standard and NIR Mono
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Ray Angle and Microlens Array Information
smaller pitch than the array of photodiodes. This
difference in pitch creates a varying degree of shift
of a pixel’s microlens with regards to its
photodiode. A shift in microlens position versus
photodiode position will cause a tilted angle of
peak photoresponse, here denoted Chief Ray
Angle (CRA). Microlenses and photodiodes are
aligned with 0 shift and CRA in the center of the
array, while the shift and CRA increases radially
towards its edges, as illustrated by Figure 7.
An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of the
photodiodes. The combined microlens array and pixel array
has two important properties:
1. Angular dependency of photoresponse of a pixel
The photoresponse of a pixel with microlens in
the center of the array to a fixed optical power
with varied incidence angle is as plotted in
Figure 5, where definitions of angles fx and fy
are as described by Figure 6.
2. Microlens shift across array and CRA
The microlens array is fabricated with a slightly
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
The purpose of the shifted microlenses is to improve the
uniformity of photoresponse when camera lenses with a
finite exit pupil distance are used. In the standard version of
PYTHONxK, the CRA varies nearly linearly with distance
from the center as illustrated in Figure 8, with a corner CRA
of approximately 10.6 degrees (for 5120 x 5120 resolution).
This edge CRA is matching a lens with exit pupil distance
of ∼85 mm.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
f
X
= 0
f = 0
Y
0.2
0.1
0
−30
−20
−10
0
10
20
30
Incidence Angle f , f
X
Y
[degrees deviation from normal]
Note that the photoresponse peaks near normal incidence for center pixels.
Figure 5. Center Pixel Photoresponse to a Fixed Optical Power with Incidence Angle Varied Along fX and fY
Figure 6. Definition of Angles used in Figure 5.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Shift
Center pixel
(aligned)
Edge pixel
(with shift)
The center axes of the microlens and the photodiode coincide for the center pixels. For the edge pixels,
there is a shift between the axis of the microlens and the photodiode causing a peak response incidence
angle (CRA) that deviates from the normal of the pixel array.
Figure 7. Principle of Microlens Shift
12
10.6
10
7.5
8
6
diagonal
4
x direction
2
y direction
0
0
5
10
15
20
Distance from Center [mm]
Figure 8. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
OVERVIEW
Figure 9 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core
Image Core Bias
Pixel Array
Column Structure
64 analog channels
Analog Front End (AFE)
64 x 10 bit
digital channels
Biasing &
Bandgap
External
Resistor
Control & Registers
Data Formatting
32 x 10 bit
digital channels
LVDS Clock
Receiver
Serializers & LVDS Interface
SPI
Interface
Reset
32, 16, 8, 4 Multiplexed LVDS Output Channels
1 LVDS Channel
1 LVDS Clock Channel
Figure 9. Block Diagram
Image Core
The image core consists of:
• Pixel array
• Address decoders and row drivers
• Pixel biasing
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz. The clock
input needs to be terminated with a 100 W resistor.
The PYTHON 25MP pixel array contains 5120 (H) x
5120 (V) readable pixels with a pixel pitch of 4.5 mm.
The PYTHON 16MP/12MP/10MP image arrays contain
4224 (H) x 4112 (V) / 4224 (H) x 3088 (V) / 3968 (H) x
2912 (V) readable pixels, inclusive of 8 pixel rows and 64
pixel columns at every side to allow for reprocessing or color
reconstruction. The sensor uses in-pixel CDS architecture,
which makes it possible to achieve a low noise read out of
the pixel array in both global shutter shutter mode with CDS.
The function of the row drivers is to access the image array
to reset or read the pixel data. The row drivers are controlled
by the on-chip sequencer and can access the pixel array.
Column Multiplexer
The 5120 pixels of one image row are stored in 5120
column sample-and-hold (S/H) stages. These stages store
both the reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 64 parallel differential outputs operating at a
frequency of 36 MHz.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
At this stage, the reset signal and integrated signal values
are transferred into an FPN-corrected differential signal. A
programmable gain of 1x, 2x, or 4x can be applied to the
signal at this stage. The column multiplexer also supports a
subsampled readout mode (read-1-skip-1 for mono and
read-2-skip-2 for color version). Enabling this mode can
speed up the frame rate, with a decrease in resolution.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Serializer and LVDS Interface
The serializer and LVDS interface block receives the
formatted (10-bit) data from the data formatting block. This
data is serialized and transmitted by the LVDS output driver.
The maximum output data bit rate is 720 Mbps per
channel.
In addition to the 32 LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system-level image reconstruction.
Bias Generator
The bias generator generates all required reference
voltages and bias currents that the on-chip blocks use. An
external resistor of 47 kW, connected between the pins
ibias_master and ibias_out is required for the bias generator
to operate properly.
Analog Front End
The AFE contains 64 channels, each containing a PGA
and a 10-bit ADC.
Sequencer
The sequencer:
For each of the 64 channels, a pipelined 10-bit ADC is
used to convert the analog image data into a digital signal,
which is delivered to the data formatting block. A black
calibration loop is implemented to ensure that the black level
is mapped to match the correct ADC input level.
• Controls the image core. Starts and stops integration
and controls pixel readout.
• Operates the sensor in master or slave mode.
• Applies the window settings. Organizes readouts so that
only the configured windows are read.
Data Formatting
• Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
The data block receives data from two ADCs and
multiplexes this data to one LVDS block. A cyclic
redundancy check (CRC) code is calculated on the passing
data. For each LVDS output channel, one data block is
instantiated. An extra data block is foreseen to transmit
synchronization codes such as frame start, line start, frame
end, and line end indications.
• Starts up the sensor correctly when leaving standby
mode.
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FOT
Readout Fra
FOT
e
-1
eadout Fra e N
FOT
Integration Ti
Handling
e
Reset
N
Reset
N+1
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
OPERATING MODES
Global Shutter Mode
The PYTHON operates in pipelined or triggered global
shutter modes. In this mode, light integration takes place on
all pixels in parallel, although subsequent readout is
sequential. Figure 10 shows the integration and readout
sequence for the global shutter mode. All pixels are light
sensitive at the same period of time. The whole pixel core is
reset simultaneously and after the integration time all pixel
values are sampled together on the storage node inside each
pixel. The pixel core is read out line by line after integration.
Note that the integration and readout can occur in parallel or
sequentially. The integration starts at a certain period,
relative to the frame start.
Pipelined Global Shutter Mode
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N–1. The readout of every frame starts with
a frame overhead time (FOT), during which the analog value
on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line by line and
the readout of each line is preceded by the row overhead time
(ROT). Figure 11 shows the exposure and readout time line
in pipelined global shutter mode.
Figure 10. Global Shutter Operation
Master Mode
In this operation mode, the integration time is set through
the register interface and the sensor integrates and reads out
the images autonomously. The sensor acquires images
without any user interaction.
Slave Mode
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode and
the integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out
of reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon a
falling edge of the trigger input, the image is sampled and the
readout begins.
Exposure Time N
FOT
Exposure Time N+1
FOT
Readout
Handling
ROT
Line Readout
Figure 11. Pipelined Shutter Operation in Master Mode
External Trigger
Integration Time
Handling
Reset
N
Reset
N+1
Exposure Time N
FOT
FOT
Exposure T im e N+1
Readout N
FOT
Readout
Handling
FOT
Readout N−1
FOT
ROT
Line Readout
Figure 12. Pipelined Shutter Operation in Slave Mode
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Exposure Ti
Register Controlled
Readout -1
FOT
FOT
Exposure Ti
Readout N
e N
e
+1
FOT
FOT
FOT
Integration Ti
Handling
e
Reset
N
Reset
N+1
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Triggered Global Shutter
Master Mode
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences from the pipelined shutter
master mode are:
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 13 shows the relation between the external trigger
signal and the exposure/readout timing. If a rising edge is
applied on the external trigger before the exposure time and
FOT of the previous frame is complete, it is ignored by the
sensor.
• Upon user action, a single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
• Integration and readout is user-controlled through an
external pin. This mode requires manual intervention
for every frame.
Slave Mode
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, the
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
The pixel array is kept in reset state until requested.
The triggered global mode can also be controlled in a
master or in a slave mode.
No effect on falling edge
External Trigger
Readout
Handling
ROT
Line Readout
Figure 13. Triggered Shutter Operation in Master Mode
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Non−Zero and Zero Row Overhead Time (ROT) Modes
This operation mode can be used for two reasons:
• Reduced total line time.
• Lower power due to reduced clock rate.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
out and integration of frame N is ongoing during readout of
the previous frame N−1. The readout of every frame starts
with a Frame Overhead Time (FOT), during which the
analog value of the pixel diode is transferred to the pixel
memory element. After the FOT, the sensor is read out line
by line and the readout of each line is preceded by a Row
Overhead Time (ROT) as shown in Figure 14.
In Reduced/Zero ROT operation mode (refer to
Figure 15), the row blanking and kernel readout occur in
parallel. This mode is called reduced ROT as a part of the
ROT is done while the image row is readout. The actual ROT
can thus be longer, however the perceived ROT will be
shorter (‘overhead’ spent per line is reduced).
FOT
(
)
ROT
ys
Readout
ys
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye
Valid Data
Figure 14. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Non−Zero ROT Readout.
FOT
(
)
ROT
ys
(blanked ou)t
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye−1
ROT
dummy
Readout
ye
Valid Data
Figure 15. Integration and Readout Sequence of the Sensor operating in Pipelined Global Shutter Mode with
Zero ROT Readout.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
SENSOR OPERATION
Flowchart
The states above are ordered by power dissipation.
Figure 16 shows the flow chart diagram of the sensor
operation. The sensor can be in five different ‘states’. Every
state is indicated with an oval circle. These states are:
• Power-Off
Clearly, in ‘power-off’ state the power dissipation will be
minimal; in ‘running’ state the power dissipation will be
maximal.
On the other hand, the lower the power consumption, the
more actions (and time) are required to put the sensor in
‘running’ state and grab images.
This flowchart provides the trade-offs between power
saving and enabling time of the sensor.
Next to the ‘states’ a set of ‘user actions’, indicated by
arrows, are included in the flow chart diagram. These user
actions make it possible to move from one state to another.
• Standby (1)
• Standby (2)
• Idle
• Running
Figure 16. Sensor Operation Flowchart
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Sensor States
output channel multiplexing (32, 16, 8 or 4), by connecting
pins F24/F25 (muxmode0/1), should be set to the correct
supply as described in Table 31 and Table 28.
When the clock frequency is stable, the reset_n signal
can be de−asserted. After a wait period of 10 ms, the power
up sequence is finished and the first SPI upload can be
initiated.
The sensor can be in five different states:
Power-off
In this state, the sensor is inactive. All power supplies are
down and the power dissipation is zero.
Standby (1)
The registers below address 40 can be configured.
LVDS clock
reset_n
Standby (2)
In this standby state all SPI registers are active, meaning
that all SPI registers can be accessed for read and write
operations. All other blocks are disabled.
vddd_18
vddd_33
Note: An Intermediate Standby state is traversed after a
hard reset. In this state the sensor contains the default
configurations. Uploads of reserved registers are required to
traverse to the Standby (2) state
vdda_33
vdd_casc
other supplies
Idle
> 10us > 10us > 10us > 10us > 10us
> 10us
In the idle state, all sensor clocks are running and all
blocks are enabled, except the sequencer block. The sensor
is ready to start grabbing images as soon as the sequencer
block is enabled.
Figure 17. Power−up Procedure
NOTE: vdd_casc should come up prior to vdd_resfd,
vdd_trans, vdd_calib and vdd_sel.
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in different global
master/slave modes.
Enable Clock Management
The ’Enable Clock Management’ action configures the
clock management blocks in a pre−defined way. The
required uploads are listed in Table 6.
User Actions: Power Up Functional Mode Sequences
Power-up Sequence
Table 6. ENABLE CLOCK MANAGEMENT REGISTER
UPLOAD
Figure 17 shows the power-up timing of the sensor. Apply
all power supplies in the order shown in the figure. It is
important to comply with the described sequence. Any other
supply ramping sequence may lead to high current peaks
and, as a consequence, a failure of the sensor power up.
The clock input should start running when all supplies are
stabilized. Note that before starting the clock, the LVDS
Upload # Address
Data
Description
Monochrome
1
2
2
0x0000
0x0001
0x0001
Color
34
Enable Logic Blocks
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Required Register Uploads
Upload #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Address
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
Data (Non−Zero ROT)
0xe061
0xe265
0xe061
0xe041
0xe001
0xe406
0xe005
0xe20a
0xe001
0xe800
0xe800
0xec0a
0xe80a
0xe800
0x0030
0x217b
0x2071
0x0071
0x107f
In this phase the ’reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads are listed in Table 7.
Table 7. REQUIRED REGISTER UPLOADS FOR,
NON−ZERO ROT, PIPELINED GLOBAL SHUTTER
MASTER MODE
Upload #
1
Address
41
Data (Non−Zero ROT)
0x0b5a
0x1001
0x018d
0x88cb
0x53c7
0x8567
0x0488
0x48ff
2
42
3
43
4
65
5
66
6
67
7
69
8
70
9
128
129
192
193*
194
197
204
211
215
216
219
220
224
225
227
237
238
384
385
386
387
388
389
390
391
392
393
394
0x360a
0x0001
0x000c
0x8600
0x0224
0x0103
0x01e4
0x0e59
0x0007
0x7f00
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
0x107f
0x107f
0x1075
0x0071
0x0036
0x21bb
0x20b1
0x00b1
0x10bf
0x0015
0x192c
0x3e07
0x5ef1
0x10bf
0x0000
0xc0a0
0x8f88
0x10bf
0x10b5
0x00b1
0x0030
0x0030
0x207b
0x2071
0x0071
0x107f
0xe800
0xf801
0xfb1f
0xfb15
0xf911
0xf901
0xf105
0x107f
0xf30f
0x107f
0xf201
0x1075
0x0071
0xe001
0xe021
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Operating Modes on page 13 for an overview of the possible
operation modes.
The ‘Enable Sequencer’ action consists of a set op register
uploads. The required uploads are listed in Table 9.
Upload #
Address
437
Data (Non−Zero ROT)
0x0036
79
80
438
0x21bb
81
439
0x20b1
Table 9. ENABLE SEQUENCER REGISTER UPLOADS
82
440
0x00b1
Upload #
Address
Data
83
441
0x10bf
1
192
0x000D
84
442
0x10bf
85
443
0x10bf
User Actions: Functional Mode to Power Down
Sequences
86
444
0x10b5
Disable Sequencer
87
445
0x00b1
During the ‘Disable Sequencer’-action, the frame
grabbing sequencer is stopped. The sensor will stop
grabbing images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set op
register uploads. The required uploads are listed in Table 10.
88
446
0x0030
Upload #
12
Address
193*
Data (Zero ROT)
0x0800
NOTE: Required Uploads for Zero ROT mode are the same as for
Non−Zero ROT mode with the exceptions noted.
Table 10. DISABLE SEQUENCER REGISTER
UPLOADS
Soft Power Up
Upload #
Address
Data
During the soft power-up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power-up uploads are listed in Table 8.
1
192
0x000C
Soft Power Down
During the soft power-down action, the internal blocks are
disabled and the sensor is put in standby state in order to
reduce the current dissipation. This action exists of a set of
register uploads. The soft power-down uploads are listed in
Table 11.
Table 8. SOFT POWER UP REGISTER UPLOADS
Upload # Address
P1−SN/SE
Data
Description
1
2
3
4
32
64
40
48
0x2005 Enable Analogue Clock
0x0001 Enable Biasing Block
0x0003 Enable Column Multiplexer
Table 11. SOFT POWER DOWN REGISTER UPLOADS
Upload # Address
P1−SN/SE
Data
Description
0x0001 Enable Analog Front-End
(AFE)
1
2
112
48
0x0000 Disable LVDS Transmitters
5
6
68
0x0088 Enable LVDS Bias
0x0000 Disable Analog Front-End
(AFE)
112
0x0007 Enable LVDS Transmitters
3
4
5
40
64
32
0x0000 Disable Column Multiplexer
0x0000 Disable Biasing Block
0x2004 Disable Analogue Clock
Enable Sequencer
During the ‘Enable Sequencer’-action, the frame
grabbing sequencer is enabled. The sensor will start
grabbing images in the configured operation mode. Refer to
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19
vꢀdd_ꢀcasc
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Disable Clock Management
Table 13. SHUTTER/OPERATION MODE
CONFIGURATION REGISTERS
The ‘Disable Clock Management’-action stops the
internal clocking in order to further decrease the power
dissipation. This action exists of a set of register uploads as
listed in Table 12.
Default
Value
Address
Description
192 [4]
0x0
Triggered mode selection
0: Normal mode
Table 12. DISABLE SEQUENCER REGISTER
UPLOADS
1: Triggered mode
192 [5]
192 [7]
192 [8]
0x0
0x0
0x0
Master/Slave selection
0: Master mode
No.
Address
Data
Description
1
34
0x0000
Disable Logic Blocks
1: Slave mode
Subsampling mode selection
0: Subsampling disabled
1: Subsampling enabled
Power-down Sequence
The timing diagram of the advised power-down sequence
is given in Figure 18. Any other sequence might cause high
peak currents.
Binning mode selection
0: Binning disabled
1: Binning enabled
NOTE: vdd_casc should be powered down after
vdd_resfd, vdd_trans, vdd_calib and vdd_sel.
Windowing Reconfiguration
LV ꢀSꢀ clock
The windowing settings can be configured during
standby, idle, and running mode.
r
ꢀset_n
The required regions of interest (ROI) can be programmed
in the roi_configuration registers (addresses 256 up to 351).
Registers roi_active0 and roi_active1 are used to activate the
desired ROIs.
vddd_18
vddd_33
vdda_33
Default window configuration (after sensor reset) is one
window, full frame (window #0).
other supplies
Exposure/Gain Reconfiguration
> 10u s
> 1 0us
> 10us
>
10 us
> 10us
> 10us
The exposure time and gain settings can be configured
during standby, idle, and running mode. Refer to Signal Gain
Path on page 32 for more information.
Figure 18. Power−down Sequence
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Sensor Configuration
Static Readout Parameters
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Some registers are only modified when the sensor is not
acquiring images. Reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
are shown in Table 14. Table 14 should not be reconfigured
during image acquisition. A specific configuration sequence
applies for these registers. Refer to the operation flow and
startup description.
Table 14. STATIC READOUT PARAMETERS
Group
Clock generator
Addresses
Description
32
40
Configure according to recommendation
Image core
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
Configure according to recommendation
AFE
48
Bias
64–71
112
192
LVDS
Sequencer mode selection
•
•
triggered_mode
slave_mode
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the
recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
The category of registers as shown in Table 15 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly exposed
The effect is transient in nature and the new configuration
is applied after the transient effect.
Table 15. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[12:8]
Reconfiguration of these registers may have an impact on the black-level calibration
algorithm. The effect is a transient number of images with incorrect black level
compensation.
Sync codes
129[13]
Incorrect sync codes may be generated during the frame in which these registers
are modified.
116–126
Datablock test configurations
144–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
Dynamic Readout Parameters
Some reconfiguration may lead to one frame being
It is possible to reconfigure the sensor while it is acquiring
images. Frame-related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
shown in Table 16.
blanked. This happens when the modification requires more
than one frame to settle. The image is blanked out and
training patterns are transmitted on the data and sync
channels.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 16. DYNAMIC READOUT PARAMETERS
Group
Addresses
Description
Subsampling/binning
192[7]
192[8]
Subsampling or binning is synchronized to a new frame start.
ROI configuration
195-196
256–351
An ROI switch is only detected when a new window is selected as the active window
(reconfiguration of registers 195, 196, or both). Reconfiguration of the ROI dimension of
the active window does not lead to a frame blank and can cause a corrupted image.
Exposure reconfiguration
Gain reconfiguration
199-201
204
Exposure reconfiguration does not cause artifact. However, a latency of one frame is
observed unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode
(master).
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates
(refer to register 204[13] gain_lat_comp).
Freezing Active Configurations
Figure 19 shows a reconfiguration that does not use the
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before reconfiguration. When all registers are
uploaded, re-enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
them for the coming frames. The freezing of the active set
of registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
When sync_configuration = ‘1’, configurations are
synchronized to the frame boundaries (The registers
exposure, fr_length, and mult_timer are not used in this
mode)
Figure 20 shows the usage of the sync_configuration
settings. Before uploading
a set of registers, the
corresponding sync_configuration is deasserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3
Frame N+4
Time Line
SPI Registers
Active Registers
Figure 19. Frame Synchronization of Configurations (no freezing)
Frame NꢁꢁꢁFrame N+1ꢁꢁꢂFrame N+2ꢁꢁꢂꢀFrame N+3ꢁꢁꢂꢀFrame N+4
Time Line
sync_configuration
SPI Registers
This configuration is not taken into
account as sync_register is inactive.
Active Registers
Figure 20. Reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 17 lists the several sync_configuration possibilities along with the respective registers being
frozen.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 17. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
sync_exposure
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
sync_gain
sync_roi
mux_gainsw
afe_gain
Update of gain configurations is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
roi_active0[15:0]
roi_active1[15:0]
subsampling
binning
Update of active ROI configurations is not synchronized at start of frame when ‘0’. The
sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. Re-configuration of
active windows is not gated by this setting.
Window Configuration
Black Calibration
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
Global Shutter Mode
Up to 32 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 351. Each window can be activated or
deactivated separately using registers 195 and 196. It is
possible to reconfigure the inactive windows while
acquiring images. Switching between predefined windows
is achieved by activation of the respective windows. This
way a minimum number of registers need to be uploaded
when it is necessary to switch between two or more sets of
windows. As an example of this, scanning the scene at
higher frame rates using multiple windows and switching to
full frame capture when the object is tracked. Switching
between the two modes only requires an upload of one (if the
total number of windows is smaller than 17) or two (if more
than 16 windows are defined) registers.
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 64 columns contained
in one kernel. This implies 64 black level offsets are
generated and applied to the corresponding columns.
Configurable parameters for the black-level algorithm are
listed in Table 18.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 18. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Group
Addresses
Description
Black Line Generation
197[7:0]
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black-level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black-level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Each black line contains 80 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured.
These blanked out lines are not used for black calibration. It is recommended to enable
this functionality, because the first line can have a different behavior caused by boundary
effects. When enabling, the number of black lines must be set to at least two in order to
have valid black samples for the calibration algorithm.
Black Value Filtering
129[0]
auto_blackcal_enable Internal black-level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black-level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide ex-
ternal statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when au-
to_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled.
The calculated black calibration factors are frozen when this register is set to 0x1FF
(all−‘1’) in auto calibration mode. Any value different from 0x1FF re−enables the black
calibration algorithm. This freezing option can be used to prevent eventual frame to frame
jitter on the black level as the correction factors are recalculated every frame. It is recom-
mended to enable the black calibration regularly to compensate for temperature changes.
129[10]
blackcal_offset_dec
black_samples
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
128[10:8]
The black samples are low-pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
black_samples
The effective number of samples taken into account for filtering is 2
.
Note: An error is reported by the device if more samples than available are requested
(refer to registers 136 to 139).
Black Level Filtering Monitoring
136
137
138
139
blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
blackcal_error1
blackcal_error2
blackcal_error3
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determina-
tion (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Serial Peripheral Interface
significant bit first. The sck clock is passed
through to the sensor as indicated in Figure 21.
The sensor samples this data on a rising edge of
the sck clock (mosi needs to be driven by the
system on the falling edge of the sck clock)
5. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 21 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON XK sensor
uses 9-bit addresses and 16-bit data words
Data driven by the system is colored blue in Figure 21,
while data driven by the sensor is colored yellow. The data
in grey indicates high-Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
6. Data transmission:
- For write commands, the master continues
sending the 16-bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
7. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note the maximum frequency for the SPI interface needs
to scale with the LVDS input clock frequency as described
in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
3. Select the sensor for read or write by pulling down
the ss_n line.
4. One SPI clock cycle (100 ns) after selecting the
sensor, the 9-bit address is transferred, most
SP I − W R ITE
ss_n
sck
t_sc ks s
t_sssck
ts ck
ts_mos i
th_mosi
A8
A7
..
..
..
A1
A0
`1'
D
5
D14
..
..
..
..
D1
D0
mosi
miso
SPI − REA D
ss_n
sck
t_sc ks s
t_sssck
ts ck
ts_mosi
th_mosi
A8
A7
..
..
..
A1
A0
`0'
mosi
miso
ts_mi so
th_mi so
D
5
D14
..
..
..
..
D1
D0
Figure 21. SPI Read and Write Timing Diagram
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 19. SPI TIMING REQUIREMENTS
Group
tsck
Addresses
Description
Units
ns
(*)
sck clock period
100
tsssck
tsckss
ts_mosi
th_mosi
ts_miso
th_miso
tspi
ss_n low to sck rising edge
sck falling edge to ss_n high
Required setup time for mosi
Required hold time for mosi
Setup time for miso
tsck
tsck
ns
ns
20
ns
20
ns
tsck/2-10
tsck/2-20
2 x tsck
ns
Hold time for miso
ns
Minimal time between two consecutive SPI accesses (not shown in figure)
ns
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/f . See text for more information on SPI clock frequency restrictions.
SPI
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
IMAGE SENSOR TIMING AND READOUT
Global Shutter Mode
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
Pipelined Global Mode (Master)
The sensor timing in master global shutter mode is
controlled by the user by means of configuration registers.
One can distinguish three parameters for the frame timing in
global shutter mode:
• Image Array Reset Length
• Integration Time
• Frame Length
NOTES:
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. Therefore, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to read out all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
The relation between these parameters is:
Frame Length = Reset Length + Integration Time
The FOT time needs to be added to the frame length
parameter to determine the total frame Time
Total Frame Time = FOT Time + Frame Length
Frame Length and Integration Time as Parameters
When fr_mode is configured to 0x1, one configures the
frame time and exposure. The reset_length is determined by
the sequencer. This configuration mode is depicted in
Figure 2.
Frame and integration time configuration can be controlled
in two ways:
1. fr_mode = 0x0
The reset length and integration time is configured
by the user. The sensor shall calculate the frame
length as the sum of both parameters.
The frame length is configured in register fr_length, while
the integration time is configured in register exposure. The
mult_timer register defines granularity of both settings.
Note that the FOT needs to be added to the configured
fr_length to calculate the total frame time.
2. fr_mode = 0x1
The frame length and integration time is
configured by the user. The reset time during
which the pixels are reset, is calculated by the
sensor as being the difference between the frame
length and the desired integration time.
Triggered Global Shutter (Master)
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger pin. The
exposure or integration time is defined by the registers
exposure and mult_timer, similar to the master pipelined
global mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 24.
The configuration registers are exposure[15:0] and
fr_length[15:0]. The latter configuration register is either
used as Reset Length configuration (fr_mode = 0x0) or as
Frame Length (fr_mode = 0x1). The granularity of both
registers is defined by the mult_timer[15:0] register and is
expressed in number of 72 MHz cycles (13.889 ns nominal).
NOTES:
• The falling edge on the trigger pin does not have any
impact. However, the trigger must be asserted for at
least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. Therefore, the effective
time during which the image core is in reset state is
extended to the start of a new line.
Reset Length and Integration Time as Parameters
The reset time for the pixel array is controlled by the
registers fr_length[15:0] and exposure[15:0]. The
mult_timer configuration defines the granularity of the
registers fr_length and exposure and is to be read as the
number of 72 MHz cycles (13.889 ns nominal).
The exposure control for pipelined global master mode is
depicted in Figure 22.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
The pixel values are transferred to the storage node during
the FOT, after which all photo diodes are reset. The reset
state remains active for a certain time, defined by the
fr_length and mult_timer registers, as shown in the figure.
Meanwhile, the image array is read out line by line. After
this reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
If the exposure timer expires before the end of readout, the
exposure time is extended until the end of the last active line.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Frame N
Frame N+1
Exposure State
Readout
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Image Array Global Reset
fr_length
exposure
= ROT
= Readout
Figure 22. Integration Control for Pipelined Global Shutter Mode (Master, fr_mode = 0x0)
Frame N
Frame N+1
Exposure State
Readout
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Image Array Global Reset
exposure x mult_timer
fr_length x mult_timer
= ROT
= Readout
Figure 23. Integration Control for Pipelined Global Shutter Mode (Master, fr_mode = 0x1)
Frame N
Frame N+1
Exposure State
trigger0
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
(No effect on falling edge )
Readout
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
Figure 24. Exposure Time Control in Triggered Global Mode (Master)
Triggered Global Shutter (Slave)
starts during a frame readout. Therefore, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure, and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer and
readout of the image array. In other words, the high time of
the trigger pin indicates the integration time, the period of
the trigger pin indicates the frame time.
• If the trigger is deasserted before the end of readout, the
exposure time is extended until the end of the last
active line. Consequently the FOT and start of frame
readout is postponed accordingly.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
The use of the trigger during slave mode is shown in
Figure 25.
NOTES:
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Frame N
Frame N+1
Exposure State
trigger
FOT
FOT
Reset
Integrating
FOT
FOT
Reset
Integrating
FOT
FOT
Readout
Image Array Global Reset
= ROT
= Readout
Figure 25. Exposure Time Control in Global−Slave Mode
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
ADDITIONAL FEATURES
Multiple Window Readout
y1_end
y0_end
y1_start
The PYTHON sensor supports multiple window readout,
which means that only the user−selected Regions Of Interest
(ROI) are read out. This allows limiting data output for every
frame, which in turn allows increasing the frame rate. In
global shutter mode, up to 32 ROIs can be configured.
ROI 1
ROI 0
Window Configuration
Figure 26 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
x1_end
ROI 0
Figure 27. Overlapping Multiple Window
Configuration
y-start
The sequencer analyses each line that need to be read out
for multiple windows.
Restrictions
The following restrictions for each line are assumed for
the user configuration:
x-startꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢂx-end
• Windows are ordered from left to right, based on their
Figure 26. Region of Interest Configuration
x−start address:
x_start_roi(i) vx_start_roi(j) AND
x_end_roi(i) vx_end_roi(j)
Where j > i
• x−start[6:0]
x−start defines the x−starting point of the desired window.
The sensor reads out 64 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 64 pixels. The value configured in the x−start
register is multiplied by 64 to find the corresponding column
in the pixel array.
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #31.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
• x−end[6:0]
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to thirty−two windows can be defined, possibly
(partially) overlapping, as illustrated in Figure 27.
Figure 28 illustrates
configuration with five windows. The current position of the
a
practical example of
a
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Subsampling and Binning
read pointer (ys) is indicated by a red line crossing the image
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels are
scanned up to the ROI3 x−end position. From there, the
x−pointer jumps to the next window, which is ROI4 in this
illustration. When reaching ROI4’s x−end position, the read
pointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
Pixel binning and subsampling methods are used as a way
of decimating the image. The number of pixel samples is
reduced by a factor of four, while the optical area is
maintained.
Pixel Binning
Pixel binning is a technique in which different pixels
belonging to a rectangular bin are averaged in the analog
domain. Two-by-two pixel binning is implemented in the
PYTHON XK sensor. This implies that two adjacent pixels
are averaged both in column and row. Binning is
configurable using a register setting. Pixel binning is not
supported on PYTHON XK color option.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 28, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
Notes:
1. Binning can be activated for the x and y direction
independently by means of the binning_mode
register. Refer to the registermap for more
information.
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
2. Binning in the y−direction is not supported in
conjunction with Zero ROT mode.
Subsampling
Subsampling is obtained by adapting the readout
sequence. In subsampling mode, both lines and pixels are
read in a read-N-skip-N mode. This reduces the number of
lines in a frame and the number of pixels in a line. Overall
frame time is reduced by a factor 4.
• Each window can be activated separately. There is no
restriction on which window and how many of the 8
windows are active.
Subsampling can be configured for the x and y direction
independently by means of the subsampling_mode register.
The monochrome sensor is read out in
read-one-skip-one pattern for both the rows and the
columns, while the color version supports
a
a
read-two-skip-two subsampling scheme. This mode is
selectable through register configuration. Figure 29 shows
which pixels are read and which ones are skipped for
monochrome and color sensors respectively. Readout
direction is indicated as an x and y arrow.
ROI 2
ROI 4
ROI 3
ys
ROI 1
ROI 0
Figure 28. Scanning the Image Array with Five
Windows
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Figure 29. Subsampling Scheme for PYTHON XK
Signal Gain Path
Table 20 and Table 21 show the available registers (fields)
to program the desired exposure time and gain settings.
Table 21. GAIN CONFIGURATION REGISTERS
Unity
Gain
Config-
Address uration
Table 20. EXPOSURE TIME CONFIGURATION
REGISTERS
Description
204 [4:0]
0x04
0x04:
0x18:
0x08:
0x10:
1x
Default
1.26x
1.87x
3.17x
Value
Address
Description
201
0x0000 Exposure time: granularity defined by
’Mult Timer’ (register 199).
204 [13]
Postpone gain update by one frame
when ‘1’ to compensate for exposure
time updates latency.
199
200
0x0001 Mult Timer
Defines granularity of exposure and
reset length.
205[11:0]
0x080
Digital Gain, 5.7 unsigned representation
(5 bits before decimal point, 7 bits after
fractional part). Maximum gain is 31.992
unit = 1/72 MHz for normal ROT mode
0x0000 Reset length or Frame Length
Granularity defined by ’Mult Timer’
(register 199)
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Table 22. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Corrupted
Frame
Blanked Out
Frame
Configuration
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Configurable
Configurable with blank_subsampling_ss register.
Disabling: Yes
binning
No
No
Configurable
Configurable with blank_subsampling_ss register
Frame Timing
black_lines
Exposure Control
mult_timer
fr_length
No
No
No
No
No
No
No
Latency is 1 frame
Latency is 1 frame
Latency is 1 frame
exposure
Gain
mux_gainsw
afe_gain
No
No
No
No
No
No
Latency configurable by means of gain_lat_comp register
Latency configurable by means of gain_lat_comp register.
Latency configurable by means of gain_lat_comp register.
db_gain
Window/ROI
roi_active
See Note
See Note
No
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
Black Calibration
black_samples
No
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
CRC Calculation
crc_seed
Sync Channel
bl_0
See Note
No
No
No
Manual blackcal_offset updates are instantly active.
Impacts the transmitted CRC
No
No
No
No
No
No
No
No
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
Impacts the Sync channel information, not the Data channels.
img_0
crc_0
tr_0
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Sensor Status
Monitor Pins
The currently used exposure and gain parameters are
The sensor features three logic monitor output pins. These
pins can provide internal state and synchronization
information to the outside system. These status pins can be
used during system setup or for system frame
synchronization.
The pins are named monitor0, monitor1, and monitor2.
The information provided on these pins is configured with
the register monitor_select (register 192[13:11]).
reported by the sensor in registers 240 to 248. These status
registers are updated at the start of the frame in which these
parameters become active.
Temperature Diode
The temperature diode allows the monitoring of the sensor
die temperature during operation. The diode can be
connected through the pins td_anode and td_cathode.
The die temperature (Tdie), as a function of the measured
forward threshold voltage of the diode, with a known bias
current (Vdiode at bias 40 mA), is determined according to
the following formula:
NOTE: Monitor indications are generated in the
sequencer. These signals lead the image and
synchronization data on the LVDS channels.
T
= (0.77–Vdiode at bias 40 mA)/0.00158°C
die
Temperature Sensor
The PYTHON has an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8−bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of 2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of 5°C.
Note that any process variation will result in an offset in
the bit count and that offset will remain within 5°C over the
temperature range of 0°C and 85°C. Tsensor output digital
code can be read out through the SPI interface.
Output of the temperature sensor to the SPI:
tempd_reg_temp<7:0>: This is the 8−bit N count readout
proportional to temperature.
Input from the SPI:
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
Calibration using one temperature point
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
T = R (Nread − Ncalib) + Tcalib
J
T = junction die temperature
J
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 23. MONITOR SELECT
Monitor Select
Monitor Output
Description
0x0
monitor0: ‘0’
monitor1: ‘0’
monitor2: ‘0’
No information is provided on the output pins. All outputs are
driven to logic ‘0’
0x1
0x2
0x3
0x4
0x5
0x6
0x7
monitor0: Integration time indication
monitor1: ROT indication
High during integration
High when ROT is active, low outside ROT
High during dummy lines, low during all other lines
High during integration
monitor2: Dummy line indication
monitor0: Integration time indication
monitor1: N/A
N/A
monitor2: N/A
N/A
monitor0: Start of X-readout
monitor1: Black line indication
monitor2: Dummy line indication
monitor0: Frame start
Pulse indicating the start of X-readout
High during black lines, low during all other lines
High during dummy lines, low during all other lines
Pulse indicating the start of a new frame
Pulse indicating the start of ROT
monitor1: Start of ROT
monitor2: Start of X-readout
monitor0: First line indication
monitor1: Start of ROT indication
monitor2: ROT inactive
Pulse indicating the start of X-readout
High during the first line of each frame, low for all others
Pulse indicating the start of ROT
Low when ROT is active, high outside ROT
High when ROT is active, low outside ROT
Pulse indicating the start of X-readout
Low during X-readout, high outside X-readout
Pulse indicating the start of X-readout for black lines
Pulse indicating the start of X-readout for image lines
Pulse indicating the start of X-readout for dummy lines
monitor0: ROT indication
monitor1: Start of X-readout
monitor2: X-readout inactive
monitor0: Start of X-readout for black lines
monitor1: Start of X-readout for image lines
monitor2: Start of X-readout for dummy lines
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
DATA OUTPUT FORMAT
LVDS Output Channels
deserializer. Word alignment is done by looking for well
known training patterns.
All major FPGA vendors provide bit and word alignment
methods for their FPGAs. Refer to the FPGA vendor’s
application for more information on the use of these
functionalities.
When the host succeeds in a lock for bit and word
alignment procedures, the system enables the sensor for
image acquisition. Specific frame alignment patterns are
transmitted for image frame synchronization purposes.
The image data output occurs through 32 LVDS data
channels, operating at 720 Mbps. A synchronization LVDS
channel and an LVDS output clock signal synchronizes the
data.
The 32 data channels are used to output the image data
only. The sync channel transmits information about data sent
over these data channels (includes codes indicating black
pixels, normal pixels, and CRC).
To perform word synchronization on the output data
stream, a predefined training pattern is sent after startup of
the sensor and during idle times (during FOT, ROT, and in
between frames and lines). This data is used to perform word
alignment on the receiving side.
The words on data and sync channels have a 10-bit length.
The words are serialized most significant bit first. The
output data rate is 720 Mbps.
Frame Format
The frame format is explained by example of the readout
of two (overlapping) windows, as shown in Figure 30 (a).
The readout of a frame occurs on a line-by-line basis. In
this representation, the read pointer goes from left to right,
bottom to top.
Figure 30 indicates that, after the FOT is complete, a
number of lines which only include information of ‘ROI 0’
are sent out, starting at position y0_start. When the line at
position y1_start is reached, a number of lines containing
data of ‘ROI 0’ and ‘ROI 1’ are sent out, until the line
position of y0_end is reached. From there on, only data of
‘ROI 1’ appears on the data output channels until line
position y1_end is reached.
Serial Link Interface Operation
This sensor’s serial link interface is based on a
mesochronous clocking system. This means that all data and
control links operate at the same frequency, but their phase
may be different due to skew. The host provides an LVDS
clock as input to the sensor. To compensate for possible large
on-chip delays, the sensor retransmits this clock with the
same delay as that seen by the data (32 data channels) and
control path (one sync channel). The receiver end (generally
an FPGA-based system) performs per-interface skew
compensation.
The data on high-speed serial links can drift due to various
reasons such as skew, jitter, PCB trace delays, process,
voltage, and temperature variations. The receiver performs
per-LVDS interface skew compensation using bit and word
alignment techniques.
To support per-interface skew compensation, the sensor
provides a training mode that allows the system to perform
bit and word alignment on all interfaces.
During idle moments (when the sensor is not capturing
images or during frame and line overhead), the image sensor
transmits training patterns. These patterns are configurable
by means of a register upload and should be chosen such that
these can easily be detected by reducing the risk of
mimicking in the regular data stream.
NOTE: Only frame start and frame end sync words are
indicated in (b). CRC codes are also omitted
from Figure 30.
During readout of image data over the data channels, the
sync channel sends out frame synchronization codes, which
provide information related to the image data being sent
over the 32 data output channels.
Each line of a window starts with a line start (LS)
indication and ends with a line end (LE) indication. The line
start of the first line is replaced by a frame start; the line end
of the last line is replaced with a frame end indication. Each
such frame synchronization code is followed by a window
ID (range 0 to 31).
The data channels contain valid pixel data during
FS/FE/LS/LE and window ID synchronization codes.
NOTE: For overlapping windows, the line
synchronization codes of the overlapping
windows with lower IDs are not sent out. As
shown in the illustration, no LE is transmitted
for the overlapping part of window 0.
Bit Alignment
Bit alignment procedures position the sampling edge of
the clock at the center of the data eye window by adding
delay to the data path (using delay taps).
Black lines are read out at the start of a frame. These lines
are enclosed by LS and LE indications (no frame start/end).
The window ID for the black lines must be ignored.
Word Alignment
Word alignment procedures ensure that the reconstructed
parallel data bits are in correct order at the output of the
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36
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Reset
N
Reset
N+1
FOT
FOT
FOT
FOT
Exposure Time N
Exposure Time N+1
Readout Frame N-1
Readout Frame N
Readout
Handling
B
L
ROI
1
B
L
ROI
1
FOT
ROI 0
ROI 0
FS0
FS1
FE1
FS0
FS1
FE1
(b)
Figure 30. Frame Sync Codes
Figure 31 and Figure 32 show the details of the readout of
a number of lines for single window readout, at the
beginning of the frame.
Figure 33 shows the details of the readout of a number of
lines for two overlapping windows.
Sequencer
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
Internal State
data channels
sync channel
Training
TR
Training
data channels
sync channel
LS
0
BL
BL
BL
BL
BL
BL
LE
0
CRC
TR
timeslot
0
timeslot
1
timeslot
77
timeslot
78
timeslot
79
CRC
timeslot
Figure 31. Timeline Showing Readout of Black Line for Global Shutter
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Sequencer
Internal State
FOT
ROT
black
ROT
ROT
line Ys+1
ROT
line Ye
line Ys
data channels
sync channel
Training
Training
TR
data channels
sync channel
TR
FS
ID
IMG IMG
IMG
IMG
IMG IMG
LE
ID
CRC
timeslot
Xstart
timeslot
Xstart + 1
timeslot
Xend - 2
timeslot
Xend - 1
timeslot
Xend
CRC
timeslot
Figure 32. Timeline for Single Window Readout
NOTE: In the figure, the second image line is shown in more detail. The LS code is replaced by FS for the first line and
the LE code is replaced by FE for the last line in the window.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
line Ys+1
ROT
line Ye
data channels
sync channel
Training
TR
Training
TR
data channels
sync channel
LS
IMG IMG
LS
IDN IMG
LE
IDN
CRC
IDM
IMG
IMG
timeslot
XstartM
timeslot
XstartM +1
timeslot
XstartN
timeslot
XstartN -1
timeslot
XendN
CRC
timeslot
Figure 33. Timeline Showing Readout of Two Overlapping Windows
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Frame Synchronization
same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 24 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable). If more than one window is active at the
Table 24. FRAME SYNCHRONIZATION CODE DETAILS
Sync Word Bit
Position
Register
Address
Default Value
Description
9:7
9:7
9:7
9:7
6:0
N/A
N/A
0x5
0x6
Frame start (FS) indication
Frame end (FE) indication
Line start (LS) indication
Line end (LE) indication
N/A
0x1
N/A
0x2
117[6:0]
0x2A
These bits indicate that the received sync word is a frame synchronization code. The value is
programmable by a register setting
Window Identification
Data Classification Codes
Frame synchronization codes are always followed by a
4−bit window identification (bits 3:0). This is an integer
number, ranging from 0 to 15, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 25.
Table 25. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES
Sync Word Bit
Position
Register
Address
Default Value
Description
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
9:0
9:0
119 [9:0]
125 [9:0]
126 [9:0]
0x035
0x059
0x3A6
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).
CRC value. The data on the data output channels is the CRC code of the finished image data line.
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Training Patterns on Data Channels
During idle periods, the data channels transmit training
patterns, indicated on the sync channel by a TR code. These
training patterns are configurable independent of the
training code on the sync channel as shown in Table 26.
Table 26. TRAINING CODE ON SYNC CHANNEL
Sync Word Bit
Position
Register
Address
Default
Value
Description
[9:0]
116 [9:0]
0x3A6
Data channel training pattern. The data output channels send out the training pattern, which can be
programmed by a register setting. The default value of the training pattern is 0x3A6, which is identical
to the training pattern indication code on the sync channel.
Cyclic Redundancy Code
Black Reference
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is at a minimum, equal to 1. The length
of the black lines depends on the operation mode. For global
shutter mode, the sensor always reads out the entire line,
independent of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual LVDS channels,
while the regular image data is compensated (can be
bypassed).
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
10
9
6
3
2
The polynomial is x +x +x +x +x +x+1. The CRC
encoder is seeded at the start of a new line and updated for
every (valid) data word received. The CRC seed is
configurable usign the crc_seed register. When ‘0’, the CRC
is seeded by all-‘0’; when ‘1’ it is seeded with all-‘1’.
On the output interface, black lines can be seen as a
separate window, without frame start and ends (only line
start and ends). The window ID is to be ignored and data is
indicated by a BL code.
NOTE: Note The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Example Using Multiple Windowing
Figure 34 shows an example of the synchronization codes sent when reading out multiple windows.
LS+0+IMGx(x_size0-4)+FE+0+CRC
LS+0+IMGx(x_size0-4)+LE+0+CRC
ROI0
where
FS+0+IMGx(x_size0-4)+LE+0+CRC
LS+DC+BLx156+LE+DC+CRC
x_size0 = x_end0 - x_start0 ꢀ+ ꢀ1
DC = “Don't Care"
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+FE+0ꢀ+CꢀRC
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+CꢀRC
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+LꢀS+1ꢀ+IMꢀGx(x_ꢀsizeꢀ1-4ꢀ)+FE+1ꢀ+CꢀRC
ROI1
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+LꢀS+1ꢀ+IMꢀGx(x_ꢀsizeꢀ1-4ꢀ)+LꢀE+1+CꢀRC
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+FS+1ꢀ+IMꢀGx(x_ꢀsizeꢀ1ꢀ-4ꢀ)+LE+1ꢀ+CꢀRC
ROI0
LꢀS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+CꢀRC
where
FS+0ꢀ+IMGx(x_ꢀsizeꢀ0ꢀ-4ꢀ)+LꢀE+0ꢀ+CꢀRC
x_size0 = x_end0 - x_start0 ꢀ+ ꢀ1
x_size1 = x_end1 - x_start1 ꢀ+ ꢀ1
DC = “Don't Care"
LS+DC+BLx156+LE+DC+CRC
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+FE+0+CꢀRC
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+CꢀRC
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+LS+1ꢀ+IMGx(x_ꢀsize1)+FE+ ꢀ+CꢀRC
ROI1
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+LS+1ꢀ+IMGx(x_ꢀsize1-4)+LE+1+CꢀRC
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+FS+1ꢀ+IMGx(x_ꢀsize1ꢀ-4)+LE+1ꢀ+CꢀRC
ROI0
LꢀS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+CꢀRC
where
FS+0+IMGx(x_sizeꢀ0-4ꢀ)+LE+0+CꢀRC
x_size0 = x_end0 - x_start0 ꢀ+ ꢀ1
x_size1 = x_end1 - x_start1 ꢀ+ ꢀ1
DC = “Don't Care"
LꢀS+DꢀCꢀ+BLx156ꢀ+ ꢀE+
ꢀ ꢀ+CRC
LS+1+IMGx(x_size1-4)+FE+1+ ꢀRC
LS+1+IMGx(x_size1-4)+LE+1+ ꢀRC
LS+0+IMGx(x_size0-overlap1_0-2)+LS+1+IMGx(x_size1-4)+LE+1+CꢀRC
ROI1
LS+0+IMGx(x_size0-overlap1_0-2)+LS+1+IMGx(x_size1-4)+LE+1+CꢀRC
ROI0
LS+0+IMGx(x_size0-overlap1_0-2)+FS+1+IMGx(x_size1ꢀ-4)+LE+1+C
LS+0+IMGx(x_size0-4)+LE+0+ ꢀRC
RC
FS+0+IMGx(x_size0-4)+LE+0+CꢀRC
where
x_size0 = x_end0 - x_start0 ꢀ+ ꢀ1
x_size1 = x_end1 - x_start1 ꢀ+ ꢀ1
overlap1_0 = x_end0 - ꢀx_start1 +1
DC = “Don't Care"
LS+DC+BLx156+LE+DC+CRC
Figure 34. Synchronization Codes for Multiple Windows (applicable for Global Shutter only)
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
LVDS Output Multiplexing
8
Ch0, Ch1, Ch2, Ch3
Ch0
4
The PYTHON sensor contains
a
function for
Ch4, Ch5, Ch6, Ch7
Ch4
down−multiplexing the output channels. Using this
function, one may for instance use the PYTHON XK with
16, 8 or 4 datachannels instead of 32 data channels.
Enabling the down−multiplexing is done through the
muxmode[1:0] pins. Connecting these pins to ground
disables all down−multiplexing. Configuring higher values
sets a higher degree of down−multiplexing. The channels
that are used per degree of multiplexing are shown in Table
27. The unused data channels are powered down and will not
send any data.
Ch8, Ch9, Ch10, Ch11
Ch12, Ch13, Ch14, Ch15
Ch16, Ch17, Ch18, Ch19
Ch20, Ch21, Ch22, Ch23
Ch24, Ch25, Ch26, Ch27
Ch28, Ch29, Ch30, Ch31
Ch8
Ch12
Ch16
Ch20
Ch24
Ch28
Ch0
4
Ch0, Ch1, Ch2, Ch3,
Ch4, Ch5, Ch6, Ch7
8
Note the maximum frequency for the SPI interface needs
to scale with the amount of LVDS channels as described in
Table 5.
Ch8, Ch9, Ch10, Ch11,
Ch12, Ch13, Ch14, Ch15
Ch8
Ch16, Ch17, Ch18, Ch19, Ch16
Ch20, Ch21, Ch22, Ch23
Table 27. LVDS CHANNEL MULTIPLEXING
No. of
Ch24, Ch25, Ch26, Ch27, Ch24
Ch28, Ch29, Ch30, Ch31
No. of
LVDS
outputs
Repetition
of Sync
Codes
Output
Channel
Table 28 shows how to select the desired output multiplex
mode and describes the required register upload needed to
guarantee the correct functionality of the sensor.
Channels Multiplexed
32
16
No multiplexing
Ch0 to
Ch31
1
Ch0, Ch1
Ch0
2
Table 28. OUTPUT MULTIPLEX MODE SELECTION
Number of
Ch2, Ch3
Ch2
Required Upload
Output
Ch4, Ch5
Ch4
muxmode1 muxmode0
LVDS
Ch6, Ch7
Ch6
Address
211
Data
(Pin F24)
(Pin F25)
Channels
Ch8, Ch9
Ch8
0
0
32
16
8
0x0E5B
0x0E4B
0x0E3B
0x0E2B
Ch10, Ch11
Ch12, Ch13
Ch14, Ch15
Ch16, Ch17
Ch18, Ch19
Ch20, Ch21
Ch22, Ch23
Ch24, Ch25
Ch26, Ch27
Ch28, Ch29
Ch30, Ch31
Ch10
Ch12
Ch14
Ch16
Ch18
Ch20
Ch22
Ch24
Ch26
Ch28
Ch30
0
3.3 V
0
211
3.3 V
3.3 V
211
3.3 V
4
211
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Data Order
Figure 35 indicates how the kernels are organized. The
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is 64
pixels in x-direction by one pixel in y-direction.
data order of this image data on the data output channels
depends on the subsampling mode.
kernel
(79,5119)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
61 62 63
Figure 35. Kernel Organization in Pixel Array
Figure 36 shows how a kernel is read out over the 32
• P1−SE/SN/FN: Subsampling Disabled
output channels. For even positioned kernels, the kernels are
read out ascending, and for odd positioned kernels the data
order is reversed (descending).
♦ 32 LVDS Output Channels
The image data is read out in kernels of 64 pixels in
x-direction by one pixel in y-direction. One data channel
output delivers two pixel values of one kernel sequentially.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
2
3
4
59 60 61 62 63
pixel # (even kernel)
pixel # (odd kernel)
63 62 61 60 59
4
3
2
1
0
MSB
LSB MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 36. 32 LVDS Data Output Order when Subsampling is Disabled
♦ 16 LVDS Output Channels
the kernels are read out ascending but in pair of even and odd
pixels, while for odd positioned kernles the data order is
reversed (descending) but in pair of even and odd pixels.
Figure 37 shows how a kernel is read out over the 16
output channels. Each pair of adjacent channels is
multiplexed into one channel. For even positioned kernels,
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel # (even kernel)
0
2
1
3
4
6
5
7
56 58 57 59 60 62 61 63
pixel # (odd kernel) 63 61 62 60 59 57 58 56
7
5
6
4
3
1
2
0
nd
Every 2
channel
MSB
LSB MSB
LSB
Note: The bit order is always MSB first,
regardless the kernel number
10−bit
10−bit
Figure 37. Data Output Order for 16 LVDS Outputs when Subsampling is Disabled
♦ 8 LVDS Output Channels
the kernels are read out ascending but in sets of 4 even and
4 odd pixels, while for odd positioned kernles the data order
is reversed (descending) but in sets of 4 odd and 4 even
pixels.
Figure 38 shows how a kernel is read out over the 8 output
channels. Each bunch of four adjacent channels is
multiplexed into one channel. For even positioned kernels,
kernel N−2
kernel N−1
kernel N
kernel N+1
pixel #
(even kernel)
0
2
4
6
1
3
5
7
8
10 12 14 9 11 13 15
48 50 52 54 49 51 53 55 56 58 60 62 57 59 61 63
15 13 11 14 12 10 8
63 61 59 57 62 60 58 56 55 53 51 49 54 52 50 48
9
7
5
3
1
6
4
2
0
pixel #
(odd kernel)
th
Every 4
channel
Note: The bit order is always MSB first,
regardless the kernel number
MSB
10−bit
LSB MSB
10−bit
LSB
Figure 38. Data Output Order for 8 LVDS Outputs when Subsampling is Disabled
♦ 4 LVDS Output Channels
the kernels are read out ascending but in sets of 8 even and
8 odd pixels, while for odd positioned kernles the data order
is reversed (descending) but in sets of 8 odd and 8 even
pixels.
Figure 39 shows how a kernel is read out over the 4 output
channels. Each bunch of eight adjacent channels is
multiplexed into one channel. For even positioned kernels,
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
kernel N−2 kernel N−1
kernel N
kernel N+1
pixel #
0
2
4
6
8
10 12 14 1
3
5
7
9
11 13 15
48 50 52 54 56 58 60 62 49 51 53 55 57 59 61 63
15 13 11 14 12 10 8
(even kernel)
pixel #
(odd kernel)
63 61 59 57 55 53 51 49 62 60 58 56 54 52 50 48
9
7
5
3
1
6
4
2
0
th
Every 8
channel
Note: The bit order is always MSB first,
regardless the kernel number
MSB
LSB MSB
LSB
10−bit
10−bit
Figure 39. Data Output Order for 4 LVDS Outputs when Subsampling is Disabled
♦ 32 LVDS Output Channels
Figure 40 shows the data order for 32 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
• Subsampling on Monochrome Sensors
During subsampling, every other pixel is read out and the
lines are read in a read-1-skip-1 manner. To read out the
image data with subsampling enabled, two neighboring
kernels are combined to a single kernel of 128 pixels in the
x-direction and one pixel in the y-direction.
Note that there is no difference in data order for even and
odd kernel numbers. This is opposed to the
‘no-subsampling’ readout described earlier.
kernel N−2
kernel N−1
pixel #
kernel N
kernel N+1
0
126
2
124
4
68 60 66 62 64
Figure 40. Data Output Order for 32 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
♦ 16 LVDS Output Channels
Figure 41 shows the data order for 16 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
kernel N−2
pixel #
kernel N−1
kernel N
kernel N+1
0
2
126 124
4
6
122 120
56 58 70 68 60 62 66 64
Every 2nd
channel
Figure 41. Data Output Order for 16 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
♦ 8 LVDS Output Channels
Figure 42 shows the data order for 8 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
2
4
6
126 124 122 120
8
10 12 14 118 116 114 112
48 50 52 54 78 76 74 72 56 58 60 62 70 68 66 64
pixel #
th
Every 4
channel
Figure 42. Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
♦ 4 LVDS Output Channels
Figure 43 shows the data order for 4 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
2
4
6
8
10 12 14 126 124 122 120 118 116 114 112
48 50 52 54 56 58 60 62 78 76 74 72 70 68 66 64
th
Every 8
channel
Figure 43. Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
the y-direction. Only the pixels 0, 1, 4, 5, 8, 9, 12, 13 to 124,
• Binning Mode
and 125 are read out. There is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no-subsampling’ readout described in section.
The output order in binning mode is identical to the
subsampled mode.
• Subsampling on Color Sensor
♦ 32 LVDS Output Channels
Figure 44 shows the data order for 32 LVDS output
channels.
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
single kernel of 128 pixels in the x-direction and 1 pixel in
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
kernel N−2
kernel N−1
kernel N
kernel N+1
0
1
125 124
4
5
121 120
56 57
69 68
60 66
65 64
pixel #
Figure 44. Data Output Order for 32 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 16 LVDS Output Channels
Figure 45 shows the data order for 16 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
125
1
124
4
121
5
120
56
69 57
68 60
65
61 64
pixel #
Every 2nd
channel
Figure 45. Data Output Order for 16 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 8 LVDS Output Channels
Figure 46 shows the data order for 8 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
kernel N−2
kernel N−1
kernel N
kernel N+1
0
125
4
121
1
124
5
120
8
117 12 113
9
116 13 112
48 77 52 73 49 76 53 72 56 69 60 65 57 68 61 64
pixel #
th
Every 4
channel
Figure 46. Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 4 LVDS Output Channels
Figure 47 shows the data order for 4 LVDS output
channels.
Note that there is no difference in data order for even/odd
kernel numbers, as opposed to the ‘no−subsampling’
readout described in section 0.
www.onsemi.com
47
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
kernel N−2
kernel N−1
kernel N
kernel N+1
0
125
4
121
8
117 12 113
1
124
5
120
9
116 13 112
48 77 52 73 56 69 60 65 49 76 53 72 57 68 61 64
th
Every 8
channel
Figure 47. Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor
Frame Rate
where t
represents the equivalent ROT time for a
ROT
Frame rate for subsampling and binning mode is
compared to the normal mode. Assume the y-resolution is
the programmed number of lines to read out.
normal readout of the same frame. Analogous readout
represents the equivalent readout time for normal readout.
Test Pattern Generation
Normal Readout
The frame time in normal readout mode is shown by the
following formula:
The data block provides several test pattern generation
capabilities. Figure 48 shows the functional diagram for the
data channels. It is possible to inject synthesized test patterns
at various points. Refer to the Register Map on page 50 for
the test mode configuration registers (registers 144 to 150).
The test pattern modes are summarized in Table 29. Note
that these modes only exist for the data channel. The sync
and clock channels do not provide this functionality.
For each test mode, the user can select whether the
generated data is framed. When the register
frame_testpattern is asserted, the test data simply replaces
the ADC data. This means that the test data is only sent
between frame/line start and frame/line end indications.
Outside these windows, regular training patterns are sent, as
during normal operation. CRC is calculated and inserted as
for normal data for the fixed and incrementing test pattern
generation.
Frame Time = t
+ (y-resolution) x (t
+ t
)
FOT
ROT
readout
The frame rate is equal to 1/FrameTime. Nominal frame
rate for full frame readout is 80 fps in Zero−ROT mode.
Subsampling Mode
The frame time for subsampled readout is shown by the
following formula:
Frame Time = t
+ (y-resolution / 2) x (t
+ t
/ 2),
FOT
ROT readout
where t
represents the equivalent ROT time for a
ROT
normal readout of the same frame. Analogous readout
represents the equivalent readout time for normal readout.
Binning Mode
The frame time for subsampled readout is given by the
following formula:
Frame Time = t
/ 2),
+ (y-resolution / 2) x (t x 2+ t
ROT readout
FOT
Table 29. TEST MODE SUMMARY
Register Configuration
prbs_en
testpattern_en
testpattern
Description
0
0
0
1
X
0
Normal operation mode
Fixed pattern generation.
Pattern is defined by testpattern register
0
1
1
1
Incrementing pattern generation.
Initial value is determined by testpattern.
X
X
PRBS data generation. The testpattern register determines the seed for the
PRBS generator.
When frame_testpattern is deasserted, the output is constantly replaced by the generated test data. No training patterns are
generated.
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48
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Blackꢀ Levꢀel
adc_db_data_0
Caꢀlibꢀration
CRC
Calculation
Blackꢀ Levꢀel
adc_db_data_1
Caꢀlibꢀration
`0ꢀ'
`1'
`0'
`0ꢀ'
`
`
ꢀ'
ꢀ'
`1ꢀ'
`
`
ꢀ'
ꢀ'
`1ꢀ'
Test Pattern
Generation
tesꢀtpattern_er
prbsꢀ_en
PRBS
Generator
training pattern
(testpattern_en and not frame_testpattern)
i ꢀseꢀrt CRC
bypass
Figure 48. Functional Block Diagrams for the Data Channels
NOTE: In the figure, register configurations are
indicated in red.
The sync channel continues to send regular frame timing
information when the sequencer is enabled (independently
of the test pattern configurations).
The synthesized test patterns are injected directly into the
data channels. Therefore, no data demultiplexing is required
at the receiving end (as opposed to regular image data
capture).
Pseudo Random Bit Sequence Generation
In this test mode, the output channels are sourced with
pseudo random bit sequence (PRBS) pattern. The PRBS
seed can be configured for each data channel using the
testpattern register. For the other test pattern generation
mode, the datastream is not interrupted when
frame_testpattern is deasserted.
NOTES:
• The CRC generator is not functional in this mode, and
no real CRC can be calculated. Instead, the CRC slot is
used to send one more PRBS word.
Fixed Pattern
A configured word can be continuously repeated on the
output. This word is configurable for each data channel
separately (testpattern). The testpattern is inserted when
testpattern_en is asserted.
• A PRBS generator does not generate random data when
the seed is all zero. Therefore, it is advisable to
configure the testpattern registers to a value different
from ‘0’. Using different seeds for each channel results
in different sequences for each data channel.
Incrementing Test Pattern
In each cycle, the test pattern word is incremented by one,
when inc_testpattern is asserted. After reaching the
maximum value, the incrementer is reset to its start value
(testpattern). When the testdata is framed, the incrementer
is also reset to the testpattern value at each line start.
To enable this mode, enable the digital testpattern mode
(assert testpattern_en) and assert inc_testpattern.
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49
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
REGISTER MAP
Each functional entity has a dedicated address space,
starting at a block offset. The register address is obtained by
adding the address offset to the block offset. This address
must be used to perform SPI uploads and is shown in the
Address column of the register map table.
The table below represents the register map for the
NOIP1xx025KA part. Deviating default values for the
NOIP1xx16KA, NOIP1xx12KA and NOIP1xx10KA are
mentioned between brackets (“[]”).
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
Default
Description
Type
Status
Status
Chip ID
0
0
1
0
1
chip_id
0x50FA
0x50FA
0x0000
0x0
20730
Chip ID
[15:0]
id
20730
Chip ID
reserved
reserved
resolution
0
0
0
Reserved
Reserved
[3:0]
[9:8]
0x0
P25K: 0, P16K: 1,
P12K: 2, P10K: 3
[11:10]
reserved
0x0
0
0
Reserved
2
2
chip_configuration
0x0000
Chip General
Configuration
RW
[0]
color
0x0
0
Color/Monochrome
Configuration
’0’: Monochrome
’1’: Color
[1]
reserved
reserved
0x0
0x0
0
0
Reserved
Reserved
[15:2]
Reset Gen-
erator
8
0
8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0099
0x9
153
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
[3:0]
[7:4]
9
0x9
9
1
2
9
0x0009
0x9
9
RW
RW
[3:0]
9
2457
9
10
0x0999
0x9
[3:0]
[7:4]
0x9
9
[11:8]
0x9
9
16
0
1
16
17
0x0004
0x0
4
0
RW
RW
[0]
[1]
[2]
0x0
0
0x1
1
0x2113
0x13
0x1
8467
19
1
[7:0]
[12:8]
[14:13]
0x1
1
20
24
0
0
20
24
0x0000
0x0
0
0
0
0
RW
[0]
[9:8]
[10]
0x0
0x0
0x0000
0x0
0
0
Status
[0]
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50
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
8832
128
2
Description
Reserved
Type
2
3
26
0x2280
0x80
RW
[7:0]
[10:8]
[14:12]
reserved
reserved
reserved
reserved
reserved
reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2
0x2
2
27
32
0x3D2D
0x2D
0x3D
15661
45
RW
RW
[7:0]
[15:8]
61
Clock Gen-
erator
32
0
config0
0x0004
0x0
4
0
Clock Generator Config-
uration
[0]
enable_analog
Enable analogue clocks
’0’: disabled,
’1’: enabled
[1]
[2]
reserved
reserved
reserved
mux
0x0
0x1
0x0
0x0
0x0
0x0
0
1
0
0
0
0
Reserved
Reserved
Reserved
Multiplex Mode
Reserved
Reserved
[3]
[5:4]
[11:8]
[14:12]
reserved
reserved
General
Logic
34
0
34
config0
enable
0x0000
0x0
0
0
Clock Generator Config-
uration
RW
[0]
Logic General Enable
Configuration
’0’: Disable
’1’: Enable
38
40
0
1
38
39
reserved
reserved
reserved
reserved
0x0000
0x0000
0x0000
0x0000
0
0
0
0
Reserved
Reserved
Reserved
Reserved
RW
RW
[15:0]
[15:0]
Image
Core
0
40
image_core_config0
imc_pwd_n
0x0000
0x0
0
0
Image Core
Configuration
RW
[0]
[1]
[2]
Image Core Power
Down
’0’: powered down,
’1’: powered up
mux_pwd_n
0x0
0x0
0
0
Column Multiplexer
Power Down
’0’: powered down,
’1’: powered up
colbias_enable
Bias Enable
’0’: disabled
’1’: enabled
1
41
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0x0B5A
0xA
2906
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
[3:0]
[7:4]
[10:8]
[12:11]
[13]
10
5
0x5
0x3
3
0x1
1
0x0
0
[14]
0x0
0
[15]
0x0
0
2
42
0x0001
1
RW
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51
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
[0]
[1]
0x1
0x0
1
0
0
0
0
0
0
0
0
0
0
0
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[6:4]
[10:8]
[15:12]
0x0
0x0
0x0
3
43
0x0000
0x0
RW
[0]
[1]
0x0
[2]
0x0
[3]
0x0
[6:4]
[7]
0x0
0x0
[15:8]
0x0
AFE
Bias
48
64
0
48
power_down
pwd_n
0x0000
0x0
0
0
AFE Configuration
RW
[0]
Power down for AFE’s
’0’: powered down,
’1’: powered up
0
1
64
65
power_down
pwd_n
0x0000
0x0
0
0
Bias Power Down Con-
figuration
RW
RW
[0]
[0]
Power down bandgap
’0’: powered down,
’1’: powered up
configuration
extres
0x888B
0x1
34955
1
Bias Configuration
External Resistor
Selection
’0’: internal resistor,
’1’: external resistor
[3:1]
[7:4]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
lvds_bias
lvds_ibias
lvds_iref
reserved
reserved
reserved
reserved
reserved
reserved
0x5
0x8
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LVDS Bias Configuration
LVDS Ibias
LVDS Iref
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
[11:8]
[15:12]
0x8
8
0x8
8
2
3
66
67
0x53C8
0x8
21448
RW
RW
[3:0]
[7:4]
8
0xC
12
[14:8]
0x53
0x8888
0x8
83
34952
[3:0]
[7:4]
8
0x8
8
[11:8]
[15:12]
0x8
8
0x8
8
4
5
68
69
0x0088
0x8
136
RW
RW
[3:0]
[7:4]
8
0x8
8
0x0888
0x8
2184
[3:0]
[7:4]
8
0x8
8
[11:8]
0x8
8
34952
8
6
70
0x8888
0x8
RW
[3:0]
www.onsemi.com
52
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
[7:4]
[11:8]
[15:12]
0x8
0x8
8
8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x8
8
7
0
71
72
0x8888
0x8888
34952
34952
RW
RW
[15:0]
72
0x2220
0x0
8736
[0]
[1]
0
0
0
2
2
2
0x0
[2]
0x0
[6:4]
[10:8]
[14:12]
0x2
0x2
0x2
80
0
80
0x0000
0x0
0
RW
[1:0]
[3:2]
[5:4]
[7:6]
[9:8]
0
0x0
0
0x0
0
0
0x0
0x0
0
1
0
81
96
0x8881
0x8881
34945
34945
RW
RW
[15:0]
Tempera-
ture Sensor
96
enable
enable
0x0000
0x0
0
0
Temperature Sensor
Configuration
[0]
Temperature Diode
Enable
’0’: disabled,
’1’: enabled
[1]
[2]
reserved
reserved
reserved
reserved
reserved
offset
0x0
0x0
0x0
0x0
0x0
0x0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
[3]
[4]
[5]
[13:8]
Temperature Offset
(signed)
1
97
temp
0x0000
0x00
0
0
Temperature Sensor
Status
Status
[7:0]
temp
Temperature Readout
Reserved
104
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0
1
104
105
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
Reserved
RW
RW
[15:0]
Reserved
0x0000
0x0
Reserved
[1:0]
[6:2]
[7]
Reserved
0x0
Reserved
0x0
Reserved
[9:8]
[14:10]
[15]
0x0
Reserved
0x0
Reserved
0x0
Reserved
2
106
0x0000
Reserved
Status
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53
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
107
Register Name
reserved
Default
Description
Reserved
Type
Status
Status
Status
Status
Status
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0
0
0
0
0
0
0
0
0
0
0
3
4
5
6
7
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
108
109
110
111
Serializers/
LVDS/IO
112
0
112
power_down
0x0000
0x0
0
0
LVDS Power Down Con-
figuration
RW
[0]
[1]
[2]
clock_out_pwd_n
Power down for Clock
Output.
’0 ’: powered down,
’1’: powered up
sync_pwd_n
data_pwd_n
0x0
0x0
0
0
Power down for Sync
channel
’0’: powered down,
’1’: powered up
Power down for data
channels (4 channels)
’0’: powered down,
’1’: powered up
Sync
Words
116
4
116
trainingpattern
trainingpattern
0x03A6
0x3A6
934
934
Data Formating −
Training Pattern
RW
[9:0]
Training pattern sent on
Data channels during
idle mode. This data is
used to perform word
alignment on the LVDS
data channels.
5
6
117
118
sync_code0
frame_sync_0
sync_code1
bl_0
0x002A
0x02A
0x0015
0x015
42
42
21
21
LVDS Power Down Con-
figuration
RW
RW
[6:0]
[9:0]
Frame Sync Code LSBs
− Even kernels
Data Formating − BL In-
dication
Black Pixel Identification
Sync Code − Even
kernels
7
8
119
120
sync_code2
img_0
0x0035
0x035
53
53
Data Formating − IMG
Indication
RW
RW
[9:0]
[9:0]
[6:0]
Valid Pixel Identification
Sync Code − Even
kernels
sync_code3
ref_0
0x0025
0x025
37
37
Data Formating − IMG
Indication
Reference Pixel Identifi-
cation Sync Code −
Even kernels
9
121
122
sync_code4
frame_sync_1
sync_code5
0x002A
0x02A
42
42
21
LVDS Power Down Con-
figuration
RW
RW
Frame Sync Code LSBs
− Odd kernels
10
0x0015
Data Formating − BL In-
dication
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54
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
bl_1
Default
Description
Type
[9:0]
[9:0]
[9:0]
[9:0]
0x015
21
Black Pixel Identification
Sync Code − Odd
kernels
11
12
123
sync_code6
img_1
0x0035
0x035
53
53
Data Formating − IMG
Indication
RW
Valid Pixel Identification
Sync Code − Odd
kernels
124
sync_code7
ref_1
0x0025
0x025
37
37
Data Formating − IMG
Indication
RW
Reference Pixel Identifi-
cation Sync Code − Odd
kernels
13
14
125
126
sync_code8
0x0059
0x059
89
89
Data Formating − CRC
Indication
RW
RW
crc
CRC Value Identification
Sync Code
sync_code9
tr
0x03A6
0x3A6
934
934
Data Formating − TR In-
dication
[9:0]
[9:0]
Training Value Identifica-
tion Sync Code
15
0
127
128
reserved
reserved
0x02AA
0x2AA
682
682
Reserved
Reserved
RW
RW
Data Block
128
blackcal
0x4008
0x08
0x0
16392
Black Calibration Config-
uration
[7:0]
black_offset
black_samples
8
0
Desired black level at
output
[10:8]
Black pixels taken into
account for black
calibration.
Total samples =
2**black_samples
[14:11]
[15]
reserved
crc_seed
0x8
0x0
8
0
Reserved
CRC Seed
’0’: All−0
’1’: All−1
1
129
general_configuration
auto_blackcal_enable
0x0001
0x1
1
1
Black Calibration and
Data Formating
Configuration
RW
[0]
Automatic
blackcalibration is
enabled when 1,
bypassed when 0
[9:1]
[10]
blackcal_offset
0x00
0x0
0
0
Black Calibration offset
used when au-
to_black_cal_en = ’0’.
blackcal_offset_dec
blackcal_offset is added
when 0, subtracted when
1
[11]
[12]
[13]
[14]
reserved
reserved
reserved
ref_mode
0x0
0x0
0x0
0x0
0
0
0
0
Reserved
Reserved
Reserved
Data contained on
reference lines:
’0’: reference pixels
’1’: black average for the
corresponding data
channel
[15]
ref_bcal_enable
0x0
0
Enable black calibration
on reference lines
’0’: Disabled
’1’: Enabled
www.onsemi.com
55
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
2
130
0x000F
0x1
15
1
RW
[0]
[1]
[2]
[3]
[4]
[8]
reserved
Reserved
reserved
0x1
1
Reserved
reserved
0x1
1
Reserved
reserved
0x1
1
Reserved
reserved
0x0
0
Reserved
reserved
0x0
0
Reserved
8
9
136
137
138
139
blackcal_error0
blackcal_error[15:0]
0x0000
0x0000
0
Black Calibration Status
Status
Status
Status
Status
[15:0]
[15:0]
[15:0]
[15:0]
0
Black Calibration Error.
This flag is set when not
enough black samples
are availlable. Black
Calibration shall not be
valid. Channels 0−16
blackcal_error1
0x0000
0x0000
0
0
Black Calibration Status
blackcal_error[31:16]
Black Calibration Error.
This flag is set when not
enough black samples
are availlable. Black
Calibration shall not be
valid. Channels 16−31
10
11
blackcal_error2
0x0000
0x0000
0
0
Black Calibration Status
blackcal_error[47:32]
Black Calibration Error.
This flag is set when not
enough black samples
are availlable. Black
Calibration shall not be
valid. Channels 32−47
blackcal_error3
0x0000
0x0000
0
0
Black Calibration Status
blackcal_error[63:48]
Black Calibration Error.
This flag is set when not
enough black samples
are availlable. Black
Calibration shall not be
valid. Channels 48−63
12
13
16
140
141
144
reserved
0x0000
0x0000
0xFFFF
0xFFFF
0x0000
0
0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
[15:0]
[15:0]
reserved
reserved
65535
65535
0
reserved
test_configuration
Data Formating Test
Configuration
[0]
[1]
testpattern_en
inc_testpattern
0x0
0x0
0
0
Insert synthesized test-
pattern when ’1’
Incrementing testpattern
when ’1’, constant test-
pattern when ’0’
[2]
[3]
prbs_en
0x0
0x0
0
0
Insert PRBS when ’1’
frame_testpattern
Frame test patterns
when ’1’, unframed
testpatterns when ’0’
[4]
reserved
0x0
0
0
Reserved
Reserved
Reserved
17
18
145
146
reserved
0x0000
RW
RW
[15:0]
reserved
0
test_configuration0
0x0100
0x00
256
Data Formating Test
Configuration
[7:0]
testpattern0_lsb
0
Testpattern used on
datapath #0 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
www.onsemi.com
56
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
Default
Description
Type
[15:8]
testpattern1_lsb
0x01
1
Testpattern used on
datapath #1 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
19
20
21
22
147
test_configuration1
testpattern2_lsb
0x0302
0x02
770
2
Data Formating Test
Configuration
RW
[7:0]
Testpattern used on
datapath #2 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
[15:8]
testpattern3_lsb
0x03
3
Testpattern used on
datapath #3 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
148
149
150
test_configuration2
testpattern4_lsb
0x0504
0x04
1284
4
Data Formating Test
Configuration
RW
RW
RW
[7:0]
Testpattern used on
datapath #4 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
[15:8]
testpattern5_lsb
0x05
5
Testpattern used on
datapath #5 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
test_configuration3
testpattern6_lsb
0x0706
0x06
1798
6
Data Formating Test
Configuration
[7:0]
Testpattern used on
datapath #6 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
[15:8]
testpattern7_lsb
0x07
7
Testpattern used on
datapath #7 when
testpattern_en = ’1’.
Note: Most significant
bits are configured in
register 150.
test_configuration16
testpattern0_msb
testpattern1_msb
testpattern2_msb
testpattern3_msb
testpattern4_msb
testpattern5_msb
testpattern6_msb
testpattern7_msb
reserved
0x0000
0x0
0
0
0
0
0
0
0
0
0
0
Data Formating Test
Configuration
[1:0]
[3:2]
Testpattern used when
testpattern_en = ’1’
0x0
Testpattern used when
testpattern_en = ’1’
[5:4]
0x0
Testpattern used when
testpattern_en = ’1’
[7:6]
0x0
Testpattern used when
testpattern_en = ’1’
[9:8]
0x0
Testpattern used when
testpattern_en = ’1’
[11:10]
[13:12]
[15:14]
0x0
Testpattern used when
testpattern_en = ’1’
0x0
Testpattern used when
testpattern_en = ’1’
0x0
Testpattern used when
testpattern_en = ’1’
26
154
0x0000
Reserved
RW
www.onsemi.com
57
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
[15:0]
[15:0]
0x0000
0x0000
0x0000
0
0
0
27
0
155
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
160
160
0x0010
0x0
16
0
RW
[0]
[1]
[2]
[3]
[4]
0x0
0
0x0
0
0x0
0
0x1
1
1
161
0x60B8
0xB8
24760
184
24
RW
[9:0]
[15:10]
0x018
0x0080
0x80
2
3
4
5
6
7
162
163
164
165
166
167
128
128
128
128
128
128
128
128
1023
1023
2048
0
RW
RW
RW
RW
RW
RW
[9:0]
[9:0]
[9:0]
[9:0]
[15:0]
0x0080
0x80
0x0080
0x80
0x0080
0x80
0x03FF
0x03FF
0x0800
0x0
[1:0]
[3:2]
0x0
0
[15:4]
0x080
0x0001
0x0001
0x0800
0x0
128
1
8
9
168
169
RW
RW
[15:0]
1
2048
0
[1:0]
[3:2]
0x0
0
[15:4]
0x080
0x03FF
0x03FF
0x100D
0x1
128
1023
1023
4109
1
10
11
170
171
RW
RW
[15:0]
[1:0]
[3:2]
0x3
3
[15:4]
0x100
0x0083
0x083
0x00
256
131
131
0
12
172
RW
[7:0]
[13:8]
[15:14]
0x0
0
13
14
173
174
0x2824
0x024
0x028
0x2A96
0x6
10276
36
RW
RW
[7:0]
[15:8]
40
10902
6
[3:0]
www.onsemi.com
58
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
9
Description
Reserved
Type
[7:4]
[11:8]
[15:12]
0x9
0xA
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
10
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2
15
16
17
18
19
20
21
24
25
26
175
176
177
178
179
180
181
184
185
186
0x0080
0x080
0x0100
0x100
0x0100
0x100
0x0080
0x080
0x00AA
0x0AA
0x0100
0x100
0x0155
0x155
0x0000
0x0000
0x0000
0x0
128
128
256
256
256
256
128
128
170
170
256
256
341
341
0
RW
RW
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[15:0]
[7:0]
RW
RW
RW
RW
RW
Status
Status
Status
0
0
0
0x0000
0x000
0x0
0
[9:0]
[12]
0
0
27
28
187
188
0x0000
0x0000
0x0000
0x0
0
Status
Status
[15:0]
0
0
[1:0]
[3:2]
0
0x0
0
[15:4]
0x000
0x0000
0x000
0x0
0
29
189
192
0
Status
RW
[12:0]
[13]
0
0
Sequencer
192
0
general_configuration
enable
0x0000
0x0
0
0
Sequencer General
Configuration
[0]
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
[2]
reserved
0x0
0x0
0
0
Reserved
zero_rot_enable
Zero ROT mode
Selection.
‘0’: Normal ROT,
‘1’: Zero ROT’
[3]
[4]
reserved
0x0
0x0
0
0
Reserved
triggered_mode
Triggered Mode
Selection
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection
‘0’: master,
‘1’: slave
www.onsemi.com
59
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
Default
Description
Type
[6]
nzrot_xsm_delay_en-
able
0x0
0
Insert delay between
end of ROT and start of
readout in normal ROT
readout mode if ‘1’.
ROT delay is defined by
register xsm_delay
[7]
[8]
subsampling
binning
0x0
0x0
0
0
Subsampling mode
selection
‘0’: no subsampling,
‘1’: subsampling
Binning mode selection
‘0’: no binning,
‘1’: binning
[10]
reserved
0x0
0x0
0
0
Reserved
[13:11]
monitor_select
Control of the monitor
pins
[14]
[15]
reserved
0x0
0x0
0
0
Reserved
sequence
Enable a sequenced
readout with different
parameters for even and
odd frames.
1
2
193
194
reserved
0x0000
0x00
0x00
0x00E4
0x0
0
0
Reserved
RW
RW
[7:0]
reserved
Reserved
[15:8]
reserved
0
Reserved
integration_control
reserved
228
0
Integration Control
Reserved
[0]
[1]
[2]
reserved
0x0
0
Reserved
fr_mode
0x1
1
Representation of
fr_length.
‘0’: reset length
‘1’: frame length
[3]
[4]
reserved
0x0
0x0
0
0
Reserved
int_priority
Integration Priority
‘0’: Frame readout has
priority over integration
‘1’: Integration End has
priority over frame read-
out
[5]
halt_mode
0x1
1
The current frame will be
completed when the
sequencer is disabled
and halt_mode = ‘1’.
When ‘0’, the sensor
stops immediately when
disabled, without fin-
ishing the current frame.
[6]
[7]
fss_enable
fse_enable
0x1
0x1
1
1
Generation of Frame
Sequence Start Sync
code (FSS)
‘0’: No generation of
FSS
‘1’: Generation of FSS
Generation of Frame
Sequence End Sync
code (FSE)
‘0’: No generation of
FSE
‘1’: Generation of FSE
[8]
[9]
reverse_y
reserved
0x0
0x0
0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
Reserved
www.onsemi.com
60
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
Default
Description
Type
[11:10]
subsampling_mode
0x0
0
Subsampling mode
0x0: Subsampling in x
and y (VITA compatible)
0x1: Subsampling in x,
not y
0x2: Subsampling in y,
not x
0x3: Subsampling in x
an y
[13:12]
binning_mode
0x0
0
Binning mode
0x0: Binning in x and y
(VITA compatible)
0x1: Binning in x, not y
0x2: Binning in y, not x
0x3: Binning in x an y
[14]
[15]
reserved
0x0
0x0
0
0
1
1
Reserved
reserved
Reserved
3
4
5
195
196
197
roi_active0_0
roi_active0
0x0001
0x01
Active ROI Selection
RW
RW
RW
[15:0]
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
roi_active1_0
roi_active1_0
0x0000
0x0000
0
0
Active ROI Selection
[15:0]
Active ROI Selection
[0] Roi16 Active
[1] Roi17 Active
...
[15] Roi31 Active
black_lines
black_lines
0x0102
0x02
258
2
Black Line Configuration
[7:0]
Number of black lines.
Minimum is 1.
Range 1−255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1−31: blank 1−31 lines
6
7
198
199
reserved
0x0000
0x000
0
0
1
Reserved
Reserved
RW
RW
[11:0]
[15:0]
reserved
mult_timer0
0x0001
Exposure/Frame Rate
Configuration
mult_timer0
0x0001
1
Mult Timer
Defines granularity (unit
= 1/PLL clock) of
exposure and re-
set_length
8
200
fr_length0
fr_length0
0x0000
0x0000
0
0
Exposure/Frame Rate
Configuration
RW
[15:0]
Frame/Reset length
Reset length when
fr_mode = ’0’, Frame
Length when fr_mode =
’1’
Granularity defined by
mult_timer
9
201
exposure0
exposure0
0x0000
0x0000
0
0
Exposure/Frame Rate
Configuration
RW
[15:0]
Exposure Time
Granularity defined by
mult_timer
10
11
12
202
203
204
reserved
0x0000
0x0000
0x0000
0x0000
0x01E3
0
0
Reserved
RW
RW
RW
[15:0]
[15:0]
reserved
Reserved
reserved
0
Reserved
reserved
0
Reserved
gain_configuration0
483
Gain Configuration
www.onsemi.com
61
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
mux_gainsw0
reserved
Default
Description
Column Gain Setting
Reserved
Type
[4:0]
[12:5]
[13]
0x03
0xF
0x0
3
15
0
gain_lat_comp
Postpone gain update by
1 frame when ’1’ to
compensate for expo-
sure time updates laten-
cy.
Gain is applied at start of
next frame if ’0’
13
14
205
206
digital_gain_con-
figuration0
0x0080
128
Gain Configuration
RW
RW
[11:0]
db_gain0
0x080
128
895
Digital Gain
sync_configuration
0x037F
Synchronization
Configuration
[0]
[1]
[2]
[3]
[4]
sync_rs_x_length
sync_black_lines
sync_dummy_lines
sync_exposure
sync_gain
0x1
0x1
0x1
0x1
0x1
1
1
1
1
1
Update of rs_x_length
will not be sync’ed at
start of frame when ’0’
Update of black_lines
will not be sync’ed at
start of frame when ’0’
Update of dummy_lines
will not be sync’ed at
start of frame when ’0’
Update of exposure will
not be sync’ed at start of
frame when ’0’
Update of gain settings
(gain_sw, afe_gain) will
not be sync’ed at start of
frame when ’0’
[5]
[6]
sync_roi
0x1
0x1
1
1
Update of roi updates
(active_roi) will not be
sync’ed at start of frame
when ’0’
sync_ref_lines
Update of ref_lines will
not be sync’ed at start of
frame when ’0’
[8]
[9]
blank_roi_switch
0x1
0x1
1
1
Blank first frame after
ROI switching
blank_subsam-
pling_ss
Blank first frame after
subsampling/binning
mode switching
’0’: No blanking
’1’: Blanking
[10]
exposure_sync_mode
0x0
0
When ’0’, exposure con-
figurations are sync’ed at
the start of FOT. When
’1’, exposure configura-
tions sync is disabled
(continuously syncing).
This mode is only rele-
vant for Triggered −
master mode, where the
exposure configurations
are sync’ed at the start
of exposure rather than
the start of FOT. For all
other modes it should be
set to ’0’.
Note: Sync is still post-
poned if sync_expo-
sure=’0’.
15
16
207
208
ref_lines
ref_lines
0x0000
0x00
0
0
Reference Line Configu-
ration
RW
RW
[7:0]
Number of Reference
Lines
0−255
reserved
0x4F00
20224
Reserved
www.onsemi.com
62
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
[7:0]
0x00
0x4F
0x0E5B
0x1
0
[15:8]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
79
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
19
211
3675
RW
[0]
[1]
1
0x1
1
[2]
0x0
0
[3]
0x1
1
[6:4]
[15:8]
0x5
5
0xE
14
20
212
0x0000
0x0000
0x0
0
RW
[12:0]
[15]
0
0
21
22
213
214
0x13FF
0x13FF
0x0000
0x00
0x0
5119
RW
RW
[12:0]
5119
0
[7:0]
0
[15:8]
0
23
215
0x0103
0x1
259
RW
[0]
[1]
1
0x1
1
[2]
0x0
0
[3]
0x0
0
[4]
0x0
0
[5]
0x0
0
[6]
0x0
0
0
[7]
0x0
[8]
0x1
1
[9]
0x0
0
[10]
[11]
[12]
[13]
[14]
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
24
25
26
27
28
216
217
218
219
220
0x7F08
0x08
0x7F
0x4444
0x44
0x44
0x4444
0x44
0x44
0x0016
0x016
0x00
0x301F
0x1F
0x30
32520
8
RW
RW
RW
RW
RW
[6:0]
[14:8]
127
17476
68
68
17476
68
68
22
22
0
[6:0]
[14:8]
[6:0]
[14:8]
[6:0]
[14:8]
12319
31
48
[6:0]
[14:8]
www.onsemi.com
63
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
reserved
Default
Description
Reserved
Type
29
221
0x6245
0x45
0x62
0x6230
0x30
0x62
0x001A
0x1A
0x3E01
0x1
25157
RW
[6:0]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
roi_active0_1
roi_active1
69
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Active ROI Selection
[14:8]
98
30
222
25136
RW
[6:0]
48
[14:8]
98
31
32
223
224
26
RW
RW
[6:0]
26
15873
[3:0]
[7:4]
[8]
1
0x00
0x0
0
0
[9]
0x1
1
[10]
[11]
[12]
[13]
0x1
1
0x1
1
0x1
1
0x1
1
33
34
35
225
226
227
0x5EF1
0x11
0x17
0x17
0x0
24305
RW
RW
RW
[4:0]
[9:5]
17
23
[14:10]
[15]
23
0
0x6000
0x00
0x00
0x18
0x0
24576
[4:0]
[9:5]
0
0
[14:10]
[15]
24
0
0x0000
0x0
0
[0]
[1]
[2]
[3]
[4]
0
0x0
0
0x0
0
0x0
0
0x0
0
36
37
38
39
228
229
230
231
0x0001
0x01
1
RW
RW
RW
RW
[7:0]
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
roi_active1_1
roi_active1_1
0x0000
0x0000
0
0
Active ROI Selection
[15:0]
Active ROI Selection
[0] Roi16 Active
[1] Roi17 Active
...
[15] Roi31 Active
mult_timer1
mult_timer1
0x0001
0x0001
1
1
Exposure/Frame Rate
Configuration
[15:0]
Mult Timer
Defines granularity (unit
= 1/PLL clock) of expo-
sure and reset_length
fr_length1
0x0000
0
Exposure/Frame Rate
Configuration
www.onsemi.com
64
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
fr_length1
Default
Description
Type
[15:0]
0x0000
0
Frame/Reset length
Reset length when
fr_mode = ’0’, Frame
Length when fr_mode =
’1’
Granularity defined by
mult_timer
40
232
exposure1
exposure1
0x0000
0x0000
0
0
Exposure/Frame Rate
Configuration
RW
[15:0]
Exposure Time
Granularity defined by
mult_timer
41
42
43
233
234
235
reserved
0x0000
0x0000
0x0000
0x0000
0x01E3
0x03
0
0
Reserved
RW
RW
RW
[15:0]
[15:0]
reserved
Reserved
reserved
0
Reserved
reserved
0
Reserved
gain_configuration1
mux_gainsw1
afe_gain1
483
3
Gain Configuration
Column Gain Setting
[4:0]
[12:5]
0xF
15
AFE Programmable
Gain Setting
44
236
digital_gain_con-
figuration1
0x0080
128
Gain Configuration
RW
[11:0]
[15:0]
[15:0]
[15:0]
db_gain1
reserved
reserved
reserved
reserved
reserved
reserved
x_resolution
0x080
0x0000
0x0000
0xFFFF
0xFFFF
0x0000
0x0
128
Digital Gain
Reserved
45
46
47
48
237
238
239
240
0
RW
RW
0
65535
65535
0
Reserved
Reserved
Reserved
Reserved
RW
0
Reserved
0x0050
[0x0042,
0x0042,
0x003E]
80
[66, 66,
62]
Sequencer Status
Status
[7:0]
[12:0]
[15:0]
x_resolution
0x0050
[0x0042,
0x0042,
0x003E]
80
[66, 66,
62]
Sensor x Resolution
49
50
241
242
y_resolution
y_resolution
0x1400
5120
Sequencer Status
Sequencer Status
Status
Status
0x1400
[0x1010,
0x0C10,
0x0B60]
5120
[4112,
3088,
2912]
mult_timer_status
mult_timer
0x0000
0x0000
0
0
Sequencer Status
Mult Timer Status
(Master Global Shutter
only)
51
52
53
54
55
243
244
245
246
247
reset_length_status
reset_length
0x0000
0x0000
0
0
Sequencer Status
Status
Status
Status
Status
Status
[15:0]
[15:0]
[15:0]
[15:0]
Current Reset Length
(not in Slave mode)
exposure_status
exposure
0x0000
0x0000
0
0
Sequencer Status
Current Exposure Time
(not in Slave mode)
exposure_ds_status
exposure_ds
0x0000
0x0000
0
0
Sequencer Status
Current Exposure Time
(not in Slave mode)
exposure_ts_status
exposure_ts
0x0000
0x0000
0
0
Sequencer Status
Current Exposure Time
(not in Slave mode)
gain_status
0x0000
0
Sequencer Status
www.onsemi.com
65
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
mux_gainsw
Default
Description
Type
[4:0]
0x00
0
Current Column Gain
Setting
[12:5]
afe_gain
0x00
0
Current AFE Program-
mable Gain
56
58
248
250
digital_gain_status
db_gain
0x0000
0x000
0x0
0
Sequencer Status
Digital Gain
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Status
RW
[11:0]
[12]
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0
[13]
0x0
0
0x0423
0x03
1059
[4:0]
[9:5]
3
1
0x01
[14:10]
0x01
1
59
60
61
251
252
253
0x030F
0xF
783
15
3
RW
RW
RW
[7:0]
[15:8]
0x3
0x0601
0x1
1537
1
[7:0]
[15:8]
0x6
6
0x0000
0x00
0
[7:0]
0
[15:8]
0x00
0
62
63
254
255
0x0000
0x0000
0x0000
0x0000
0
RW
RW
[12:0]
[12:0]
0
0
0
Sequencer
ROI
256
0
256
roi0_configuration0
x_start
0x4F00
0x00
20224
0
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
RW
[7:0]
[15:8]
x_end
0x4F
79
1
2
3
257
258
259
roi0_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi0_configuration2
y_end
5119
5119
20224
0
roi1_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
4
5
6
260
261
262
roi1_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi1_configuration2
y_end
5119
5119
20224
0
roi2_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
7
8
9
263
264
265
roi2_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0
RW
RW
RW
[12:0]
[12:0]
0
roi2_configuration2
y_end
5119
5119
20224
roi3_configuration0
www.onsemi.com
66
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
x_start
Default
0
Description
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
Type
[7:0]
0x00
0x4F
[15:8]
x_end
79
10
11
12
266
267
268
roi3_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi3_configuration2
y_end
5119
5119
20224
0
roi4_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
13
14
15
269
270
271
roi4_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi4_configuration2
y_end
5119
5119
20224
0
roi5_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
16
17
18
272
273
274
roi5_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi5_configuration2
y_end
5119
5119
20224
0
roi6_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
19
20
21
275
276
277
roi6_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi6_configuration2
y_end
5119
5119
20224
0
roi7_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
22
23
24
278
279
280
roi7_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi7_configuration2
y_end
5119
5119
20224
0
roi8_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
25
26
27
281
282
283
roi8_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi8_configuration2
y_end
5119
5119
20224
0
roi9_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
28
29
284
285
roi9_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0
RW
RW
[12:0]
[12:0]
0
roi9_configuration2
y_end
5119
5119
www.onsemi.com
67
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
roi10_configuration0
x_start
Default
20224
0
Description
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Type
30
286
0x4F00
0x00
RW
[7:0]
[15:8]
x_end
0x4F
79
31
32
33
287
288
289
roi10_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi10_configuration2
y_end
5119
5119
20224
0
roi11_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
34
35
36
290
291
292
roi11_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi11_configuration2
y_end
5119
5119
20224
0
roi12_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
37
38
39
293
294
295
roi12_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi12_configuration2
y_end
5119
5119
20224
0
roi13_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
40
41
42
296
297
298
roi13_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi13_configuration2
y_end
5119
5119
20224
0
roi14_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
43
44
45
299
300
301
roi14_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi14_configuration2
y_end
5119
5119
20224
0
roi15_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
46
47
48
302
303
304
roi15_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi15_configuration2
y_end
5119
5119
20224
0
roi16_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
49
50
305
306
roi16_configuration1
y_start
0x0000
0x0000
0x13FF
0
RW
RW
[12:0]
0
roi16_configuration2
5119
www.onsemi.com
68
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
y_end
Default
5119
20224
0
Description
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
Type
[12:0]
0x13FF
0x4F00
0x00
51
307
roi17_configuration0
x_start
RW
[7:0]
[15:8]
x_end
0x4F
79
52
53
54
308
309
310
roi17_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi17_configuration2
y_end
5119
5119
20224
0
roi18_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
55
56
57
311
312
313
roi18_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi18_configuration2
y_end
5119
5119
20224
0
roi19_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
58
59
60
314
315
316
roi19_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi19_configuration2
y_end
5119
5119
20224
0
roi20_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
61
62
63
317
318
319
roi20_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi20_configuration2
y_end
5119
5119
20224
0
roi21_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
64
65
66
320
321
322
roi21_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi21_configuration2
y_end
5119
5119
20224
0
roi22_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
67
68
69
323
324
325
roi22_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi22_configuration2
y_end
5119
5119
20224
0
roi23_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
70
326
roi23_configuration1
y_start
0x0000
0x0000
0
RW
[12:0]
0
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69
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
Register Name
roi23_configuration2
y_end
Default
5119
5119
20224
0
Description
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Type
71
327
0x13FF
0x13FF
0x4F00
0x00
RW
[12:0]
72
328
roi24_configuration0
x_start
RW
[7:0]
[15:8]
x_end
0x4F
79
73
74
75
329
330
331
roi24_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi24_configuration2
y_end
5119
5119
20224
0
roi25_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
76
77
78
332
333
334
roi25_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi25_configuration2
y_end
5119
5119
20224
0
roi26_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
79
80
81
335
336
337
roi26_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi26_configuration2
y_end
5119
5119
20224
0
roi27_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
82
83
84
338
339
340
roi27_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi27_configuration2
y_end
5119
5119
20224
0
roi28_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
85
86
87
341
342
343
roi28_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi28_configuration2
y_end
5119
5119
20224
0
roi29_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
88
89
90
344
345
346
roi29_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0x4F00
0x00
0
RW
RW
RW
[12:0]
[12:0]
0
roi29_configuration2
y_end
5119
5119
20224
0
roi30_configuration0
x_start
[7:0]
[15:8]
x_end
0x4F
79
91
347
roi30_configuration1
0x0000
0
RW
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70
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Block
Offset
Address
Offset
Bit
Field
Default
(Hex)
Category
Address
348
Register Name
y_start
Default
0
Description
Y Start Configuration
ROI Configuration
Y End Configuration
ROI Configuration
X Start Configuration
X End Configuration
ROI Configuration
Y Start Configuration
ROI Configuration
Y End Configuration
Type
RW
[12:0]
[12:0]
0x0000
0x13FF
0x13FF
0x4F00
0x00
92
93
roi30_configuration2
y_end
5119
5119
20224
0
349
roi31_configuration0
x_start
RW
[7:0]
[15:8]
x_end
0x4F
79
94
95
350
351
roi31_configuration1
y_start
0x0000
0x0000
0x13FF
0x13FF
0
RW
RW
[12:0]
[12:0]
0
roi31_configuration2
y_end
5119
5119
384
0
384
…
reserved
reserved
…
Reserved
Reserved
…
RW
[15:0]
…
…
…
127
511
Reserved
Reserved
[15:0]
reserved
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71
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
PACKAGE INFORMATION
Pin Description
Refer to Electrical Specifications on page 4 for power supplies and references. The CMOS IO follow the JEDEC Standard
(JEDEC−JESD8C−01).
Table 31. PIN DESCRIPTION
Pin No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
Name
vddd_18
Type
Supply
Analog
CMOS
Ground
Ground
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Analog
CMOS
Ground
LVDS
Direction
Description
Digital supply - 1.8 V domain
mbs2_out
adc_dout1
gnd_colbias
gnd_colbias
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vdda_33
vddd_18
vddd_18
vddd_33
ibias_master
adc_dout2
gnd_colbias
doutn30
Out
Out
For test purposes only. Do not connect
For test purposes only. Do not connect
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Analog supply - 3.3 V domain
Digital supply - 1.8 V domain
Digital supply - 1.8 V domain
Digital supply - 3.3 V domain
In/Out
Out
Bias reference - Connect with 47 kW to ibias_out
For test purposes only. Do not connect
Column biasing ground - Connect to ground
LVDS data out negative - Channel 30
LVDS data out positive - Channel 28
LVDS data out negative - Channel 27
LVDS data out negative - Channel 25
LVDS data out negative - Channel 23
LVDS data out negative - Channel 21
LVDS data out negative - Channel 19
LVDS data out positive - Channel 17
LVDS data out negative - Channel 16
Out
Out
Out
Out
Out
Out
Out
Out
Out
doutp28
LVDS
doutn27
LVDS
doutn25
LVDS
doutn23
LVDS
doutn21
LVDS
doutn19
LVDS
doutp17
LVDS
doutn16
LVDS
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C01
C02
Name
doutn14
Type
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Ground
LVDS
LVDS
Supply
Supply
Analog
Direction
Out
Description
LVDS data out negative - Channel 14
LVDS data out positive - Channel 12
LVDS data out positive - Channel 10
LVDS data out positive - Channel 8
LVDS data out positive - Channel 6
LVDS data out positive - Channel 4
LVDS data out negative - Channel 3
LVDS data out positive - Channel 1
Column biasing ground - Connect to ground
LVDS clock in positive
doutp12
doutp10
doutp8
Out
Out
Out
doutp6
Out
doutp4
Out
doutn3
Out
doutp1
Out
gnd_colbias
clock_inp
clock_inn
vddd_33
vddd_33
ibias_out
In
In
LVDS clock in negative
Digital supply - 3.3 V domain
Digital supply - 3.3 V domain
In/Out
Out
Bias ground reference - Connect with 47 kW to
ibias_master
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D01
D02
D03
D04
adc_dout9
gnd_colbias
doutp30
CMOS
Ground
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Ground
Ground
Ground
Supply
Analog
CMOS
CMOS
Ground
For test purposes only. Do not connect
Column biasing ground - Connect to ground
LVDS data out positive - Channel 30
LVDS data out negative - Channel 28
LVDS data out positive - Channel 27
LVDS data out positive - Channel 25
LVDS data out positive - Channel 23
LVDS data out positive - Channel 21
LVDS data out positive - Channel 19
LVDS data out negative - Channel 17
LVDS data out positive - Channel 16
LVDS data out positive - Channel 14
LVDS data out negative - Channel 12
LVDS data out negative - Channel 10
LVDS data out negative - Channel 8
LVDS data out negative - Channel 6
LVDS data out negative - Channel 4
LVDS data out positive - Channel 3
LVDS data out negative - Channel 1
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Digital supply - 3.3 V domain
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
doutn28
doutp27
doutp25
doutp23
doutp21
doutp19
doutn17
doutp16
doutp14
doutn12
doutn10
doutn8
doutn6
doutn4
doutp3
doutn1
gnd_colbias
gnd_colbias
gnd_colbias
vddd_33
mbs1_out
adc_dout5
adc_dout10
gnd_colbias
Out
Out
Out
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
Column biasing ground - Connect to ground
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
Name
clock_outp
Type
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Ground
CMOS
CMOS
CMOS
CMOS
CMOS
Analog
Ground
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Direction
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Description
LVDS clock out positive
doutn31
doutn29
doutn26
doutn24
doutn22
doutn20
doutn18
doutp15
doutp13
doutp11
doutp9
LVDS data out negative - Channel 31
LVDS data out negative - Channel 29
LVDS data out negative - Channel 26
LVDS data out negative - Channel 24
LVDS data out negative - Channel 22
LVDS data out negative - Channel 20
LVDS data out negative - Channel 18
LVDS data out positive - Channel 15
LVDS data out positive - Channel 13
LVDS data out positive - Channel 11
LVDS data out positive - Channel 9
LVDS data out positive - Channel 7
LVDS data out positive - Channel 5
LVDS data out positive - Channel 2
LVDS data out positive - Channel 0
LVDS sync positive
doutp7
doutp5
doutp2
doutp0
syncp
gnd_colbias
miso
Column biasing ground - Connect to ground
SPI master in -slave out
Out
In
mosi
SPI master out - slave in
ss_n
In
SPI slave select (active low)
adc_dout0
adc_dout4
srd2_n
Out
Out
For test purposes only. Do not connect
For test purposes only. Do not connect
Not connected
gnd_colbias
clock_outn
doutp31
doutp29
doutp26
doutp24
doutp22
doutp20
doutp18
doutn15
doutn13
doutn11
doutn9
Column biasing ground - Connect to ground
LVDS clock out negative
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
LVDS data out positive - Channel 31
LVDS data out positive - Channel 29
LVDS data out positive - Channel 26
LVDS data out positive - Channel 24
LVDS data out positive - Channel 22
LVDS data out positive - Channel 20
LVDS data out positive - Channel 18
LVDS data out negative - Channel 15
LVDS data out negative - Channel 13
LVDS data out negative - Channel 11
LVDS data out negative - Channel 9
LVDS data out negative - Channel 7
LVDS data out negative - Channel 5
LVDS data out negative - Channel 2
LVDS data out negative - Channel 0
LVDS sync negative
doutn7
doutn5
doutn2
doutn0
syncn
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
E22
E23
E24
E25
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
Name
gnd_colbias
trigger
Type
Direction
Description
Column biasing ground - Connect to ground
Trigger
Ground
CMOS
CMOS
CMOS
CMOS
CMOS
Analog
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
CMOS
CMOS
In
In
sck
SPI clock
reset_n
In
Active low system reset
adc_dout3
adc_dout6
srd2_nguard
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
scan_in2
Out
Out
For test purposes only. Do not connect
For test purposes only. Do not connect
Not connected
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Scan chain input #2 - Connect to ground
Selects number of output channels
Selects number of output channels
For test purposes only. Do not connect
For test purposes only. Do not connect
For test purposes only. Do not connect
Not connected
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
In
In
muxmode1
muxmode0
adc_dout8
adc_dout7
afe_clk
In
Out
Out
Out
srd1_nguard
srd1_n
Not connected
td_anode
In/Out
In/Out
In
Temperature diode - Anode
td_cathode
mbs3_in
Temperature diode - Cathode
Analog test input - Connect to ground
Analog test input - Connect to ground
For test purposes only. Do not connect
For test purposes only. Do not connect
Digital test input - Connect to ground
Digital test input - Connect to ground
mbs4_in
In
spare_ana
spare_ana
spare_dig_in
spare_dig_in
Out
Out
In
In
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
H21
H22
H23
H24
H25
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
Name
spare_dig_in
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
gnd_colbias
scan_clk
Type
Direction
Description
Digital test input - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Column biasing ground - Connect to ground
Scan chain clock - Connect to ground
Monitor output #2
CMOS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Analog
Analog
Analog
Analog
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply
Ground
Ground
In
In
Out
Out
Out
In
monitor2
monitor1
Monitor output #1
monitor0
Monitor output #0
test_enable
adc_mode
spare_dig_out
spare_dig_out
spare_dig_out
spare_vref6t_hv
spare_vref6t_hv
spare_vref6t_hv
spare_vref6t_hv
gndd_33
Test enable - Connect to ground
Connect to Gndd_33 (‘0’)
In
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 3.3 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Digital ground - 1.8 V domain
Pixel calibration ground - Connect to ground
Pixel transfer ground - sinking supply
Floating diffusion reset ground - Connect to ground
Floating diffusion reset ground - Connect to ground
gndd_33
gndd_33
gndd_33
gndd_33
gndd_33
gndd_33
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
gndd_33
gndd_18
gndd_18
gndd_18
gndd_18
gndd_18
gndd_18
gndd_18
gndd_18
gndd_18
gnd_calib
gnd_trans
gnd_resfd
gnd_resfd
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76
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
K01
K02
K03
K04
K05
K06
K07
K08
K9
Name
spare_vref6t
spare_vref6t
spare_vref6t
spare_vref6t
spare_vref6t
spare_vref6t
spare_vref6t
spare_vref6t
vdd_pix
Type
Direction
Description
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Ground
Supply
Ground
Supply
Ground
Ground
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Pixel array supply
Pixel array supply
Pixel array supply
Pixel array supply
Pixel array supply
Pixel array supply
Pixel array supply
Pixel array supply
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
vdd_pix
vdd_pix
vdd_pix
vdd_pix
vdd_pix
vdd_pix
vdd_pix
gnd_sel
Pixel select ground - Connect to ground
Pixel select ground - Connect to ground
Pixel select ground - Connect to ground
Pixel select ground - Connect to ground
Pixel calibration supply
gnd_sel
gnd_sel
gnd_sel
vdd_calib
gnd_calib
gnd_trans
gnd_resfd
gnd_resfd
vref_colmux
vdd_pix
Pixel calibration ground - Connect to ground
Pixel transfer ground - sinking supply
Floating diffusion reset ground - Connect to ground
Floating diffusion reset ground - Connect to ground
Column multiplexer reference supply
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
L12
L13
L14
L15
L16
L17
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_casc
Cascode supply
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
L18
Name
vdd_casc
Type
Direction
Description
Supply
Supply
Supply
Supply
Ground
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Ground
Supply
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Cascode supply
L19
vdd_sel
Pixel select supply
Pixel select supply
L20
vdd_sel
L21
vdd_calib
gnd_calib
gnd_trans
vdd_resfd
vref_colmux
vref_colmux
vdd_pix
Pixel calibration supply
L22
Pixel calibration ground - Connect to ground
Pixel transfer ground - sinking supply
Floating diffusion reset supply
Column multiplexer reference supply
Column multiplexer reference supply
Pixel array supply
L23
L24
L25
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
N01
N02
N03
N04
N05
N06
N07
N08
N09
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_pix
Pixel array supply
vdd_casc
vdd_casc
vdd_sel
Cascode supply
Cascode supply
Pixel select supply
vdd_sel
Pixel select supply
vdd_calib
gnd_calib
gnd_trans
vdd_resfd
vref_colmux
vddd_33
vdd_pix
Pixel calibration supply
Pixel calibration ground - Connect to ground
Pixel transfer ground - sinking supply
Floating diffusion reset supply
Column multiplexer reference supply
Digital supply - 3.3-V domain
Pixel array supply
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
R01
Name
gnd_colpc
Type
Direction
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply
Supply
Supply
Supply
Supply
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Pixel calibration supply
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
vdd_calib
vdd_trans
vdd_trans
vdd_resfd
vddd_33
Pixel transfer supply
Pixel transfer supply
Floating diffusion reset supply
Digital supply - 3.3 V domain
vddd_33
Digital supply - 3.3 V domain
vdd_pix
Pixel array supply
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
gnd_colpc
vdd_trans
vdd_trans
vdd_resfd
vddd_33
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Column precharge ground - Connect to ground
Pixel transfer supply
Pixel transfer supply
Floating diffusion reset supply
Digital supply - 3.3 V domain
vddd_18
Digital supply - 1.8 V domain
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 31. PIN DESCRIPTION
Pin No.
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
Name
vddd_18
Type
Direction
Description
Digital supply - 1.8 V domain
Supply
Supply
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Supply
Supply
Supply
vddd_18
gnd_colpc
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
gnda_33
vddd_18
vddd_18
vddd_18
Digital supply - 1.8 V domain
Column precharge ground - Connect to ground
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Analog ground - 3.3 V domain
Digital supply - 1.8 V domain
Digital supply - 1.8 V domain
Digital supply - 1.8 V domain
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Mechanical Specifications
Table 32. MECHANICAL SPECIFICATIONS
Parameter
Description
Min
Typ
Max
Units
Die
Die thickness
725
mm
2
Die size
25.5 x 32.5
mm
Die center, X offset to the center of package
Die center, Y offset to the center of the package
Die position, tilt to the Die Attach Plane
-50
-50
−1
0
0
0
0
50
50
1
mm
mm
deg
deg
Die rotation accuracy (referenced to die scribe and lead
fingers on package on all four sides)
−1
1
Optical center referenced from the die/package center (X-dir)
Optical center referenced from the die/package center (Y-dir)
Distance from bottom of the package to top of the die surface
Distance from top of the die surface to top of the glass lid
XY size
0
3602
mm
mm
1.605
1.075
1.80
1.995
1.855
mm
mm
1.45
2
Glass Lid
32.47 x 39.4
0.7
mm
Specification
Thickness
mm
nm
%
Spectral response range
400
1000
Transmission of glass lid (refer to Figure 44)
D263 Teco (no coatings on glass)
92
Glass Lid Material
Mechanical Shock
Vibration
JESD22-B104C; Condition G
2000
2000
g
JESD22-B103B; Condition 1
Hz
Mounting Profile
Pb−free wave soldering profile for pin grid array package
Andon Electronics Corporation (www.andonelectronics.com)
Recommended
Socket
10−31−13A−355−400T4−R27−L14
NOTE: Optical center min/max tolerance is calculated on X/Y package tolerances with package center as a reference.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Package Drawing
All dimensions are in mm,
unless specified otherwise.
Figure 49. PYTHON XK Package Diagram
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Optical Center Information
♦ A1 is the at (1214, 31388) mm
♦ A2 is at (24286, 31388) mm
♦ A3 is at (24286, 8316) mm
♦ A4 is at (1214, 8316) mm
• Center of the Active Area
♦ AA is at (12750, 19852) mm
• Center of the Die
The center of the die (CD) is the center of the cavity
The center of the die (CD) is exactly at 50% between the
outsides of the two outer seal rings
The center of the cavity is exactly at 50% between the
insides of the finger pads.
• Die outer dimensions:
♦ B4 is the reference for the Die (0,0) in mm
♦ B1 is at (0,32500) mm
♦ CD is at (12750, 16250) mm
♦ B2 is at (25500,32500) mm
♦ B3 is at (25500,0) mm
NOTE: The data represented here is for the 25K variant.
For the other variants only A1−A4 are different.
Centers remain the same.
• Active Area outer dimensions
Figure 50. Graphical Representation of the Optical Center
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Glass Lid
As seen in Figure 51, the sensor does not have an infrared
The PYTHON XK image sensor uses a glass lid without
any coatings. Figure 51 shows the transmission
characteristics of the glass lid.
attenuating filter glass. A filter must be provided in the
optical path when color devices are used (source:
http://www.pgo-online.com).
Figure 51. Transmission Characteristics of Glass Lid
SPECIFICATIONS AND USEFUL REFERENCES
Application Note and References
Specifications, Application Notes and useful resources
can be accessible via customer login account at MyOn -
ISG Extranet.
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
• PYTHON XK Layout DSN drawing
• PYTHON XK 3D package STP file for CAD
Acceptance Criteria Specification
The Product Acceptance Criteria is available on request.
This document contains the criteria to which the PYTHON
XK is tested prior to being shipped.
Useful References
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
Return Material Authorization (RMA)
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
ACRONYMS
Acronym
ADC
AFE
BL
Description
Analog-to-Digital Converter
Analog Front End
Acronym
LE
Description
Line End
Line Start
LS
Black pixel data
LSB
LVDS
MSB
PGA
PLS
PRBS
PRNU
QE
least significant bit
CDM
CDS
CMOS
CRC
DAC
DDR
DNL
DS
Charged Device Model
Correlated Double Sampling
Complementary Metal Oxide Semiconductor
Cyclic Redundancy Check
Digital-to-Analog Converter
Double Data Rate
Low-Voltage Differential Signaling
most significant bit
Programmable Gain Amplifier
Parasitic Light Sensitivity
Pseudo-Random Binary Sequence
Photo Response Non-Uniformity
Quantum Efficiency
Differential Non-Llinearity
Double Sampling
RGB
RMA
RMS
ROI
Red-Green-Blue
EIA
Electronic Industries Alliance
Electrostatic Discharge
Frame End
Return Material Authorization
Root Mean Square
ESD
FE
Region of Interest
FOT
FPGA
FPN
FPS
FS
Frame Overhead Time
Field Programmable Gate Array
Fixed Pattern Noise
ROT
S/H
Row Overhead Time
Sample and Hold
SNR
SPI
Signal-to-Noise Ratio
Frame per Second
Serial Peripheral Interface
Telecommunications Industry Association
Junction temperature
Frame Start
TIA
HBM
IMG
INL
Human Body Model
T
J
Image data (regular pixel data)
Integral Non-Linearity
Intellectual Property
TR
Training pattern
% RH
Percent Relative Humidity
IP
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
GLOSSARY
conversion gain
CDS
A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel.
Conversion gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance
of the photodiode or sense node.
Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is
sampled and subtracted from the voltage after exposure to light.
CFA
Color filter array. The materials deposited on top of pixels that selectively transmit color.
Differential non-linearity (for ADCs)
DNL
DSNU
Dark signal non-uniformity. This parameter characterizes the degree of non-uniformity in dark leakage
currents, which can be a major source of fixed pattern noise.
fill-factor
A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the
actual QE of a pixel divided by the QE of a photodiode of equal area. In practice, it is never measured.
INL
Integral nonlinearity (for ADCs)
IR
Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm.
2
2
Lux
Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m = 1/683 W/m )
pixel noise
Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the
pixel array and may be limited to a single color plane.
photometric units
PLS
Units for light measurement that take into account human physiology.
Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes.
PRNU
Photo-response non-uniformity. This parameter characterizes the spread in response of pixels, which is a
source of FPN under illumination.
QE
Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and
converting them into electrons. It is photon wavelength and pixel color dependent.
read noise
reset
Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode
into an output signal.
The process by which a pixel photodiode or sense node is cleared of electrons. ”Soft” reset occurs when
the reset transistor is operated below the threshold. ”Hard” reset occurs when the reset transistor is oper-
ated above threshold.
reset noise
responsivity
Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units
of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel
designs, reset noise can be removed with CDS.
The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units
are typically A/W and are dependent on the incident light wavelength. Note that responsivity and sensitivity
are used interchangeably in image sensor characterization literature so it is best to check the units.
ROI
Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on.
The ROI can be the entire array or a small subsection; it can be confined to a single color plane.
sense node
sensitivity
In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodi-
ode itself.
A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts
2
upon illumination with light. Units are typically V/(W/m )/sec and are dependent on the incident light wave-
length. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683 lux
2
is equal to 1 W/m ; the units of sensitivity are quoted in V/lux/sec. Note that responsivity and sensitivity are
used interchangeably in image sensor characterization literature so it is best to check the units.
spectral response
SNR
The photon wavelength dependence of sensitivity or responsivity.
Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum
up to half the Nyquist frequency.
temporal noise
Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels.
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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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