NLVVHC1GT125DF2G [ONSEMI]
Noninverting Buffer / CMOS Logic Level Shifter; 非反相缓冲器/ CMOS逻辑电平转换器
| 型号： | NLVVHC1GT125DF2G |
| 厂家： | 
ONSEMI |
| 描述： | Noninverting Buffer / CMOS Logic Level Shifter |
| 文件： | 总6页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1GT125
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT125 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
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MARKING
The MC74VHC1GT125 requires the 3−state control input (OE) to
be set High to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT125 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
DIAGRAMS
5
5
1
W1 M G
SC−88A / SOT−353 / SC−70
DF SUFFIX
G
1
5
CASE 419A
5
W1 M G
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
G
1
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
CASE 483
Features
W1
M
G
= Device Code
= Date Code*
= Pb−Free Package
• High Speed: t = 3.5 ns (Typ) at V = 5 V
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
PD
CC
CC
A
(Note: Microdot may be in either location)
IL
IH
*Date Code orientation and/or position may vary
depending upon manufacturing location.
OH
CC OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PIN ASSIGNMENT
1
2
3
4
5
OE
IN A
GND
OUT Y
V
CC
OE
IN A
GND
V
CC
5
4
1
2
FUNCTION TABLE
OE Input
A Input
Y Output
OUT Y
L
H
X
L
L
L
H
Z
3
H
Figure 1. Pinout (Top View)
OE
IN A
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
September, 2012 − Rev. 14
MC74VHC1GT125/D
MC74VHC1GT125
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power Dissipation in Still Air
Thermal Resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
JA
T
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage Temperature
260
L
T
+150
−65 to +150
°C
J
T
stg
°C
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
3.0
0.0
0.0
−55
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
V
CC
V
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
20
°C
ns/V
t , t
V
CC
= 5.0 V 0.5 V
r
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature 5C
Time, Hours
Time, Years
117.8
47.9
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
90
100
110
120
130
140
20.4
1
9.4
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
MC74VHC1GT125
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
(V)
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
Maximum Low−Level
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
IL
Input Voltage
V
OH
Minimum High−Level
V
OH
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
IN
IH
IL
Output Voltage
I
= − 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
IL
I
I
= − 4 mA
= − 8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
V
V
OL
= V or V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
IN
IH
IL
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
IL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.10
1.0
1.0
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
1.0
20
40
CC
CC
I
Quiescent Supply
Current
Input: V = 3.4 V
5.5
1.35
1.50
1.65
mA
CCT
IN
Other Input: V or
CC
GND
I
Output Leakage
Current
V
= 5.5 V
0.0
5.5
0.0
0.5
5.0
2.5
5.0
10
2.5
10
mA
mA
mA
OPD
OUT
I
Maximum 3−State
Leakage Current
V
V
= V or V
IL
0.25
0.5
OZ
IN
OUT
IH
= V or GND
CC
I
Output Leakage
Current
V
OUT
= 5.5 V
OPD
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation
Delay, A to Y
ns
V
V
V
= 3.3 0.3 V C = 15pF
5.6
8.1
8.0
1.0
1.0
9.5
12.0
16.0
PLH
CC
CC
CC
L
t
C = 50pF
11.5
13.0
PHL
L
(Figures 3 and 5.)
= 5.0 0.5 V C = 15pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
L
C = 50pF
L
,
Maximum Output
Enable TIme,OE to Y
(Figures 4 and 5)
ns
ns
= 3.3 0.3 V C = 15pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
PZL
t
L
L
R = R = 500 W
C = 50pF
PZH
L
I
V
CC
= 5.0 0.5 V C = 15pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
L
R = R = 500 W
C = 50pF
L
L
I
,
Maximum Output
Disable Time,OE to Y
(Figures 4 and 5)
V
CC
= 3.3 0.3 V C = 15pF
6.5
8.0
9.7
13.2
1.0
1.0
11.5
15.0
14.5
18.0
PLZ
t
L
R = R = 500 W
C = 50pF
L
PHZ
L
I
V
CC
= 5.0 0.5 V C = 15pF
4.8
7.0
6.8
8.8
1.0
1.0
8.0
10.0
10.0
12.0
L
R = R = 500 W
C = 50pF
L
L
I
C
Maximum Input Capacitance
4
6
10
10
10
pF
pF
in
C
Maximum Three−State
Output Capacitance
(Output in High Impedance
State)
out
Typical @ 25°C, V = 5.0 V
CC
14
C
Power Dissipation Capacitance (Note 5)
pF
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /4 (per buffer). C is used to determine the
CC
CC(OPR
CC
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
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3
MC74VHC1GT125
SWITCHING WAVEFORMS
V
CC
OE
50%
V
CC
GND
50%
t
t
PZL
PLZ
A
Y
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
50% V
Y
Y
CC
V
V
+ 0.3V
OL
50% V
CC
t
t
PZH
PHZ
- 0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 4. Switching Waveforms
Figure 5.
TEST POINT
1 kW
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
Package
ORDERING INFORMATION
†
Device
M74VHC1GT125DF1G
M74VHC1GT125DF2G
M74VHC1GT125DT1G
Shipping
SC−88A / SOT−353 / SC−70
(Pb−Free)
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
3000/Tape & Reel
NLVVHC1GT125DF1G*
NLVVHC1GT125DF2G*
NLVVHC1GT125DT1G*
SC−88A / SOT−353 / SC−70
(Pb−Free)
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHC1GT125
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
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5
MC74VHC1GT125
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
SOLDERING FOOTPRINT*
2.50
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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MC74VHC1GT125/D
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