NLVVHC1GT50DFT1G [ONSEMI]
Noninverting Buffer / CMOS Logic Level Shifter;
| 型号： | NLVVHC1GT50DFT1G |
| 厂家： | 
ONSEMI |
| 描述： | Noninverting Buffer / CMOS Logic Level Shifter |
| 文件： | 总6页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
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MARKING
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to
low voltage circuits. The output structures also provide protection
DIAGRAMS
5
5
VL M G
1
G
SC−88A / SOT−353 / SC−70
DF SUFFIX
1
5
CASE 419A
5
VL M G
when V = 0 V. These input and output structures help prevent
CC
G
device destruction caused by supply voltage − input/output voltage
mismatch, battery backup, hot insertion, etc.
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
1
Features
CASE 483
• Designed for 1.65 V to 5.5 V Operation
CC
• High Speed: t = 3.5 ns (Typ) at V = 5 V
PD
CC
VL = Device Code
M
G
= Date Code*
= Pb−Free Package
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V, V = 5 V
IL
IH
CC
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 104; Equivalent Gates = 26
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PIN ASSIGNMENT
1
2
3
4
5
NC
IN A
GND
OUT Y
• These Devices are Pb−Free and are RoHS Compliant
V
CC
NC
5
V
CC
1
2
3
FUNCTION TABLE
IN A
A Input
Y Output
L
L
GND
4
OUT Y
H
H
Figure 1. Pinout (Top View)
1
IN A
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
February, 2013 − Rev. 15
MC74VHC1GT50/D
MC74VHC1GT50
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power dissipation in still air
Thermal resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
JA
T
Lead temperature, 1 mm from case for 10 secs
Junction temperature under bias
Storage temperature
260
L
T
+150
−65 to +150
°C
J
T
stg
°C
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
1.65
0.0
Max
5.5
5.5
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
V
V
OUT
V
= 0
CC
0.0
0.0
V
High or Low State
V
CC
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1GT50
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
T
A
= 25°C
T
≤ 85°C
−55 ≤ T ≤ 125°C
A
CC
A
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
Minimum
High−Level
Input Voltage
1.65 to 2.29 0.50 V
0.50 V
0.50 V
CC
V
V
IH
CC
CC
2.3 to 2.99
0.45 V
0.45 V
0.45 V
CC
CC
CC
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
Maximum
Low−Level
Input Voltage
1.65 to 2.29
2.3 to 2.99
0.10 V
0.15 V
0.10 V
0.15 V
0.10 V
CC
V
V
V
CC
CC
IL
0.15 V
CC
CC
CC
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
Minimum
High−Level
Output
V
OH
V
I
= V
1.65 to 2.99
V
CC
− 0.1
V
CC
− 0.1
V
CC
− 0.1
IN
IH
= −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
OH
Voltage
V
I
I
= V
= −4 mA
= −8 mA
V
V
IN
OH
OH
IH
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
Maximum
Low−Level
Output
V
OL
V
I
= V
IL
1.65 to 2.99
0.0
0.0
0.1
0.1
0.1
IN
= 50 mA
3.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
OL
Voltage
V
I
I
= V
= 4 mA
= 8 mA
V
IN
OL
OL
IL
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
Maximum
Input
Leakage
Current
V
IN
= 5.5 V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
I
IN
Maximum
Quiescent
Supply
V
IN
= V or GND
CC
5.5
1.0
20
40
mA
I
CC
Current
Quiescent
Supply
Input: V = 3.4 V
5.5
0.0
1.35
0.5
1.50
5.0
1.65
10
mA
I
I
IN
CCT
Current
Output
Leakage
Current
V
OUT
= 5.5 V
mA
OPD
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
T
A
= 25°C
T
≤ 85°C
Max
−55 ≤ T ≤ 125°C
A
A
Min
Typ
Max Min
Min
Max
Symbol
Parameter
Test Conditions
Unit
ns
t
,
Maximum
V
V
= 1.8 0.15 V
= 2.5 0.2 V
C = 15 pF
16.6
18.0
22.0
PLH
CC
L
t
Propagation
PHL
C = 15 pF
C = 50 pF
13.3
19.5
14.5
22.0
17.5
25.5
ns
CC
L
L
Delay, Input A to Y
V
V
= 3.3 0.3 V
= 5.0 0.5 V
C = 15 pF
L
4.5
6.3
10.0
13.5
11.0
15.0
13.0
17.5
ns
CC
L
C = 50 pF
C = 15 pF
3.5
4.3
6.7
7.7
7.5
8.5
8.5
9.5
CC
L
C = 50 pF
L
C
Maximum Input
Capacitance
5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
12
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1GT50
V
CC
A
Y
50%
GND
t
t
PHL
PLH
V
V
OH
50% V
CC
OL
Figure 4. Switching Waveforms
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
M74VHC1GT50DFT1G
NLVVHC1GT50DFT1G*
M74VHC1GT50DFT2G
NLVVHC1GT50DFT2G*
M74VHC1GT50DTT1G
SC−88A / SOT−353 / SC−70
(Pb−Free)
3000 / Tape & Reel
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHC1GT50
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
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5
MC74VHC1GT50
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT50/D
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