NCP1596AMNTWG [ONSEMI]
1.5 A, 1.5 MHz Current Mode PWM Buck Down Converter; 1.5 A ， 1.5 MHz的电流模式PWM降压降转换器
| 型号： | NCP1596AMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | 1.5 A, 1.5 MHz Current Mode PWM Buck Down Converter |
| 文件： | 总12页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1596A
1.5 A, 1.5 MHz Current
Mode PWM Buck Down
Converter
The NCP1596A is a current mode PWM buck converter with
integrated power switch. It can provide up to 1.5 A output current with
high conversion efficiency. High frequency PWM control scheme can
provide a low output ripple noise. Thus, it allows the usage of small
size passive components to reduce the board space. In a low load
condition, the controller will automatically change to PFM mode
which provides a higher efficiency at low load. Additionally, the
device includes soft−start, thermal shutdown with hysteresis,
cycle−by−cyclecurrent limit, and short circuit protection. This device
is available in a compact 3x3 DFN package.
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1
6 PIN DFN 3x3
MN SUFFIX
CASE 506AH
Features
• High Efficiency up to 90%, 1 A @ 3.3 V, 75% @ 1.2 V
• Fully Internal Compensation
MARKING DIAGRAM
1
1596A
ALYW
G
• Low Output Voltage Ripple, 20 mV Typical
•
1.5% Reference Voltage
• High PWM Switching Frequency, 1.5 MHz
• Automatic PWM / PFM Switchover at Light Load
• Built−in 1 ms Digital Soft Start
1596A = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Cycle−by−cycle Current Limit
• Thermal Shutdown with Hysteresis
• Internal UVLO Protection
• Ext. Adjustable Output Voltage
• Low Profile and Minimum External Components
• Designed for use with Ceramic Capacitor
• Compact 3x3 DFN Package
PIN CONNECTIONS
FB
GND
LX
EN
VCC
VCCP
• These are Pb−Free Devices
(Top View)
Typical Applications
• Hard Disk Drives
• USB Power Device
• Wireless and DSL Modems
ORDERING INFORMATION
†
Device
NCP1596AMNTWG
Package
Shipping
3000 /
Tape & Reel
DFN6
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
June, 2009 − Rev. 0
NCP1596A/D
NCP1596A
L1
V
IN
= 4.0 V to 5.5 V
V = 0.8 V to 0.9 x V
OUT IN
LX
VCCP
NCP1596A
R1
D1
VCC
C1
C2
EN
FB
GND
R2
Figure 1. Typical Operating Circuit
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply (Pins 4, 5)
V
IN
6.0
V
−0.3 (DC)
−1.0 (100 ns)
Input / Output Pins
Pins 1, 3, 6
V
IO
6.0
V
−0.3 (DC)
−1.0 (100 ns)
Thermal Characteristics
3x3 DFN Plastic Package
Maximum Power Dissipation @ T = 25°C
P
q
1450
68.5
mW
A
D
JA
Thermal Resistance Junction−to−Ambient 0 lfpm
Operating Junction Temperature Range (Note 4)
Operating Ambient Temperature Range
Storage Temperature Range
R
°C/W
T
−40 to +150
−40 to +85
−55 to +150
230
°C
°C
°C
°C
−
J
T
A
T
stg
Lead Temperature Soldering (10 sec)
Moisture Sensitivity Level (Note 3)
MSL
1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: ESD data available upon request.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115.
2. Latch−up Current Maximum Rating: 150 mA per JEDEC standard: JESD78.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
4. The maximum package power dissipation limit must not be exceeded.
T
J(max) * TA
PD
+
RqJA
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2
NCP1596A
ELECTRICAL CHARACTERISTICS
(V = 5.0 V, V
= 1.2 V, T = 25°C for typical value, −40°C ≤ T ≤ 85°C for min/max values unless otherwise noted)
IN
OUT
A
A
Characteristic
Symbol
Min
4.0
3.2
−
Typ
−
Max
5.5
3.8
−
Unit
V
Operating Voltage
V
IN
Under Voltage Lockout Threshold
Under Voltage Lockout hysteresis
PFET Leakage Current (Pins 5, 4)
V
3.5
180
V
UVLO
UVLO_HYS
V
mV
mA
I
LEAK−P
T
= 25°C
= −40°C to 85°C
−
−
1.0
−
10
15
A
T
A
FEEDBACK VOLTAGE
FB Input Threshold (T = −40°C to 85°C)
V
0.788
0.800
10
0.812
100
V
A
FB
FB Input Current
I
FB
−
nA
THERMAL SHUTDOWN
Thermal Shutdown Threshold (Note 5)
Hysteresis (Note 5)
T
−
−
160
30
−
−
°C
°C
SHDN
T
SDHYS
PWM SMPS MODE
Switching Frequency (T = −40°C to 85°C)
F
1.27
−
1.5
0.2
0
1.725
0.3
−
MHz
Ohm
%
A
OSC
Internal PFET ON−Resitance (I = 100 mA, V = 5.0 V, T = 25°C) (Note 5)
R
DS(on)_P
LX
IN
A
Minimum Duty Cycle
Maximum Duty Cycle
D
−
MIN
D
−
100
1.0
2.5
−
%
MAX
Soft−Start Time (V = 5.0 V, V = 1.2 V, I
= 0 mA, T = 25°C)
T
0.8
2.0
1.2
−
ms
A
IN
o
LOAD
A
SS
Main PFET Switch Current Limit (Note 5)
ENABLE
I
LIM
Enable Threshold High
Enable Threshold Low
Enable bias current (EN = 0 V)
EFFICIENCY
V
1.8
−
−
−
−
0.4
−
V
V
EN_H
V
EN_L
I
−
500
nA
EN
Output Load Current 10 mA @ 1.2 V (Note 5)
h
h
−
−
50
70
−
−
%
%
Output Load Current 100 mA to 1.2 A @ 1.2 V (Note 5)
TOTAL DEVICE
Quiescent Current Into V
(V = 5 V, V = 1.0 V, T = 25°C)
I
−
−
−
10
500
1.0
−
−
mA
mA
mA
CCP
IN
FB
A
CCP
Quiescent Current Into V (V = 5 V, V = 1.0 V, T = 25°C)
I
CC
CC
IN
FB
A
Shutdown Quiescent Current into V and V
I
CC_SD
3.0
CC
CCP
(EN = 0, V = 5 V, V = 1.0 V, T = 25°C)
IN
FB
A
5. Values are design guaranteed.
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3
NCP1596A
PIN FUNCTION DESCRIPTIONS
Pin #
Symbol
Pin Description
1
FB
Feedback pin. Part is internally compensated. Only necessary to place a voltage divider or connect the out-
put directly to this pin.
2
3
4
5
6
GND
LX
Ground
Pin connected internally to power switch. Connect externally to inductor.
Power connection to the power switch.
VCCP
VCC
EN
IC power connection.
Device Enable pin. This pin has an internal current source pull up. No connect is enable the device. With this
pin pulled down below 0.8 V, the device is disabled and enters the shutdown mode.
EN
VCCP
disable
500 nA
Isense
UVLO
VCC
Vin
Thermal
Shutdown
Oscillator
C1
V
out
= 0.8 V to 0.9 V * V
in
Short
circuit
protect
Isense
Soft Start
0.8 V
L1
Q
Q
S
R
LX
FB
driver
R1
R2
Ton(min)
D1
C2
GND
Figure 2. Detail Block Diagram
EXTERNAL COMPONENT REFERENCE DATA
V
OUT
Inductor Model
Inductor (L1)
Diode (D1)
C
(C1)
C (C2)
OUT
R1
R2
IN
3.3 V
2.5 V
1.5 V
1.2 V
CDC5D23 3R3 (1 A)
3.3 mH
MBRA210LT3G
22 mF
22 mF
31 k
21 k
8 k
10 k
CDRH6D38 3R3 (1.5 A)
22 mF x 2
22 mF x 2
CDC5D23 3R3 (1 A)
CDRH6D38 3R3 (1.5 A)
3.3 mH
3.3 mH
3.3 mH
MBRA210LT3G
MBRA210LT3G
MBRA210LT3G
22 mF
22 mF x 2
22 mF
22 mF x 2
10 k
10 k
10 k
CDC5D23 3R3 (1 A)
CDRH6D38 3R3 (1.5 A)
22 mF
22 mF x 2
22 mF
22 mF x 2
CDC5D23 3R3 (1 A)
CDRH6D38 3R3 (1.5 A)
22 mF
22 mF x 2
22 mF
22 mF x 2
5 k
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4
NCP1596A
3.8 V
3.5 V
VIN
TIME 1 ms/div
TIME 1 ms/div
VOUT
1 ms
5V
EN
1.8 V
EN
0.4 V
Figure 3. Timing Diagram
Power up the
device
VCC > 3 V
Enable the
internal Vref
NO
Disable the
Oscillator,
VCC > UVLO
YES
OTA and driver
YES
Enable
Oscillator,
OTA and
driver
Temperature
NO
<
130 deg
Ramp up
Soft start
(1 ms)
YES
Current Limit
> 2.5 A
VCC
<
UVLO
YES
Temperature
>
160 deg
Normal
YES
Operation
Figure 4. State Diagram
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5
NCP1596A
TYPICAL OPERATING CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0.0
806
804
802
800
798
796
794
−40
0
25
85
−40
0
25
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. Switch ON Resistance vs.
Temperature
Figure 6. Feedback Input Threshold vs.
Temperature
1.56
1.54
1.52
1.50
1.48
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1.46
1.44
−40
0
25
85
−40
0
25
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Switching Frequency vs.
Temperature
Figure 8. Main P−FET Current Limit vs.
Temperature
550
530
510
490
470
450
500
450
400
350
300
250
−40
0
25
85
−40
0
25
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 9. Quiescent Current Into VCC vs.
Temperature
Figure 10. Shutdown Quiescent Current vs.
Temperature
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6
NCP1596A
100
90
80
70
60
50
40
30
1.5
1.0
V
= 4.0 V
IN
V
IN
= 5.0 V
0.5
V
V
= 5.0 V
= 4.0 V
IN
0.0
IN
−0.5
−1.0
−1.5
V
= 3.3 V
V
= 3.3 V
OUT
OUT
L = 3.3 mH
C
C
L = 3.3 mH
C
C
= 22 mF
= 22 mF
= 22 mF
IN
OUT
IN
OUT
= 22 mF
100
OUTPUT CURRENT
1
10
100
1000
10000
10
1000
10000
OUTPUT CURRENT
Figure 11. Output Voltage Change vs. Output
Current
Figure 12. Efficiency vs. Output Current
100
90
80
70
60
50
40
30
1.5
1.0
V
= 4.0 V
V
IN
= 5.0 V
0.5
IN
V
V
= 5.0 V
= 4.0 V
IN
0.0
IN
−0.5
−1.0
−1.5
V
= 1.8 V
V
= 1.8 V
OUT
OUT
L = 3.3 mH
C
C
L = 3.3 mH
C
C
= 22 mF
= 22 mF
= 22 mF
IN
OUT
IN
OUT
= 22 mF
100
OUTPUT CURRENT
1
10
100
1000
10000
10
1000
10000
OUTPUT CURRENT
Figure 13. Output Voltage Change vs.
Output Current
Figure 14. Efficiency vs. Output Current
100
90
80
70
60
50
40
30
1.5
1.0
V
V
= 4.0 V
= 5.0 V
IN
0.5
V
V
= 5.0 V
IN
IN
0.0
= 4.0 V
IN
−0.5
−1.0
−1.5
V
= 1.2 V
V
= 1.2 V
OUT
OUT
L = 3.3 mH
C
C
L = 3.3 mH
C
C
= 22 mF
= 22 mF
= 22 mF
IN
OUT
IN
OUT
= 22 mF
100
OUTPUT CURRENT
1
10
100
1000
10000
10
1000
10000
OUTPUT CURRENT
Figure 16. Output Voltage Change vs.
Output Current
Figure 15. Efficiency vs. Output Current
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7
NCP1596A
(V = 5 V, I
= 10 mA, L = 3.3 mH, C
= 20 mF)
(V = 5 V, I
= 500 mA, L = 3.3 mH, C
= 20 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: Output Ripple Voltage, 20 mV/div
Upper Trace: Output Ripple Voltage, 20 mV/div
Middle Trace: L Pin Switching Waveform, 5 V/div
Middle Trace: L Pin Switching Waveform, 5 V/div
X
X
Lower Trace: Inductor Current Waveform, 500 mA/div
Time Base: 500 ns/div
Lower Trace: Inductor Current Waveform, 500 mA/div
Time Base: 200 ns/div
Figure 17. DCM Switching Waveform for
Figure 18. CCM Switching Waveform for
VOUT = 3.3 V
V
OUT = 3.3 V
(V = 5 V, I
= 10 mA, L = 3.3 mH, C
= 20 mF)
(V = 5 V, I
= 500 mA, L = 3.3 mH, C
= 20 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: Output Ripple Voltage, 20 mV/div
Upper Trace: Output Ripple Voltage, 20 mV/div
Middle Trace: L Pin Switching Waveform, 5 V/div
Middle Trace: L Pin Switching Waveform, 5 V/div
X
X
Lower Trace: Inductor Current Waveform, 500 mA/div
Time Base: 2 ms/div
Lower Trace: Inductor Current Waveform, 500 mA/div
Time Base: 200 ns/div
Figure 19. DCM Switching Waveform for
Figure 20. CCM Switching Waveform for
VOUT = 1.2 V
V
OUT = 1.2 V
(V = 5 V, I
= 10 mA, L = 3.3 mH, C
= 20 mFx2)
(V = 5 V, I
= 10 mA, L = 3.3 mH, C
= 20 mFx2)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: Input Voltage, 1 V/div
Lower Trace: Output Voltage, 1 V/div
Time Base: 500 ms/div
Upper Trace: Input Voltage, 1 V/div
Lower Trace: Output Voltage, 500 mV/div
Time Base: 500 ms/div
Figure 21. Soft−Start Waveforms for VOUT = 3.3 V
Figure 22. Soft−Start Waveforms for VOUT = 1.2 V
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NCP1596A
(V = 5 V, L = 3.3 mH, C
= 10 mFx2)
(V = 5 V, L = 3.3 mH, C
= 10 mFx2)
IN
OUT
IN
OUT
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 200 mA/div
Time Base: 20 ns/div
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 200 mA/div
Time Base: 20 ns/div
Figure 23. Load Regulation for VOUT = 3.3 V
Figure 24. Load Regulation for VOUT = 3.3 V
(V = 5 V, L = 3.3 H, C
= 10 mFx2)
(V = 5 V, L = 3.3 H, C
= 10 mF x 2)
IN
OUT
IN
OUT
Upper Trace: Output Dynamic Voltage, 50 mV/div
Lower Trace: Output Current, 200 mA/div
Time Base: 10 ns/div
Upper Trace: Output Dynamic Voltage, 50 mV/div
Lower Trace: Output Current, 200 mA/div
Time Base: 10 ns/div
Figure 25. Load Regulation for VOUT = 1.2 V
Figure 26. Load Regulation for VOUT = 1.2 V
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9
NCP1596A
DETAILED OPERATING DESCRIPTION
Introduction
inside NCP1596A to overcome the potential instability.
Slope compensation consists of a ramp signal generated by
the synchronization block and adding this to the inductor
current signal. The summed signal is then applied to the
PWM comparator.
The NCP1596A is a current−mode buck converter with
switching frequency at 1.5 MHz. High operation frequency
can reduce the capacitor value and PCB area. Also, more
features are built in this converter.
1. Internal 1 ms soft−start to avoid inrush current at
startup.
2. Internal cycle by cycle current limit provides an
output short circuit protection.
3. Internal compensation. No external compensation
components are necessary.
4. Thermal shutdown protects the devices from over
heat.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event when maximum
junction temperature is exceeded. When activated, typically
at 180°C, the shutdown signal will disable the P−channel
switch. The thermal shutdown circuit is designed with 30°C
of hysteresis. This means that the switching will not start
until the die temperature drops by this amount. This feature
is provided to prevent catastrophic failures from accidental
device overheating. It is not intended as a substitute for
proper heat sinking. NCP1596A is contained in the
thermally enhanced QFN package.
5. 100% duty cycle allowed. Speed up transient load
response.
The upper feature can provide more cost effective
solutions to applications. A simple function block diagram
and timing diagram are shown in Figure 1 and Figure 2.
Under Voltage Lockout (UVLO)
Soft−Start and Current Limit
UVLO function is used to ensure the logic level correctly
when input voltage is very low. In NCP1596A, the UVLO
level is set to 3.5 V. If the input voltage is less than 3.5 V, the
converter will shutdown itself automatically.
A soft start circuit is internally implemented to reduce the
in−rush current during startup. This helps to reduce the
output voltage over−shoot.
The current limit is set to allow peak switch current in
excess of 2 A. The intended output current of the system is
1.5 A. The ripple current is calculated to be approximately
350 mA with a 3.3 mH inductor. Therefore, the peak current
at 1.5 A output will be approximately 1.7 Amps. A 2.5 Amp
set point will allow for transient currents during load step.
The current limit circuit is implemented as a cycle−by−cycle
current limit. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the
P−channel switch current buildup during conduction with a
current limit comparator. The output of the current limit
comparator resets the PWM latch, immediately terminating
the current cycle. When output loading is short circuit,
device will auto restart with soft−start.
Low Power Shutdown Mode (EN)
NCP1596A can be disabled whenever the EN pin is tied
to ground. During the shutdown mode, the internal
reference, oscillator and driver control circuits will be turn
off, the device only consume 1 mA typically and output
voltage will be discharge to zero by the external resistor
divider. EN pin has an internal pull−up current source, which
typical value is 500 nA.
Power Saving Pulse−Frequency−Modulation (PFM)
Control Scheme
While the converter loading decreases, the converter
enters the Discontinues−conduction−mode (DCM)
operation. In DCM operation, the on−time (T ) of the
on
Error Amplifier and Slope Compensation
integrated switch for each switching cycle will decrease
when the output current decreases. In order to maintain a
high converter efficiency at light load condition. A
A fully internal compensated error amplifier is provided
inside NCP1596A. No external circuitry is needed to
stabilize the device. The error amplifier provides an error
signal to the PWM comparator by comparing the feedback
voltage (800 mV) with internal voltage reference of 1.2 V.
Current mode converter can exhibit instability at duty
cycles over 50%. A slope compensation circuit is provided
minimum T is set to 70 ns. It can make sure a minimum
on
fixed power send to output. To avoid a higher switch loss
occurs when without loading apply. This control scheme can
reduce the switching loss at light load and improve the
conversion efficiency.
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10
NCP1596A
APPLICATION INFORMATION
Output Voltage Selection
The output voltage is programmed through an external
resistor divider connect from V to FB then to GND.
For internal compensation and noise immunity, the
resistor from FB to GND should be in 10 k to 20 k ranges.
The relationship between the output voltage and feedback
resistor is given by:
ripple current, input voltage, output voltage, output current
and operation frequency, the inductor value is given by:
OUT
VOUT
VOUT
ǒ1 * Ǔ
VIN
(eq. 2)
DIL
+
L FSW
DIL : peak to peak inductor ripple current
L: inductor value
FSW: switching frequency
ǒ1 ) R1Ǔ
(eq. 1)
V
OUT + VFB
After selected a suitable value of the inductor, it should be
check out the inductor saturation current. The saturation
current of the inductor should be higher than the maximum
load plus the ripple current.
R2
V
V
: Output voltage
: Feedback Voltage
OUT
FB
R1: Feedback resistor from V
R2: Feedback resistor from FB to GND.
to FB.
OUT
DIL
(eq. 3)
DIL(MAX) + DIOUT(MAX)
)
2
Input Capacitor Selection
D
D
: Maximum inductor current
: Maximum output current
IL(MAX)
In the PWM buck converter, the input current is pulsating
current with switching noise. Therefore, a bypass input
capacitor must choose for reduce the peak current drawn
from the power supply. For NCP1596A, low ESR ceramic
capacitor of 10 mF should be used for most of cases. Also,
the input capacitor should be placed as close as possible to
IOUT(MAX)
Output Capacitor Selection
Output capacitor value is based on the target output ripple
voltage. For NCP1596A, the output capacitor is required a
ceramic capacitors with low ESR value. Assume buck
converter duty cycle is 50%. The output ripple voltage in
PWM mode is given by:
the V
pin for effective bypass the supply noise.
CCA
Inductor Selection
The inductor parameters are including three items, which
are DC resistance, inductor value and saturation current.
Inductor DC resistance will effect the convector overall
efficiency, low DC resistor value can provide a higher
efficiency. Thus, inductor value are depend on the inductor
1
ǒ
) ESRǓ(eq. 4)
DVOUT [ DIL
4 FSW COUT
In general, value of ceramic capacitor using 20 mF should
be a good choice.
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11
NCP1596A
PACKAGE DIMENSIONS
DFN6 3*3 MM, 0.95 PITCH
CASE 506AH−01
ISSUE O
NOTES:
A
D
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMESNION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
REFERENCE
MILLIMETERS
DIM MIN
0.80
A1 0.00
NOM MAX
2X
A
0.90
0.03
1.00
0.05
0.15
C
A3
b
D
D2 2.40
E
E2 1.50
e
0.20 REF
0.40
3.00 BSC
2.50
3.00 BSC
1.60
0.95 BSC
−−−
2X
0.35
0.45
2.60
1.70
0.15
C
TOP VIEW
0.10
C
C
K
L
0.21
0.30
−−−
0.50
A
6X
0.40
SEATING
PLANE
0.08
(A3)
C
SOLDERING FOOTPRINT*
SIDE VIEW
D2
A1
0.450
0.0177
0.950
6X L
4X
e
0.0374
1
6
3
4
E2
1.700
0.0685
6X K
3.31
0.130
6X b
(NOTE 3)
0.10 C A B
0.05
C
2.60
BOTTOM VIEW
0.63
0.025
0.1023
SCALE 10:1
mm
inches
ǒ
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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