NCP1597A [ONSEMI]
1 MHz, 2.0 A Synchronous Buck Regulator; 1兆赫， 2.0 A同步降压稳压器
| 型号： | NCP1597A |
| 厂家： | 
ONSEMI |
| 描述： | 1 MHz, 2.0 A Synchronous Buck Regulator |
| 文件： | 总13页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1597A
1 MHz, 2.0 A Synchronous
Buck Regulator
The NCP1597A family are fixed 1 MHz, high−output−current,
synchronous PWM converters that integrate a low−resistance,
high−side P−channel MOSFET and a low−side N−channel MOSFET.
The NCP1597A utilizes current mode control to provide fast transient
response and excellent loop stability. It regulates input voltages from
4.0 V to 5.5 V down to an output voltage as low as 0.8 V and is able to
supply up to 2.0 A.
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MARKING
DIAGRAM
The NCP1597A includes an internally fixed switching frequency
(FSW), and an internal soft−start to limit inrush currents. Using the EN
pin, shutdown supply current is reduced to 3 mA maximum.
Other features include cycle−by−cycle current limiting,
short−circuit protection, power saving mode and thermal shutdown.
1
1
1597A
AYWWG
G
DFN6
CASE 506AH
A
Y
= Assembly Location
= Year
= Work Week
Features
WW
G
= Pb−Free Package
• Input Voltage Range: from 4.0 V to 5.5 V
• Internal 140 mW High−Side Switching P−Channel MOSFET and
90 mW Low−Side N−Channel MOSFET
• Fixed 1 MHz Switching Frequency
• Cycle−by−Cycle Current Limiting
• Overtemperature Protection
(Note: Microdot may be in either location)
PIN CONNECTIONS
FB
GND
LX
1
2
3
6 EN
• Internal Soft−Start
5
4
VCC
• Start−up with Pre−Biased Output Load
• Adjustable Output Voltage Down to 0.8 V
• Power Saving Mode During Light Load
• These are Pb−Free Devices
VCCP
ORDERING INFORMATION
Applications
• DSP Power
• Hard Disk Drivers
• Computer Peripherals
• Home Audio
• Set−Top Boxes
• Networking Equipment
• LCD TV
• Wireless and DSL/Cable Modem
• USB Power Devices
†
Device
NCP1597AMNTWG
Package
Shipping
DFN6
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010 − Rev. 0
NCP1597/D
NCP1597A
BLOCK DIAGRAM
NCP1597A
VCCP
VCC
+
CA
−
Power Reset
UVLO
NC/EN
THD
Hiccup
OSC
+
PMOS
M1
Soft−Start
−
+
+
PWM
Control
Logic
LX
gm
Vref
+
FB
−
GND
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin No
Symbol
Description
1
FB
Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output
voltage to this pin to set the converter’s output voltage.
2
3
4
5
GND
LX
Ground pin. Connect to thermal pad.
The drains of the internal MOSFETs. The output inductor should be connected to this pin.
Power input for the power stage
V
CCP
V
CC
Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect
to this pin.
6
EN
Logic input to enable the part. Logic high to turn on the part and logic low to shut off the part.
EP
PAD
Exposed pad of the package provides both electrical contact to the ground and good thermal contact
to the PCB. This pad must be soldered to the PCB for proper operation.
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2
NCP1597A
APPLICATION CIRCUIT
V
VCCP
VCC
LX
GND
FB
V
out
in
4.0 V − 5.5 V
NC/EN
Figure 2. NCP1597A
Symbol
ABSOLUTE MAXIMUM RATINGS
Rating
Value
Unit
Power Supply Pin (Pin 4, 5) to GND
V
in
6.5
V
−0.3 (DC)
−1.0 (t < 100 ns)
LX to GND
V
+ 0.3
V
V
in
−0.6 (DC)
−1.0 (t < 100 ns)
All other pins
6.0
−0.3 (DC)
−1.0 (t < 100 ns)
Operating Temperature Range
Junction Temperature
TA
TJ
−40 to +85
−40 to +150
−55 to +150
68.5
°C
°C
Storage Temperature Range
TS
°C
Thermal Resistance Junction−to−Air (Note 1)
RqJA
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper.
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NCP1597A
ELECTRICAL CHARACTERISTICS
(V = 4.0 V − 5.5 V, V = 1.2 V, T = +25°C for typical value; −40°C < T < 85°C for min/max values unless noted otherwise)
in
out
J
J
Parameter
Symbol
Test Conditions
Min
4.0
3.2
Typ
Max
5.5
Unit
V
V
V
Input Voltage Range
V
in
in
UVLO Threshold
3.5
275
1.7
25
3.8
V
CC
UVLO Hysteresis
mV
mA
mA
mA
V
V
V
Quiescent Current
I
V
V
= 5 V,V = 1.5 V, (No Switching)
2.0
3.0
CC
inVCC
in
FB
Quiescent Current
I
= 5 V,V = 1.5 V, (No Switching)
CCP
inVCCP
QSHDN
in
FB
Shutdown Supply Current (Note 2)
I
EN = 0 V
1.8
in
FEEDBACK VOLTAGE
Reference Voltage
V
0.788
0.800
10
0.812
100
V
ref
Feedback Input Bias Current
Feedback Voltage Line Regulation
PWM
I
FB
V
= 0.8 V
nA
FB
V
in
= 4.0 V to 5.5 V
0.06
%/V
Maximum Duty Cycle (Regulating)
Minimum Controllable ON Time (Note 2)
PULSE−BY−PULSE CURRENT LIMIT
Pulse−by−Pulse Current Limit (Regulation)
Pulse−by−Pulse Current Limit (Soft−Start)
OSCILLATOR
83
85
50
%
ns
I
2.7
4.0
3.9
5.3
4.3
6.1
A
A
LIM
I
LIMSS
Oscillator Frequency
F
0.87
1.0
140
90
1.13
MHz
SW
MOSFET
High Side MOSFET ON Resistance
High Side MOSFET Leakage (Note 2)
Low Side MOSFET ON Resistance
Low Side MOSFET Leakage (Note 2)
ENABLE (NCP1597A)
R
R
I
I
= 100 mA, V = 5 V
200
10
mW
mA
DS(on)
DS
GS
HS
V
= 0 V, V
= 0 V
EN
SW
= 100 mA, V = 5 V
125
10
mW
mA
DS(on)
DS
GS
LS
V
= 0 V, V
= 5 V
EN
SW
EN HI Threshold
ENHI
ENLO
1.4
V
V
EN LO Threshold
0.4
3.0
EN Hysteresis
200
1.4
mV
mA
EN Pullup Current
SOFT−START
Soft−Start Ramp Time
t
SS
F
SW
= 1 MHz
1.0
2.0
ms
ms
Hiccup Timer
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
2. Guaranteed by design. Not production tested.
185
30
°C
°C
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NCP1597A
TYPICAL OPERATING CHARACTERISTICS
3.7
3.6
3.5
3.4
3.3
3.2
3.1
815
810
805
800
795
790
785
UVLO Rising Threshold
UVLO Falling Threshold
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 3. Undervoltage Lockout vs.
Temperature
Figure 4. Feedback Input Threshold vs.
Temperature
6.0
5.5
5.0
4.5
4.0
3.5
1.3
1.2
1.1
1.0
0.9
I
(Soft−Start)
LIM
I
(Regulation)
35
LIM
0.8
0.7
−40
−15
10
35
60
85
−40
−15
10
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. Switching Frequency vs.
Temperature
Figure 6. Current Limit vs. Temperature
2.0
1.8
1.6
1.4
2.0
1.8
1.6
1.4
1.2
1.0
1.2
1.0
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Quiescent Current Into VCC vs.
Temperature
Figure 8. Quiescent Current Into VCC vs.
Temperature
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5
NCP1597A
TYPICAL OPERATING CHARACTERISTICS
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
100
V
IN
= 4.0 V
V
= 3.3 V
OUT
90
80
70
60
50
40
30
20
L = 3.3 mH
= 2 x 22 mF
V
= 5.0 V
IN
C
OUT
V
V
= 5.0 V
= 4.0 V
IN
V
= 3.3 V
OUT
IN
L = 3.3 mH
= 2 x 22 mF
C
OUT
0.01
0.1
1
10
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, OUTPUT CURRENT (A)
I
, OUTPUT CURRENT (A)
I
OUT
OUT
Figure 9. Load Regulation for VOUT = 3.3 V
Figure 10. Efficiency vs. Output Current for
OUT = 3.3 V
V
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
100
90
80
70
60
50
40
30
20
V
= 1.8 V
OUT
V
IN
= 4.0 V
L = 3.3 mH
= 2 x 22 mF
C
OUT
V
= 5.0 V
IN
V
V
= 5.0 V
= 4.0 V
IN
IN
V
= 1.8 V
OUT
L = 3.3 mH
= 2 x 22 mF
C
OUT
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, OUTPUT CURRENT (A)
0.01
0.1
1
10
I
I
, OUTPUT CURRENT (A)
OUT
OUT
Figure 11. Load Regulation for VOUT = 1.8 V
Figure 12. Efficiency vs. Output Current for
OUT = 1.8 V
V
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
100
90
80
70
60
50
40
30
20
V
= 1.2 V
OUT
V
IN
= 4.0 V
L = 3.3 mH
= 2 x 22 mF
C
OUT
V
IN
= 5.0 V
V
V
= 5.0 V
= 4.0 V
IN
IN
V
= 1.2 V
OUT
L = 3.3 mH
= 2 x 22 mF
C
OUT
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, OUTPUT CURRENT (A)
0.01
0.1
I , OUTPUT CURRENT (A)
OUT
1
10
I
OUT
Figure 13. Load Regulation for VOUT = 1.2 V
Figure 14. Efficiency vs. Output Current for
OUT = 1.2 V
V
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NCP1597A
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
(V = 5 V, I
= 700 mA, L = 3.3 mH, C
= 2 x 22 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: L Pin Switching Waveform, 2 V/div
Upper Trace: L Pin Switching Waveform, 2 V/div
X
X
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Figure 15. DCM Switching Waveform for
Figure 16. CCM Switching Waveform for
VOUT = 3.3 V
V
OUT = 3.3 V
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
(V = 5 V, I
= 400 mA, L = 3.3 mH, C
= 2 x 22 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: L Pin Switching Waveform, 2 V/div
Upper Trace: L Pin Switching Waveform, 2 V/div
X
X
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 200 mA/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Figure 17. DCM Switching Waveform for
Figure 18. CCM Switching Waveform for
VOUT = 1.2 V
V
OUT = 1.2 V
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: EN Pin Voltage, 2 V/div
Middle Trace: Output Voltage, 1 V/div
Lower Trace: Inductor Current, 100 mA/div
Upper Trace: EN Pin Voltage, 2 V/div
Middle Trace: Output Voltage, 1 V/div
Lower Trace: Inductor Current, 100 mA/div
Figure 19. Soft−Start Waveforms for VOUT = 3.3 V
Figure 20. Soft−Start Waveforms for VOUT = 1.2 V
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NCP1597A
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
(V = 5 V, I
= 100 mA, L = 3.3 mH, C
= 2 x 22 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Figure 21. Transient Response for VOUT
3.3 V
=
Figure 22. Transient Response for VOUT
3.3 V
=
(V = 5 V, I
= 100 mA, L = 3.3 H, C
= 2 x 22 mF)
(V = 5 V, I
= 100 mA, L = 3.3 H, C
= 2 x 22 mF)
IN
LOAD
OUT
IN
LOAD
OUT
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Input Current, 500 mA/div
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Input Current, 500 mA/div
Figure 23. Transient Response for VOUT
1.2 V
=
Figure 24. Transient Response for VOUT
1.2 V
=
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8
NCP1597A
DETAILED DESCRIPTION
Overview
delivering up to 2.0 A of current. When the controller is
disabled or during a Fault condition, the controller’s output
stage is tri−stated by turning OFF both the upper and lower
MOSFETs.
The NCP1597A is a synchronous PWM controller that
incorporates all the control and protection circuitry
necessary to satisfy a wide range of applications. The
NCP1597A employs current mode control to provide fast
transient response, simple compensation, and excellent
stability. The features of the NCP1597A include a precision
Adaptive Dead Time Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET freewheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. In NCP1597A, the drivers and MOSFETs are
integrated in a single chip. The parasitic inductance is
minimized. Adaptive dead time control method is used in
NCP1597A to prevent the shoot through from happening
and minimizing the diode conduction loss at the same time.
reference, fixed
1
MHz switching frequency,
a
transconductance error amplifier, an integrated high−side
P−channel MOSFET and low−side N−Channel MOSFET,
internal soft−start, and very low shutdown current. The
protection features of the NCP1597A include internal
soft−start, pulse−by−pulse current limit, and thermal
shutdown.
Reference Voltage
The NCP1597A incorporates an internal reference that
allows output voltages as low as 0.8 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
Pulse Width Modulation
A high−speed PWM comparator, capable of pulse widths
as low as 50 ns, is included in the NCP1597A. The inverting
input of the comparator is connected to the output of the
error amplifier. The non−inverting input is connected to the
the current sense signal. At the beginning of each PWM
cycle, the CLK signal sets the PWM flip−flop and the upper
MOSFET is turned ON. When the current sense signal rises
above the error amplifier’s voltage then the comparator will
reset the PWM flip−flop and the upper MOSFET will be
turned OFF.
Oscillator Frequency
A fixed precision oscillator is provided. The oscillator
frequency range is 1 MHz with $13% variation.
Transconductance Error Amplifier
The transconductance error amplifier’s primary function
is to regulate the converter’s output voltage using a resistor
divider connected from the converter’s output to the FB pin
of the controller, as shown in the applications Schematic. If
a Fault occurs, the amplifier’s output is immediately pulled
to GND and PWM switching is inhibited.
Power Save Mode
If the load current decreases, the converter will enter
power save mode operation automatically. During power
save mode, the converter skips switching and operates with
reduced frequency, which minimizes the quiescent current
and maintain high efficiency.
Internal Soft−Start
To limit the startup inrush current, an internal soft start
circuit is used to ramp up the reference voltage from 0 V to
its final value linearly. The internal soft start time is 1 ms
typically.
Current Sense
The NCP1597A monitors the current in the upper
MOSFET. The current signal is required by the PWM
comparator and the pulse−by−pulse current limiter.
Output MOSFETs
The NCP1597A includes low R
, both high−side
DS(on)
P−channel and low−side N−channel MOSFETs capable of
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NCP1597A
PROTECTIONS
Undervoltage Lockout (UVLO)
overcurrent detection while charging the output capacitors.
Hiccup mode reduces input supply current and power
dissipation during a short circuit. It also allows for much
improved system up−time, allowing auto−restart upon
removal of a temporary short−circuit.
The under voltage lockout feature prevents the controller
from switching when the input voltage is too low to power
the internal power supplies and reference. Hysteresis must
be incorporated in the UVLO comparator to prevent IxR
drops in the wiring or PCB traces from causing ON/OFF
cycling of the controller during heavy loading at power up
or power down.
Pre−Bias Startup
In some applications the controller will be required to start
switching when it’s output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP1597A supports
pre−bias start up by holding Low side FETs off till soft start
ramp reaches the FB Pin voltage.
Overcurrent Protection (OCP)
NCP1597A detects high side switch current and then
compares to a voltage level representing the overcurrent
threshold limit. If the current through the high side FET
exceeds the overcurrent threshold limit for seven
consecutive switching cycles, overcurrent protection is
triggered.
Once the overcurrent protection occurs, hiccup mode
engages. First, hiccup mode, turns off both FETs and
discharges the internal compensation network at the output
of the OTA. Next, the IC waits typically 2 ms and then resets
the overcurrent counter. After this reset, the circuit attempts
another normal soft−start. During soft−start, the overcurrent
protection threshold is increased to prevent false
Thermal Shutdown
The NCP1597A protects itself from over heating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF.
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NCP1597A
APPLICATION INFORMATION
Programming the Output Voltage
Iripple
(eq. 3)
The output voltage is set using a resistive voltage divider
from the output voltage to FB pin (see Figure 25). So the
output voltage is calculated according to Eq.1.
COUT(min) +
8 @ f @ Vripple
Where V
is the allowed output voltage ripple.
ripple
R1 ) R2
The required ESR for this amount of ripple can be
calculated by equation 5.
(eq. 1)
Vout + VFB
@
R2
Vripple
(eq. 4)
ESR +
V
out
Iripple
Based on Equation 2 to choose capacitor and check its
ESR according to Equation 3. If ESR exceeds the value from
Eq.4, multiple capacitors should be used in parallel.
Ceramic capacitor can be used in most of the applications.
In addition, both surface mount tantalum and through−hole
aluminum electrolytic capacitors can be used as well.
R1
FB
R2
Maximum Output Capacitor
NCP1597A family has internal 1 ms fixed soft−start and
overcurrent limit. It limits the maximum allowed output
capacitor to startup successfully. The maximum allowed
output capacitor can be determined by the equation:
Figure 25. Output divider
Di
p−p
Inductor Selection
Ilim(min) * Iload(max)
*
2
The inductor is the key component in the switching
regulator. The selection of inductor involves trade−offs
among size, cost and efficiency. The inductor value is
selected according to the equation 2.
(eq. 5)
Cout(max)
+
VoutńTSS(min)
Where T
is the minimum soft−start period (1ms);
SS(min)
D
iPP
is the current ripple.
Vout
Vout
This is assuming that a constant load is connected. For
example, with 3.3 V/2.0 A output and 20% ripple, the max
(eq. 2)
L +
@
ǒ
1 *
Ǔ
f @ Iripple
Vin(max)
allowed output capacitors is 546 mF.
Where V − the output voltage;
out
Input Capacitor Selection
f − switching frequency, 1.0 MHz;
I
− Ripple current, usually it’s 20% − 30% of output
The input capacitor can be calculated by Equation 6.
ripple
current;
V
1
Cin(min) + Iout(max) @ Dmax
@
− maximum input voltage.
(eq. 6)
in(max)
f @ Vin(ripple)
Choose a standard value close to the calculated value to
maintain a maximum ripple current within 30% of the
maximum load current. If the ripple current exceeds this
30% limit, the next larger value should be selected.
The inductor’s RMS current rating must be greater than
the maximum load current and its saturation current should
be about 30% higher. For robust operation in fault conditions
(start−up or short circuit), the saturation current should be
high enough. To keep the efficiency high, the series
resistance (DCR) should be less than 0.1 W, and the core
material should be intended for high frequency applications.
Where V
is the required input ripple voltage.
in(ripple)
Vout
+
Dmax
is the maximum duty cycle.
(eq. 7)
Vin(min)
Power Dissipation
The NCP1597A is available in a thermally enhanced
6−pin, DFN package. When the die temperature reaches
+185°C, the NCP1597A shuts down (see the
Thermal−Overload Protection section). The power
dissipated in the device is the sum of the power dissipated
from supply current (PQ), power dissipated due to switching
Output Capacitor Selection
The output capacitor acts to smooth the dc output voltage
and also provides energy storage. So the major parameter
necessary to define the output capacitor is the maximum
allowed output voltage ripple of the converter. This ripple is
related to capacitance and the ESR. The minimum
capacitance required for a certain output ripple can be
calculated by Equation 4.
the internal power MOSFET (P ), and the power
SW
dissipated due to the RMS current through the internal
power MOSFET (PON). The total power dissipated in the
package must be limited so the junction temperature does
not exceed its absolute maximum rating of +150°C at
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11
NCP1597A
maximum ambient temperature. Calculate the power lost in
the NCP1597A using the following equations:
1. High side MOSFET
ǒ
Ǔ
TJ + TC ) PTOTAL @ qJC
(eq. 15)
q
is the junction−to−case thermal resistance equal to
1.7°C/W. T is the temperature of the case and TJ is the
JC
C
The conduction loss in the top switch is:
junction temperature, or die temperature. The
case−to−ambient thermal resistance is dependent on how
well heat can be transferred from the PC board to the air.
Solder the underside−exposed pad to a large copper GND
plane. If the die temperature reaches the thermal shutdown
threshold the NCP1597A shut down and does not restart
again until the die temperature cools by 30°C.
PHSON + I 2
RDS(on)HS
(eq. 8)
RMS_HSFET
Where:
2
DIPP
2
ǒI
Ǔ
(eq. 9)
IRMS_FET
+
)
D
Ǹ
out
12
DI is the peak−to−peak inductor current ripple.
Layout Consideration
PP
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1597A switch.
When operating at higher currents and input voltages, with
poor layout, this spike can generate voltages across the
NCP1597A that may exceed its absolute maximum rating.
A ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The FB component should be kept as far away as possible
from the switch node. The ground for these components
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
The power lost due to switching the internal power high side
MOSFET is:
ǒ
2
Ǔ
Vin @ Iout @ tr ) tf @ fSW
(eq. 10)
PHSSW
+
t and t are the rise and fall times of the internal power
r
f
MOSFET measured at SW node.
2. Low side MOSFET
The power dissipated in the top switch is:
PLSON + IRMS_LSFET 2 @ RDS(on)LS
(eq. 11)
(eq. 12)
Where:
2
DIPP
2
(
)
ǒI
Ǔ@ 1 * D
IRMS_LSFET
+
)
Ǹ
out
12
DI is the peak−to−peak inductor current ripple.
PP
The switching loss for the low side MOSFET can be
ignored.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1597A. This is
achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.
The power lost due to the quiescent current (IQ) of the device
is:
PQ + Vin @ IQ
IQ is the switching quiescent current of the NCP1597A.
PTOTAL + PHSON ) PHSSW ) PLSON ) PQ
(eq. 13)
(eq. 14)
Calculate the temperature rise of the die using the following
equation:
http://onsemi.com
12
NCP1597A
PACKAGE DIMENSIONS
DFN6 3x3, 0.95P
CASE 506AH−01
ISSUE O
A
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMESNION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
REFERENCE
MILLIMETERS
2X
DIM MIN
0.80
A1 0.00
NOM MAX
0.15
C
A
0.90
0.03
1.00
0.05
2X
A3
b
D
0.20 REF
0.40
3.00 BSC
2.50
3.00 BSC
1.60
0.35
0.45
2.60
1.70
0.15
C
TOP VIEW
D2 2.40
0.10
C
E
E2 1.50
e
K
L
0.95 BSC
−−−
0.40
A
6X
0.21
0.30
−−−
0.50
SEATING
PLANE
0.08
C
(A3)
e
C
SIDE VIEW
D2
A1
SOLDERING FOOTPRINT*
0.450
0.0177
6X L
4X
0.950
0.0374
1
6
3
4
E2
6X K
1.700
0.685
3.31
0.130
6X b
(NOTE 3)
0.10 C A B
0.05
C
BOTTOM VIEW
2.60
0.63
0.025
0.1023
SCALE 10:1
mm
inches
ǒ
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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NCP1597/D
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