NCP1597B [ONSEMI]
1 MHz, 2 A Synchronous Buck Regulator; 为1 MHz ，2 A同步降压稳压器
| 型号： | NCP1597B |
| 厂家： | 
ONSEMI |
| 描述： | 1 MHz, 2 A Synchronous Buck Regulator |
| 文件： | 总9页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1597B
Product Preview
1 MHz, 2 A Synchronous
Buck Regulator
The NCP1597B is a fixed 1 MHz, high−output−current,
synchronous PWM converter that integrates a low−resistance,
high−side P−channel MOSFET and a low−side N−channel MOSFET.
The NCP1597B utilizes current mode control to provide fast transient
response and excellent loop stability. It regulates input voltages from
4.0 V to 5.5 V down to an output voltage as low as 0.8 V and is able to
supply up to 2 A.
The NCP1597B has features including fixed internal switching
frequency (FSW), and an internal soft−start to limit inrush current.
Using the EN pin, shutdown supply current is reduced to 3 mA
maximum.
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MARKING
DIAGRAM
1597B
ALYWG
G
DFN10
CASE 485C
1597B = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Other features include cycle−by−cycle current limiting;
short−circuit protection, low dropout mode, power saving mode and
thermal shutdown.
Features
(Note: Microdot may be in either location)
• Input Voltage Range: from 4.0 V to 5.5 V
• Internal 140 mW High−Side Switching P−Channel MOSFET and
90 mW Low−Side N−Channel MOSFET
• Fixed 1 MHz Switching Frequency
• Cycle−by−Cycle Current Limiting
• Overtemperature Protection
PIN CONNECTIONS
EN
VCC
1
2
3
4
5
10 PGND
9
PGND
VCCP
AGND
FB
8 LX
7 LX
6 NC
• Internal Soft−Start
• Start−up with Pre−Biased Output Load
• Adjustable Output Voltage Down to 0.8 V
• Power Saving Mode During Light Load
• Low Dropout Mode Operation to Extend the Battery Life
• These are Pb−Free Devices
(Top View)
ORDERING INFORMATION
†
Device
Package
Shipping
NCP1597BMNTWG DFN10
3000 / Tape &
Reel
Applications
• DSP Power
• Hard Disk Drivers
• Computer Peripherals
• Home Audio
• Set−Top Boxes
• Networking Equipment
• LCD TV
• Wireless and DSL/Cable Modem
• USB Power Devices
(Pb−Free)
NCP1597BMNTXG
DFN10
3000 / Tape &
Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. P0
NCP1597B/D
NCP1597B
BLOCK DIAGRAM
NCP1597B
VCCP
VCC
EN
+
CA
−
Power Reset
UVLO
THD
Hiccup
OSC
+
PMOS
M1
Soft−Start
LX
LX
−
+
+
PWM
Control
Logic
gm
Vref
+
FB
−
AGND
PGND
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin No
Symbol
Description
1
EN
Logic input to enable the part. Logic high turns on the part and a logic low disables it. An internal pullup
forces the part into an enable state when no external bias is present on the pin.
2
V
CC
Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect to
this pin.
3
4
5
V
Power input for the power stage
CCP
AGND
FB
Analog ground pin. Connect to thermal pad.
Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage
to this pin to set the converter’s output voltage.
6
NC
LX
No connection
7, 8
9, 10
EP
The drains of the internal MOSFETs. The output inductor should be connected to these pins.
Power ground pins. Connect to thermal pad.
PGND
PAD
Exposed pad of the package provides both electrical contact to the ground and good thermal contact to
the PCB. This pad must be soldered to the PCB for proper operation.
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2
NCP1597B
APPLICATION CIRCUIT
8
7
2
V
VCC
VCCP
EN
LX
LX
V
out
in
4.0 V − 5.5 V
3
1
5
FB
10
9
6
4
NC
PGND
PGND
AGND
NCP1597B
Figure 2. NCP1597B
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 V (DC) to 7.0 V −1.0 V For T < 100 ns
Unit
Power Supply Pin (Pin 4, 5) to GND
LX to GND
V
in
−0.6 V to V + 0.3 V, −1.0 V For T < 100 ns
in
All other pins
−0.3 V to 6.5 V, −1.0 V For T < 100 ns
Operating Temperature Range
Junction Temperature
Storage Temperature Range
TA
TJ
−40 to +85
−40 to +150
−55 to +150
68.5
°C
°C
TS
PD
°C
Pkg Power Dissipation (T = +25°C)
°C/W
A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NCP1597B
ELECTRICAL CHARACTERISTICS
(V = 4.0 V − 5.5 V, V = 1.2 V, T = +25°C for typical value; −40°C < T < 125°C for min/max values unless noted otherwise)
in
out
J
J
Parameter
Symbol
Test Conditions
Min
4.0
3.5
Typ
Max
5.5
Unit
V
V
V
Input Voltage Range
V
in
in
UVLO Threshold
3.7
180
1.1
60
3.9
V
CC
UVLO Hysteresis
mV
mA
mA
mA
V
V
V
Quiescent Current
I
V
= 5.0 V, V = 1.5 V, (No Switching)
2.0
3.0
CC
inVCC
in
FB
Quiescent Current
I
V
= 5.0 V,V = 1.5 V, (No Switching)
CCP
inVCCP
QSHDN
in
FB
Shutdown Supply Current (Note 1)
I
EN = 0 V
1.4
in
FEEDBACK VOLTAGE
Reference Voltage
V
0.788
0.800
10
0.812
100
V
ref
Feedback Input Bias Current
Feedback Voltage Line Regulation
PWM
I
FB
V
= 0.8 V
nA
FB
V
in
= 4.0 V to 5.5 V
0.03
%/V
Maximum Duty Cycle (regulating)
LDO Mode Threshold Voltage (falling)
LDO Mode Threshold Hysteresis (rising)
Minimum Controllable ON Time (Note 1)
PULSE−BY−PULSE CURRENT LIMIT
Pulse−by−Pulse Current Limit
OSCILLATOR
83
%
V
0.74
0.75
12
0.76
50
mV
ns
I
2.6
3.0
1.0
140
90
3.4
A
LIM
Oscillator Frequency
F
0.87
1.13
MHz
SW
MOSFET
High Side MOSFET ON Resistance
High Side MOSFET Leakage (Note 1)
Low Side MOSFET ON Resistance
Low Side MOSFET Leakage (Note 1)
ENABLE
R
R
I
I
= 100 mA, V = 5 V
200
10
mW
mA
DS(on)
HS
DS
GS
V
= 0 V, V
= 0 V
EN
SW
= 100 mA, V = 5 V
125
10
mW
mA
DS(on)
LS
DS
GS
V
= 0 V, V
= 5 V
EN
SW
EN HI Threshold
ENHI
ENLO
1.4
V
V
EN LO Threshold
0.4
3.0
EN Hysteresis
300
1.4
mV
mA
EN Pullup Current
SOFT−START
Soft−Start Ramp Time
t
SS
F
SW
= 1 MHz
1.0
2.0
ms
ms
Hiccup Timer
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
170
40
°C
°C
1. Guaranteed by design. Not production tested.
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4
NCP1597B
DETAILED DESCRIPTION
Overview
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET freewheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. In NCP1597B, the drivers and MOSFETs are
integrated in a single chip. The parasitic inductance is
minimized. Adaptive dead time control method is used in
NCP1597B to prevent the shoot through from happening
and minimizing the diode conduction loss at the same time.
The NCP1597B is a synchronous PWM controller that
incorporates all the control and protection circuitry
necessary to satisfy a wide range of applications. The
NCP1597B employs current mode control to provide fast
transient response, simple compensation, and excellent
stability. The features of the NCP1597B include a precision
reference, fixed
1
MHz switching frequency,
a
transconductance error amplifier, an integrated high−side
P−channel MOSFET and low−side N−Channel MOSFET,
internal soft−start, and very low shutdown current. The
protection features of the NCP1597B include internal
soft−start, pulse−by−pulse current limit, and thermal
shutdown.
Pulse Width Modulation
A high−speed PWM comparator, capable of pulse widths
as low as 50 ns, is included in the NCP1597B. The inverting
input of the comparator is connected to the output of the
error amplifier. The non−inverting input is connected to the
the current sense signal. At the beginning of each PWM
cycle, the CLK signal sets the PWM flip−flop and the upper
MOSFET is turned ON. When the current sense signal rises
above the error amplifier’s voltage then the comparator will
reset the PWM flip−flop and the upper MOSFET will be
turned OFF.
Reference Voltage
The NCP1597B incorporates an internal reference that
allows output voltages as low as 0.8 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
When input and output voltage gets close to each other, the
high side FET will be ON all the time (100% duty cycle) and
the part operates in a low dropout mode.
Oscillator Frequency
A fixed precision oscillator is provided. The oscillator
frequency range is 1 MHz with $13% variation.
Low Dropout Mode operation
Transconductance Error Amplifier
When the input voltage and output voltage come close to
each other, the NCP1597B enters into LDO (low dropout)
mode. The high side FET is turned on 100% for one or more
cycles. With further decreasing of input voltage, the high
side FET will be on completely. In this case, the converter
offers a low voltage difference. This is particularly useful in
battery−powered applications to achieve longest operation
time by taking full advantage of the whole battery voltage
range.
The transconductance error amplifier’s primary function
is to regulate the converter’s output voltage using a resistor
divider connected from the converter’s output to the FB pin
of the controller, as shown in the applications Schematic. If
a Fault occurs, the COMP pin is immediately pulled to GND
and PWM switching is inhibited.
Internal Soft−Start
To limit the startup inrush current, an internal soft start
circuit is used to ramp up the reference voltage from 0 V to
its final value linearly. The internal soft start time is 1 ms
typically.
Power Save Mode
If the load current decreases, the converter will enter
power save mode operation automatically. During power
save mode, the converter skips switching and operates with
reduced frequency, which minimizes the quiescent current
and maintain high efficiency.
Output MOSFETs
The NCP1597B includes low R
, both high−side
DS(on)
P−channel and low−side N−channel MOSFETs capable of
delivering up to 2.0 A of current. When the controller is
disabled or during a Fault condition, the controller’s output
stage is tri−stated by turning OFF both the upper and lower
MOSFETs.
Current Sense Amplifier
A high−bandwidth current sense amplifier monitors the
current in the upper MOSFET. The current signal is required
by the PWM comparator, the pulse−by−pulse current
limiter.
Adaptive Dead Time Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
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5
NCP1597B
PROTECTIONS
Undervoltage Lockout (UVLO)
limit circuit limits peak current to 3.0 A during overload and
short circuit conditions.
The under voltage lockout feature prevents the controller
from switching when the input voltage is too low to power
the internal power supplies and reference. Hysteresis must
be incorporated in the UVLO comparator to prevent IxR
drops in the wiring or PCB traces from causing ON/OFF
cycling of the controller during heavy loading at power up
or power down.
Pre−Bias Startup
In some applications the controller will be required to start
switching when it’s output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP1597B supports
pre−bias start up by holding Low side FETs off till soft start
ramp reaches the FB Pin voltage.
Overcurrent Protection (OCP)
NCP1597B detects high side switch current and then
compares to a voltage level representing the overcurrent
threshold limit. If the current through high side FET exceeds
the overcurrent threshold limit, overcurrent protection is
triggered. The system ignores the overcurrent signal for the
leading edge blanking time at the beginning of each cycle to
avoid any turn−on noise glitches.
Thermal Shutdown
The NCP1597B protects itself from over heating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF.
Then the high side MOSFET is turned−off for the rest of
cycle after a propagation delay. This cycle−by−cycle current
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6
NCP1597B
APPLICATION INFORMATION
Programming the Output Voltage
Iripple
(eq. 3)
The output voltage is set using a resistive voltage divider
from the output voltage to FB pin (see Figure 3). So the
output voltage is calculated according to Eq.1.
COUT(min) +
8 @ f @ Vripple
Where V
is the allowed output voltage ripple.
ripple
R1 ) R2
The required ESR for this amount of ripple can be
calculated by equation 5.
(eq. 1)
Vout + VFB
@
R2
Vripple
(eq. 4)
ESR +
V
out
Iripple
Based on Equation 2 to choose capacitor and check its
ESR according to Equation 3. If ESR exceeds the value from
Eq.4, multiple capacitors should be used in parallel.
Ceramic capacitor can be used in most of the applications.
In addition, both surface mount tantalum and through−hole
aluminum electrolytic capacitors can be used as well.
R1
FB
R2
Maximum Output Capacitor
NCP1597B family has internal 1 ms fixed soft−start and
overcurrent limit. It limits the maximum allowed output
capacitor to startup successfully. The maximum allowed
output capacitor can be determined by the equation:
Figure 3. Output divider
Di
p−p
Inductor Selection
Ilim(min) * Iload(max)
*
2
The inductor is the key component in the switching
regulator. The selection of inductor involves trade−offs
among size, cost and efficiency. The inductor value is
selected according to the equation 2.
(eq. 5)
Cout(max)
+
VoutńTSS(min)
Where T
is the minimum soft−start period (1ms);
SS(min)
D
iPP
is the current ripple.
Vout
Vout
This is assuming that a constant load is connected. For
example, with 3.3 V/2.0 A output and 20% ripple, the max
(eq. 2)
L +
@
ǒ
1 *
Ǔ
f @ Iripple
Vin(max)
allowed output capacitors is 90 mF.
Where V − the output voltage;
out
Input Capacitor Selection
f − switching frequency, 1.0 MHz;
I
− Ripple current, usually it’s 20% − 30% of output
The input capacitor can be calculated by Equation 6.
ripple
current;
V
1
Cin(min) + Iout(max) @ Dmax
@
− maximum input voltage.
(eq. 6)
in(max)
f @ Vin(ripple)
Choose a standard value close to the calculated value to
maintain a maximum ripple current within 30% of the
maximum load current. If the ripple current exceeds this
30% limit, the next larger value should be selected.
The inductor’s RMS current rating must be greater than
the maximum load current and its saturation current should
be about 30% higher. For robust operation in fault conditions
(start−up or short circuit), the saturation current should be
high enough. To keep the efficiency high, the series
resistance (DCR) should be less than 0.1 W, and the core
material should be intended for high frequency applications.
Where V
is the required input ripple voltage.
in(ripple)
Vout
+
Dmax
is the maximum duty cycle.
(eq. 7)
Vin(min)
Power Dissipation
The NCP1597B is available in a thermally enhanced
6−pin, DFN package that dissipates up to 1.0 W at T
+70°C. When the die temperature reaches +165°C, the
NCP1597B shuts down (see the Thermal−Overload
Protectionsection). The power dissipated in the device is the
sum of the power dissipated from supply current (PQ),
power dissipated due to switching the internal power
=
A
Output Capacitor Selection
The output capacitor acts to smooth the dc output voltage
and also provides energy storage. So the major parameter
necessary to define the output capacitor is the maximum
allowed output voltage ripple of the converter. This ripple is
related to capacitance and the ESR. The minimum
capacitance required for a certain output ripple can be
calculated by Equation 4.
MOSFET (P ), and the power dissipated due to the RMS
SW
current through the internal power MOSFET (PON). The
total power dissipated in the package must be limited so the
junction temperature does not exceed its absolute maximum
rating of +150°C at maximum ambient temperature.
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NCP1597B
Calculate the power lost in the NCP1597B using the
following equations:
ǒ
Ǔ
TJ + TC ) PTOTAL @ qJC
(eq. 15)
q
is the junction−to−case thermal resistance equal to
1.7°C/W. T is the temperature of the case and TJ is the
JC
1. High side MOSFET
C
The conduction loss in the top switch is:
junction temperature, or die temperature. The
case−to−ambient thermal resistance is dependent on how
well heat can be transferred from the PC board to the air.
Solder the underside−exposed pad to a large copper GND
plane. If the die temperature reaches +160°C the NCP1597B
shut down and does not restart again until the die
temperature cools by 40°C.
PHSON + I 2
RDS(on)HS
(eq. 8)
(eq. 9)
RMS_HSFET
Where:
2
DIPP
2
ǒI
Ǔ
IRMS_FET
+
)
D
Ǹ
out
12
DI is the peak−to−peak inductor current ripple.
Layout Consideration
PP
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1597B switch.
When operating at higher currents and input voltages, with
poor layout, this spike can generate voltages across the
NCP1597B that may exceed its absolute maximum rating.
A ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The FB component should be kept as far away as possible
from the switch node. The ground for these components
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
The power lost due to switching the internal power high side
MOSFET is:
ǒ
2
Ǔ
Vin @ Iout @ tr ) tf @ fSW
(eq. 10)
PHSSW
+
t and t are the rise and fall times of the internal power
r
f
MOSFET measured at SW node.
2. Low side MOSFET
The power dissipated in the top switch is:
PLSON + IRMS_LSFET 2 @ RDS(on)LS
(eq. 11)
(eq. 12)
Where:
2
DIPP
2
(
)
ǒI
Ǔ@ 1 * D
IRMS_LSFET
+
)
Ǹ
out
12
DI is the peak−to−peak inductor current ripple.
PP
The switching loss for the low side MOSFET can be
ignored.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1597B. This is
achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.
The power lost due to the quiescent current (IQ) of the device
is:
PQ + Vin @ IQ
IQ is the switching quiescent current of the NCP1597B.
PTOTAL + PHSON ) PHSSW ) PLSON ) PQ
(eq. 13)
(eq. 14)
Calculate the temperature rise of the die using the following
equation:
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8
NCP1597B
PACKAGE DIMENSIONS
DFN10 3x3, 0.5P
CASE 485C−01
ISSUE B
EDGE OF PACKAGE
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
L1
E
DETAIL A
Bottom View
PIN 1
(Optional)
REFERENCE
EXPOSED Cu
2X
0.15
C
MOLD CMPD
TOP VIEW
MILLIMETERS
2X
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
A3
(A3)
A3
b
D
0.20 REF
0.18
3.00 BSC
DETAIL B
0.10
0.08
C
C
0.30
A1
A
D2 2.40
2.60
DETAIL B
Side View
(Optional)
E
3.00 BSC
SEATING
PLANE
10X
E2 1.70
1.90
e
K
L
0.50 BSC
0.19 TYP
0.35
SIDE VIEW
A1
C
0.45
0.03
L1 0.00
D2
e
DETAIL A
10X
L
SOLDERING FOOTPRINT*
1
5
2.6016
E2
10X
K
10
6
1.8508
3.3048
2.1746
10X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NCP1597B/D
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