NCP145AMX100TCG [ONSEMI]

Very Low Dropout Bias Rail CMOS Voltage Regulator;
NCP145AMX100TCG
型号: NCP145AMX100TCG
厂家: ONSEMI    ONSEMI
描述:

Very Low Dropout Bias Rail CMOS Voltage Regulator

开关 光电二极管
文件: 总10页 (文件大小:279K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
NCP145  
500 mA, Very Low Dropout  
Bias Rail CMOS Voltage  
Regulator  
The NCP145 is a 500 mA VLDO equipped with NMOS pass  
transistor and a separate bias supply voltage (V ). The device  
BIAS  
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T
provides very stable, accurate output voltage with low noise suitable  
for space constrained, noise sensitive applications. In order to  
optimize performance for battery operated portable applications, the  
MARKING  
DIAGRAM  
NCP145 features low I consumption. The XDFN4 1.2 mm x 1.2 mm  
Q
1
package is optimized for use in space constrained applications.  
XXM  
XDFN4  
CASE 711BC  
Features  
1
Input Voltage Range: 1.0 V to 5.5 V  
Bias Voltage Range: 2.4 V to 5.5 V  
Fixed Voltage Versions Available  
Output Voltage Range: 1.0 V to 1.8 V (Fixed)  
XX = Specific Device Code  
M
= Date Code  
1.5% Accuracy over Temperature, 0.5% V  
@ 25°C  
OUT  
PIN CONNECTIONS  
UltraLow Dropout: Typ. 140 mV at 500 mA  
Very Low Bias Input Current of Typ. 80 mA  
IN  
4
3
EN  
Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA  
Logic Level Enable Input for ON/OFF Control  
Output Active Discharge Option Available  
GND  
5
Stable with a 2.2 mF Ceramic Capacitor  
OUT  
BIAS  
1
2
Available in XDFN4 1.2 mm x 1.2 mm x 0.4 mm Package  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
(Top View)  
Typical Applications  
Batterypowered Equipment  
Smartphones, Tablets  
Cameras, DVRs, STB and Camcorders  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 9 of this data sheet.  
V
BIAS  
>2.7 V  
NCP145  
GND  
100 nF  
BIAS  
IN  
V
OUT  
OUT  
1 V up to 500 mA  
V
1.5 V  
IN  
2.2 mF  
1 mF  
EN  
V
EN  
Figure 1. Typical Application Schematics  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
March, 2018 Rev. 1  
NCP145/D  
NCP145  
CURRENT  
LIMIT  
OUT  
IN  
ENABLE  
BLOCK  
EN  
BIAS  
UVLO  
150 W  
VOLTAGE  
REFERENCE  
+
THERMAL  
LIMIT  
*Active  
DISCHARGE  
GND  
*Active output discharge function is present only in NCP145AMXyyyTCG devices.  
yyy denotes the particular output voltage option.  
Figure 2. Simplified Schematic Block Diagram  
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2
NCP145  
PIN FUNCTION DESCRIPTION  
Pin No.  
XDFN4  
Pin Name  
Description  
1
2
OUT  
Regulated Output Voltage pin  
BIAS  
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage  
Lockout Circuit.  
3
EN  
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into  
shutdown mode.  
4
5
IN  
Input Voltage Supply pin  
Ground  
GND  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Symbol  
Value  
Unit  
V
Input Voltage (Note 1)  
V
IN  
0.3 to 6  
Output Voltage  
V
OUT  
0.3 to (V +0.3) 6  
V
IN  
Chip Enable, Bias Input  
V
V
0.3 to 6  
unlimited  
150  
V
EN, BIAS  
Output Short Circuit Duration  
Maximum Junction Temperature  
Storage Temperature  
t
s
SC  
T
J
°C  
°C  
V
T
55 to 150  
2000  
STG  
ESD Capability, Human Body Model (Note 2)  
ESD Capability, Machine Model (Note 2)  
ESD  
HBM  
ESD  
200  
V
MM  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.  
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:  
ESD Human Body Model tested per EIA/JESD22A114  
ESD Machine Model tested per EIA/JESD22A115  
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.  
THERMAL CHARACTERISTICS  
Rating  
Symbol  
Value  
Unit  
Thermal Characteristics, XDFN4 1.2 mm x 1.2 mm  
RqJA  
170  
°C/W  
Thermal Resistance, JunctiontoAir (Note 3)  
3. This data was derived by thermal simulations for a single device mounted on the 40 mm x 40 mm x 1.6 mm FR4 PCB with 2ounce 800 sq  
mm copper area on top and bottom.  
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3
 
NCP145  
ELECTRICAL CHARACTERISTICS 40°C T 85°C; V  
= 2.7 V or (V  
OUT J  
+ 1.6 V), whichever is greater, V = V  
+
J
BIAS  
OUT  
IN  
OUT(NOM)  
0.3 V, I  
= 1 mA, V = 1 V, unless otherwise noted. C = 1 mF, C  
= 2.2 mF. Typical values are at T = +25°C. Min/Max values are  
OUT  
EN  
IN  
for 40°C T 85°C unless otherwise noted. (Note 4)  
J
Parameter  
Test Conditions  
Symbol  
Min  
Typ  
Max  
Unit  
Operating Input Voltage  
Range  
V
IN  
V
+
5.5  
V
OUT  
DO  
V
Operating Bias Voltage  
Range  
V
(V  
+
5.5  
V
V
BIAS  
OUT  
1.40) 2.4  
Undervoltage Lockout  
V
Rising  
UVLO  
1.6  
0.2  
BIAS  
Hysteresis  
Output Voltage Accuracy  
Output Voltage Accuracy  
V
V
0.5  
%
%
OUT  
40°C T 85°C, V  
OUT(NOM)  
+ 0.3 V V ≤  
IN  
1.5  
+1.5  
J
OUT(NOM)  
OUT  
V
+ 1.0 V, 2.7 V or (V  
+
OUT(NOM)  
1.6 V), whichever is greater < V  
< 5.5 V,  
BIAS  
1 mA < I  
< 500 mA  
OUT  
V
V
Line Regulation  
V
+ 0.3 V V 5.0 V  
Line  
Line  
0.01  
0.01  
%/V  
%/V  
IN  
OUT(NOM)  
IN  
Reg  
Line Regulation  
2.7 V or (V  
greater < V  
+ 1.6 V), whichever is  
OUT(NOM)  
BIAS  
Reg  
< 5.5 V  
BIAS  
Load Regulation  
I
I
I
I
= 1 mA to 500 mA  
= 150 mA (Note 5)  
= 500 mA (Note 5)  
Load  
1.5  
37  
mV  
mV  
OUT  
OUT  
OUT  
OUT  
Reg  
V
IN  
Dropout Voltage  
V
V
V
75  
250  
1.5  
1000  
110  
1
DO  
140  
1.1  
800  
80  
DO  
DO  
CL  
V
BIAS  
Dropout Voltage  
= 500 mA, V = V (Note 5)  
BIAS  
V
mA  
mA  
mA  
mA  
V
IN  
OUT(NOM)  
Output Current Limit  
V
V
V
V
= 90% V  
= 2.7 V  
I
550  
0.9  
OUT  
BIAS  
Bias Pin Operating Current  
Bias Pin Disable Current  
Vinput Pin Disable Current  
EN Pin Threshold Voltage  
I
BIAS  
BIAS(DIS)  
0.4 V  
0.4 V  
I
0.5  
0.5  
EN  
EN  
I
1
VIN(DIS)  
EN Input Voltage “H”  
EN Input Voltage “L”  
V
EN(H)  
V
EN(L)  
0.4  
1
EN Pull Down Current  
V
= 5.5 V  
I
0.3  
mA  
ms  
EN  
EN  
ON  
TurnOn Time  
From assertion of V to V  
98% V  
=
t
215  
EN  
OUT  
. V  
= 1.2 V  
= 1.2 V,  
OUT(NOM)  
OUT(NOM) OUT(NOM)  
TurnOn Slew Rate  
V
V
0 V to 1.0 V, V  
SR  
PSRR(V  
15  
70  
80  
40  
mV/ms  
dB  
EN  
from 10 mV to 610 mV  
OUT  
Power Supply Rejection  
Ratio  
V
to V  
, f = 1 kHz, I  
= 150 mA,  
)
IN  
IN  
OUT  
OUT  
VIN V  
+0.5 V  
OUT  
V
to V  
OUT  
, f = 1 kHz, I  
= 150 mA,  
= 1.0 V,  
PSRR(V )  
BIAS  
dB  
BIAS  
VIN V  
OUT  
OUT  
+0.5 V  
Output Noise Voltage  
V
= V  
+0.5 V, V  
V
N
mV  
RMS  
IN  
OUT  
OUT(NOM)  
f = 10 Hz to 100 kHz  
Thermal Shutdown  
Threshold  
Temperature increasing  
Temperature decreasing  
160  
140  
150  
°C  
Output Discharge  
PullDown  
V
EN  
0.4 V, V  
= 0.5 V, NCP145A options  
R
DISCH  
W
OUT  
only  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T = 25°C.  
A
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.  
5. Dropout voltage is characterized when V  
falls 3% below V  
.
OUT  
OUT(NOM)  
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4
 
NCP145  
TYPICAL CHARACTERISTICS  
At T = +25°C, V = V  
+ 0.3 V, V  
= 2.7 V, V = V  
, V  
= 1.0 V, I  
= 500 mA,  
J
C
IN  
OUT(TYP)  
BIAS  
EN  
BIAS  
OUT(NOM)  
OUT  
= 1 mF, C  
= 0.1 mF, and C = 2.2 mF (effective capacitance), unless otherwise noted.  
IN  
BIAS  
OUT  
200  
180  
160  
140  
120  
100  
80  
200  
180  
I
= 100 mA  
OUT  
160  
+125°C  
+85°C  
140  
120  
100  
80  
40°C  
+125°C  
60  
+85°C  
60  
+25°C  
40°C  
40  
+25°C  
40  
20  
0
20  
0
0
100  
200  
300  
400  
500  
0.5 1.0  
1.5  
2.0  
2.5  
V  
3.0  
3.5  
4.0 4.5  
I
, OUTPUT CURRENT (mA)  
V
BIAS  
(V)  
OUT  
OUT  
Figure 3. VIN Dropout Voltage vs. IOUT and  
Temperature TJ  
Figure 4. VIN Dropout Voltage vs. (VBIAS  
V
OUT) and Temperature TJ  
300  
250  
200  
150  
100  
500  
450  
I
= 300 mA  
OUT  
I
= 500 mA  
OUT  
400  
350  
300  
250  
200  
150  
100  
+125°C  
+125°C  
+85°C  
+85°C  
+25°C  
+25°C  
40°C  
40°C  
50  
0
50  
0
0.5 1.0  
1.5  
2.0  
2.5  
V  
3.0  
3.5  
4.0  
4.5  
0.5 1.0  
1.5  
2.0  
2.5  
3.0  
(V)  
3.5  
4.0 4.5  
V
BIAS  
(V)  
V
V  
OUT  
BIAS OUT  
Figure 5. VIN Dropout Voltage vs. (VBIAS  
Figure 6. VIN Dropout Voltage vs. (VBIAS −  
V
OUT) and Temperature TJ  
V
OUT) and Temperature TJ  
140  
1500  
1400  
1300  
1200  
1100  
120  
100  
80  
+125°C  
+85°C  
+125°C  
40°C  
60  
+25°C  
+25°C  
40°C  
40  
+85°C  
1000  
900  
20  
0
0
50 100 150 200 250 300 350 400 450 500  
, OUTPUT CURRENT (mA)  
0
50  
100  
150  
200  
250  
300  
I
I
, OUTPUT CURRENT (mA)  
OUT  
OUT  
Figure 8. BIAS Pin Current vs. IOUT and  
Temperature TJ  
Figure 7. VBIAS Dropout Voltage vs. IOUT and  
Temperature TJ  
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5
NCP145  
TYPICAL CHARACTERISTICS  
At T = +25°C, V = V  
+ 0.3 V, V  
= 2.7 V, V = V  
, V  
= 1.0 V, I  
= 500 mA,  
J
C
IN  
OUT(TYP)  
BIAS  
EN  
BIAS  
OUT(NOM)  
OUT  
= 1 mF, C  
= 0.1 mF, and C = 2.2 mF (effective capacitance), unless otherwise noted.  
IN  
BIAS  
OUT  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
200  
180  
+125°C  
160  
140  
120  
100  
80  
+85°C  
+25°C  
+125°C  
40°C  
+85°C  
60  
+25°C  
40  
40°C  
100  
0
20  
0
2.0  
2.5  
3.0  
3.5  
4.0  
(V)  
4.5  
5.0  
5.5  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
V (V)  
V
BIAS  
V
BIAS  
OUT  
Figure 9. BIAS Pin Current vs. VBIAS and  
Temperature TJ  
Figure 10. Current Limit vs. (VBIAS VOUT)  
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6
NCP145  
TYPICAL CHARACTERISTICS  
At T = +25°C, V = V  
+ 0.3 V, V  
= 2.7 V, V = V  
, V  
OUT(NOM)  
= 1.0 V, I  
= 500 mA,  
J
IN  
OUT(TYP)  
BIAS  
EN  
BIAS  
OUT  
C
= 1 mF, C  
= 0.1 mF, and C  
= 2.2 mF (effective capacitance), unless otherwise noted.  
IN  
BIAS  
OUT  
V
OUT  
V
OUT  
t
R
= t = 1 ms  
F
t = t = 1 ms  
R F  
I
I
OUT  
OUT  
50 ms/div  
50 ms/div  
Figure 11. Load Transient Response,  
OUT = 50 mA to 500 mA, COUT = 10 mF  
Figure 12. Load Transient Response,  
IOUT = 50 mA to 500 mA, COUT = 2.2 mF  
I
V
OUT  
V
OUT  
t
R
= t = 1 ms  
F
t
R
= t = 1 ms  
F
I
OUT  
I
OUT  
500 ms/div  
500 ms/div  
Figure 13. Load Transient Response,  
OUT = 1 mA to 500 mA, COUT = 10 mF  
Figure 14. Load Transient Response,  
IOUT = 1 mA to 500 mA, COUT = 2.2 mF  
I
V
OUT  
V
OUT  
t
R
= t = 5 ms  
F
t
R
= t = 5 ms  
F
V
IN  
V
IN  
20 ms/div  
20 ms/div  
Figure 15. VIN Line Transient Response,  
IN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 10 mF  
Figure 16. VIN Line Transient Response,  
VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 2.2 mF  
V
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7
NCP145  
APPLICATIONS INFORMATION  
NCP145  
VBAT  
EN  
Switchmode DC/DC  
= 1.5 V  
1.0 V  
V
OUT  
BIAS  
OUT  
1.5 V  
LX  
FB  
IN  
IN  
LOAD  
GND  
EN  
Processor  
GND  
I/O  
I/O  
To other circuits  
Figure 17. Typical Application: LowVoltage DC/DC PostRegulator with ON/OFF Functionality  
The NCP145 dualrail very low dropout voltage regulator  
is using NMOS pass transistor for output voltage regulation  
or greater. Ceramic capacitors are recommended. For the  
best performance all the capacitors should be connected to  
the NCP145 respective pins directly in the device PCB  
copper layer, not through vias having not negligible  
impedance.  
When using small ceramic capacitor, their capacitance is  
not constant but varies with applied DC biasing voltage,  
temperature and tolerance. The effective capacitance can be  
much lower than their nominal capacitance value, most  
importantly in negative temperatures and higher LDO  
output voltages. That is why the recommended Output  
capacitor capacitance value is specified as Effective value in  
the specific application conditions.  
from V voltage. All the low current internal control  
IN  
circuitry is powered from the V  
voltage.  
BIAS  
The use of an NMOS pass transistor offers several  
advantages in applications. Unlike PMOS topology devices,  
the output capacitor has reduced impact on loop stability.  
Vin to Vout operating voltage difference can be very low  
compared with standard PMOS regulators in very low Vin  
applications.  
The NCP145 offers smooth monotonic start-up. The  
controlled voltage rising limits the inrush current.  
The Enable (EN) input is equipped with internal  
hysteresis. NCP145 Voltage linear regulator Fixed version  
is available.  
Enable Operation  
The enable pin will turn the regulator on or off. The  
threshold limits are covered in the electrical characteristics  
table in this data sheet. If the enable function is not to be used  
Dropout Voltage  
Because of two power supply inputs V and V  
and  
IN  
BIAS  
then the pin should be connected to V or V  
.
one V  
regulator output, there are two Dropout voltages  
IN  
BIAS  
OUT  
specified.  
The first, the V Dropout voltage is the voltage  
Current Limitation  
IN  
The internal Current Limitation circuitry allows the  
device to supply the full nominal current and surges but  
protects the device against Current Overload or Short.  
difference (V – V  
) when V  
OUT  
starts to decrease by  
IN  
OUT  
percent specified in the Electrical Characteristics table.  
is high enough; specific value is published in the  
V
BIAS  
Electrical Characteristics table.  
The second, V dropout voltage is the voltage  
Thermal Protection  
BIAS  
Internal thermal shutdown (TSD) circuitry is provided to  
protect the integrated circuit in the event that the maximum  
junction temperature is exceeded. When TSD activated , the  
regulator output turns off. When cooling down under the low  
temperature threshold, device output is activated again. This  
TSD feature is provided to prevent failures from accidental  
overheating.  
Activation of the thermal protection circuit indicates  
excessive power dissipation or inadequate heatsinking. For  
reliable operation, junction temperature should be limited to  
+125°C maximum.  
difference (V  
– V  
) when V and V  
pins are  
BIAS  
OUT  
IN  
BIAS  
joined together and V  
starts to decrease.  
OUT  
Input and Output Capacitors  
The device is designed to be stable for ceramic output  
capacitors with Effective capacitance in the range from  
2.2 mF to 10 mF. The device is also stable with multiple  
capacitors in parallel, having the total effective capacitance  
in the specified range.  
In applications where no low input supplies impedance  
available (PCB inductance in V and/or V  
inputs as  
IN  
BIAS  
example), the recommended C = 1 mF and C  
= 0.1 mF  
IN  
BIAS  
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8
NCP145  
ORDERING INFORMATION  
Device  
Nominal Output Voltage Marking  
Option  
Package  
Shipping†  
NCP145AMX100TCG  
NCP145AMX105TCG  
NCP145AMX120TCG  
1.00 V  
1.05 V  
1.20 V  
HE  
HG  
HD  
Output Active  
Discharge  
XDFN4  
(PbFree)  
3000 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-  
cifications Brochure, BRD8011/D.  
To order other package and voltage variants, please contact your ON Semiconductor sales representative  
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9
NCP145  
PACKAGE DIMENSIONS  
XDFN4 1.2x1.2, 0.8P  
CASE 711BC  
ISSUE O  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994.  
A
B
E
D
DETAIL B  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED TERMINAL  
AND IS MEASURED BETWEEN 0.15 AND  
0.20 mm FROM THE TERMINAL TIPS.  
4. COPLANARITY APPLIES TO THE EXPOSED  
PAD AS WELL AS THE TERMINALS.  
PIN ONE  
REFERENCE  
MILLIMETERS  
DETAIL B  
DIM MIN  
0.35  
A1 0.00  
MAX  
0.45  
0.05  
ALTERNATE  
A
TOP VIEW  
A3  
CONSTRUCTION  
A3  
b
0.13 REF  
SIDE VIEW  
A
0.25  
0.35  
0.25  
1.25  
0.68  
1.25  
0.68  
0.05  
C
C
b1 0.15  
1.15  
D2 0.58  
1.15  
E2 0.58  
4X  
(0.12)  
A1  
D
0.05  
4X (0.12)  
E
SEATING  
NOTE 4  
C
PLANE  
SIDE VIEW  
D2  
e
L
0.80 BSC  
0.25  
0.35  
0.23  
4X b  
L1 0.13  
M
0.05  
C A B  
e/2  
4X  
L
NOTE 3  
RECOMMENDED  
MOUNTING FOOTPRINT*  
e
1
2
DETAIL A  
E2  
L1  
4X  
C 0.195  
0.22  
PACKAGE  
OUTLINE  
1.50  
0.25  
3
4
b1  
BOTTOM VIEW  
DETAIL A  
4X  
0.35  
0.80 PITCH  
1
2X  
0.63  
4X  
0.48  
455  
DIMENSIONS: MILLIMETERS  
*For additional information on our PbFree strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
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NCP145/D  

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