NCL30086BHDR2G [ONSEMI]
Analog/Digital Dimmable Power Factor Corrected Quasi-Resonant PrimarySide Current-Mode Controller for LED Lighting;
| 型号： | NCL30086BHDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Analog/Digital Dimmable Power Factor Corrected Quasi-Resonant PrimarySide Current-Mode Controller for LED Lighting 驱动 光电二极管 接口集成电路 |
| 文件： | 总31页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30086BH
Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
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Controller for LED Lighting
The NCL30086BH is a controller targeting isolated and
non−isolated “smart−dimmable” constant−current LED drivers.
Designed to support flyback, buck−boost, and SEPIC topologies, its
proprietary current−control algorithm provides near−unity power
factor and tightly regulates a constant LED current from the primary
side, thus eliminating the need for a secondary−side feedback circuitry
or an optocoupler.
SOIC−10
CASE 751BQ
MARKING DIAGRAM
Housed in the SOIC10 which has the same body size as a standard
SOIC8, the NCL30086BH is specifically intended for very compact
space−efficient designs. The device is highly integrated with a
minimum number of external components. A robust suite of safety
protections is built in to simplify the design. To ensure reliable
operation at elevated temperatures, a user configurable current
foldback circuit is also provided. In addition, it supports analog and
PWM dimming with a dedicated dimming input intended to control
the average LED current.
Pin−to−pin compatible to the NCL30086, the NCL30086BH
provides the same benefits with in addition, an increased resolution of
the digital current−control algorithm for a 75% reduction in the LED
current quantization ripple.
L30086BH
ALYW
G
L30086BH = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
PIN CONNECTIONS
1
DIM
NC
Features
ZCD
VS
V
CC
• Quasi−resonant Peak Current−mode Control Operation
• Valley Lockout Optimizes Efficiency over the Line/Load Range
• Constant Current Control with Primary Side Feedback
• Tight LED Constant Current Regulation of 2% Typical
• Power Factor Correction
DRV
GND
CS
COMP
SD
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 29 of this data sheet.
• Analog or PWM dimming
• Line Feedforward for Enhanced Regulation Accuracy
• Low Start−up Current (10 mA typ.)
• Wide V Range
cc
♦ Current Sense (CS) Short Detection
♦ User programmable NTC Based Thermal Foldback
♦ Thermal Shutdown
• 300 mA / 500 mA Totem Pole Driver with 12 V Gate
Clamp
• Robust Protection Features
• −40 to 125°C Operating Junction Temperature
• Pb−Free, Halide−Free Product
♦ Brown−Out Detection
♦ OVP on V
♦ Programmable Over Voltage / LED Open Circuit
Protection
♦ Cycle−by−cycle Peak Current Limit
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
CC
Typical Applications
• Integral LED Bulbs
• LED Light Engines
• LED Driver Power Supplies
• Smart LED Lighting Applications
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
NCL30086BH/D
February, 2016 − Rev. 0
NCL30086BH
.
Aux
.
.
VDIM
NCL30086BH
1
2
3
4
5
10
9
8
7
6
R
sense
Figure 1. Typical Application Schematic in a Flyback Converter
.
Aux
.
VDIM
NCL30086BH
1
2
3
4
5
10
9
8
7
6
R
sense
Figure 2. Typical Application Schematic in a Buck−Boost Converter
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2
NCL30086BH
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
This pin is used for analog or PWM dimming control. An analog signal that can be
1
DIM
Analog / PWM Dimming
varied between V
LED current.
and V
or a PWM signal can be used to adjust the
DIM0
DIM100
2
3
ZCD
VS
Zero Crossing Detection
Input Voltage Sensing
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the input voltage rail for:
Power Factor Correction
Valley lockout
Brownout Detection
4
5
COMP
SD
Filtering Capacitor
This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.7 mF.
Thermal Foldback and
Shutdown
Connecting an NTC to this pin allows the user to program thermal current fold-
back threshold and slope. A Zener diode can also be used to pull−up the pin and
stop the controller for adjustable OVP protection.
6
7
8
9
CS
Current Sense
−
This pin monitors the primary peak current.
Controller ground pin.
GND
DRV
Driver Output
IC Supply Pin
The driver’s output to an external MOSFET
V
CC
This pin is the positive supply of the IC. The circuit starts to operate when V
CC
exceeds 18 V and turns off when V goes below 8.8 V (typical values). After
CC
start−up, the operating range is 9.4 V up to 26 V (V
minimum level).
CC(OVP)
10
NC
−
−
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3
NCL30086BH
Internal Circuit Architecture
Enable
STOP
V
V
REF
DD
Over Voltage Protection
(Auto−recovery or Latched)
Aux_SCP
OFF
VCC
UVLO
Latch
Fault
Management
VCC Management
Over Temp. Protection
(Auto−recovery or Latched)
Internal
Thermal
Shutdown
VCC_max
VCC Over Voltage
Protection
SD
Thermal
V
TF
Foldback
WOD_SCP
BO_NOK
FF_mode
DRV
V
VS
VCC
FF_mode
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
Aux_SCP
ZCD
Clamp
Circuit
Valley Selection
Frequency Foldback
Aux. Winding Short Circuit Prot.
DRV
S
Q
Q
CS_ok
V
VS
R
Line
feed−forward
DIM_disable
V
VS
V
REFX
STOP
GND
CS
Power Factor and
Constant−Current
Control
Leading
Edge
Blanking
CS_reset
Ipkmax
Maximum
on time
STOP
DIM_disable
t
on,max
COMP
Ipkmax
Max. Peak
Current
Limit
V
VS
BO_NOK
VS
Brown−Out
CS_ok
CS Short
Protection
V
REF
UVLO
t
on,max
DIM_disable
V
DIM
REFX
Dimming
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
control
V
TF
Figure 3. Internal Circuit Architecture
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NCL30086BH
Table 2. MAXIMUM RATINGS TABLE(S)
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 30
V
CC(MAX)
CC
I
Maximum current for V pin
Internally limited
mA
CC(MAX)
CC
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
DRV(MAX)
DRV
I
−300, +500
mA
DRV(MAX)
V
Maximum voltage on low power pins (except DRV and V pins)
−0.3, 5.5 (Notes 2 and 5)
−2, +5
V
MAX
CC
I
Current range for low power pins (except DRV and V pins)
mA
MAX
CC
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
180
150
°C/W
°C
θ
J−A
T
J(MAX)
−40 to +125
−60 to +150
3.5
°C
Storage Temperature Range
°C
ESD Capability, HBM model (Note 3)
ESD Capability, MM model (Note 3)
ESD Capability, CDM model (Note 3)
kV
V
250
2
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA.
5. Recommended maximum V voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V pin recommended range.
S
S
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V = 0 V,
ZCD
J
CC
V
CS
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
V
rising
rising
falling
V
V
16.0
8.2
8
18.0
8.8
−
20.0
9.4
−
CC
CC
CC
CC(on)
Minimum Operating Voltage
CC(off)
Hysteresis V
– V
V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset
V
4
5
6
V
Over Voltage Protection Threshold
V
25.5
26.8
28.5
V
CC
CC(OVP)
VCC(off)
V
V
noise filter
t
−
−
5
−
−
ms
CC(off)
noise filter
t
20
CC(reset)
VCC(reset)
Startup current
I
−
13
58
30
75
mA
mA
CC(start)
Startup current in fault mode
I
CC(Fault)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
0.8
–
1.0
2.6
3.0
1.2
4.0
4.5
CC
CC(off)
CC1
CC2
CC3
Device Enabled/No output load on DRV pin
Device Switching
F
= 65 kHz
sw
C
= 470 pF, F = 65 kHz
−
DRV
sw
CURRENT SENSE
Maximum Internal current limit
V
0.95
240
−
1.00
300
100
1.05
360
150
V
ILIM
LEB
ILIM
Leading Edge Blanking Duration for V
t
ns
ns
ILIM
Propagation delay from current detection to gate
off−state
t
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V = 0 V,
ZCD
J
CC
V
CS
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Maximum on−time
t
26
1.35
−
36
1.50
150
500
65
46
1.65
−
ms
V
on(MAX)
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for V
V
CS(stop)
t
ns
mA
mV
CS(stop)
BCS
Current source for CS to GND short detection
I
400
30
600
100
CS(short)
Current sense threshold for CS to GND short de-
tection
V
CS
rising
V
CS(low)
GATE DRIVE
Drive Resistance
DRV Sink
W
R
R
−
−
13
30
−
−
SNK
DRV Source
SRC
Drive current capability
DRV Sink (Note 6)
mA
I
−
−
500
300
−
−
SNK
DRV Source (Note 6)
I
SRC
Rise Time (10% to 90%)
Fall Time (90% to 10%)
DRV Low Voltage
C
C
= 470 pF
= 470 pF
t
–
–
8
40
30
–
−
−
−
ns
ns
V
DRV
r
t
DRV
f
V
= V
+0.2 V
CC(off)
V
CC
DRV(low)
C
C
= 470 pF, R
= 33 kW
DRV
DRV
DRV High Voltage
V
CC
= V
V
10
12
14
V
CC(MAX)
DRV(high)
= 470 pF, R
= 33 kW
DRV
DRV
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
Lower ZCD threshold voltage
ZCD hysteresis
V
rising
falling
V
−
35
15
−
90
55
−
150
−
mV
mV
mV
ns
ZCD
ZCD(rising)
V
ZCD(falling)
V
ZCD
V
−
ZCD(HYS)
Propagation Delay from valley detection to DRV
high
V
ZCD
falling
T
DEM
100
300
Blanking delay after on−time
Blanking delay at light load
Timeout after last DEMAG transition
Pulling−down resistor
V
> 30% V
< 25% V
T
T
1.12
0.56
5.0
−
1.50
0.75
6.5
1.88
0.94
8.0
−
ms
ms
ms
kW
REFX
REF
ZCD(blank1)
V
REFX
REF
ZCD(blank2)
T
TIMO
V
= V
R
200
ZCD
ZCD(falling)
ZCD(PD)
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at T = 25°C
V
245
250
255
mV
mV
mV
mV
−
J
REF
Reference Voltage T = 25°C to 100°C
V
REF
242.5 250.0 257.5
J
Reference Voltage T = −40°C to 125°C
V
REF
240
20
−
250
50
4
260
100
−
J
Current sense lower threshold
V
falling
V
CS(low)
CS
V
control
to current setpoint division ratio
V
I
ratio
Error amplifier gain
V
= V
G
40
50
60
mS
mA
REFX
REF
EA
EA
Error amplifier current capability
V
REFX
= V
(no dimming)
60
REF
V
REFX
= 25%* V
REF
240
COMP Pin Start−up Current Source
6. Guaranteed by Design
COMP pin grounded
I
140
mA
EA_STUP
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V = 0 V,
ZCD
J
CC
V
CS
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
LINE FEED FORWARD
to I conversion ratio
Test Condition
Symbol
Min
Typ
Max
Unit
V
VS
K
I
18
35
80
20
40
22
45
mS
mA
mA
CS(offset)
LFF
Line feed−forward current on CS pin
Offset current maximum value
DRV high, V = 2 V
VS
FF
I
100
120
offset(MAX)
VALLEY LOCKOUT SECTION
Threshold for high− line range (HL) detection
Threshold for low−line range (LL) detection
Blanking time for line range detection
FREQUENCY FOLDBACK
V
rising
falling
V
2.28
2.18
15
2.40
2.30
25
2.52
2.42
35
V
V
VS
HL
V
VS
V
LL
HL(blank)
t
ms
Minimum additional dead time in frequency fold-
back mode
t
1.4
2.0
40
2.6
ms
FF1LL
Additional dead time
V
V
= 5% V
= 0% V
t
t
−
−
−
ms
ms
REFX
REF
FF2HL
Additional dead time
90
REFX
REF
FF3HL
FAULT PROTECTION
Thermal Shutdown (Note 6)
Thermal Shutdown Hysteresis
F
SW
= 65 kHz
T
130
−
150
50
170
–
°C
°C
V
SHDN
T
SHDN(HYS)
Threshold voltage for output short circuit or aux.
winding short circuit detection
V
0.8
1.0
1.2
ZCD(short)
Short circuit detection Timer
Auto−recovery timer duration
SD pin Clamp series resistor
Clamped voltage
V
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD
ZCD(short)
t
recovery
R
1.6
1.35
2.50
30.0
85
kW
V
SD(clamp)
SD(clamp)
SD pin open
V
1.13
2.35
22.5
80
1.57
2.65
37.5
90
SD pin detection level for OVP
Delay before OVP or OTP confirmation
V
rising
V
OVP
V
SD
T
ms
mA
SD(delay)
OTP(REF)
Reference current for direct connection of an
NTC (Note 8)
I
Fault detection level for OTP (Note 7)
V
falling
rising
V
V
0.47
0.66
0.50
0.70
0.53
0.74
V
V
SD
OTP(off)
SD pin level for operation recovery after an OTP
detection
V
SD
OTP(on)
OTP blanking time when circuit starts operating
(Note 8)
t
250
0.94
0.64
370
1.06
0.74
ms
V
OTP(start)
SD pin voltage where thermal fold−back starts
V
V
R
1.00
0.69
TF(start)
TF(stop)
TF(start)
(V
REF
is decreased)
SD pin voltage at which thermal fold−back stops
V
(V
REF
is clamped to V
)
REF50
V
over I
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
T = +25°C to +125°C
10.8
7.4
5.4
7.5
11.7
8.1
5.9
8.1
12.6
8.8
6.4
8.7
kW
kW
kW
kW
TF(start)
TF(stop)
OTP(off)
OTP(on)
OTP(REF)
OTP(REF)
OTP(REF)
OTP(REF)
J
V
V
V
over I
over I
over I
T = +25°C to +125°C
J
R
R
R
TF(stop)
OTP(off)
OTP(on)
T = +25°C to +125°C
J
T = +25°C to +125°C
J
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V = 0 V,
ZCD
J
CC
V
CS
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD
J
CC
Description
FAULT PROTECTION
@ V = 600 mV (as percentage of V
Test Condition
Symbol
Min
Typ
Max
Unit
V
REFX
)
SD pin falling (no OTP
detection)
V
REF(50)
40
50
60
%
SD
REF
BROWN−OUT
Brown−Out ON level (IC start pulsing)
Brown−Out OFF level (IC shuts down)
BO comparators delay
V
rising
falling
V
0.95
0.85
1.00
0.90
30
1.05
0.95
V
V
S
BO(on)
V
S
V
BO(off)
t
t
ms
ms
nA
BO(delay)
BO(blank)
Brown−Out blanking time
15
50
25
35
V
S
pin Pulling−down Current
V = V
S
I
BO(bias)
250
450
BO(on)
DIMMING SECTION
DIM pin voltage for zero output current
(OFF voltage)
V
falling
rising
V
0.66
−
0.70
2.45
1.57
0.74
2.60
1.75
V
V
V
DIM
DIM0
DIM pin voltage for maximum output current
V
V
DIM100
DIM
(V
REFX
= V
)
REF
DIM pin voltage for 50% output current
(V = 125 mV)
V
rising or falling
V
DIM50
1.35
DIM
REFX
Dimming range
V
1.75
9.6
V
DIM(range)
Dimming pin pull−up current source
6. Guaranteed by Design
I
7.5
12
mA
DIM(pullup)
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30086BH
TYPICAL CHARACTERISTICS
20.0
19.5
19.0
18.5
18.0
17.5
17.0
9.4
9.3
9.2
9.1
9.0
8.9
8.8
8.7
8.6
8.5
8.4
16.5
16.0
8.3
8.2
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 4. VCC Start−up Threshold vs.
Temperature
Figure 5. VCC Minimum Operating Voltage vs.
Temperature
11.5
11.0
10.5
10.0
9.5
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
9.0
8.5
8.0
7.5
4.2
4.0
−50 −25
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 6. Hysteresis (VCC(on) − VCC(off)) vs.
Temperature
Figure 7. VCC(reset) vs. Temperature
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NCL30086BH
TYPICAL CHARACTERISTICS
28.0
27.8
40
35
30
25
20
15
10
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
26.0
5
0
25.8
25.6
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. VCC Over Voltage Protection
Threshold vs. Temperature
Figure 9. Start−up Current vs. Temperature
150
125
100
75
2.0
1.8
1.6
1.4
1.2
1.0
0.8
50
25
0
0.6
0.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. Start−up Current in Fault Mode vs.
Temperature
Figure 11. ICC1 vs. Temperature
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.6
1.4
1.2
1.5
1.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. ICC2 vs. Temperature
Figure 13. ICC3 vs. Temperature
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10
NCL30086BH
TYPICAL CHARACTERISTICS
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
400
380
360
340
320
300
280
260
240
220
200
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 14. Maximum Internal Current Limit vs.
Temperature
Figure 15. Leading Edge Blanking vs.
Temperature
150
140
130
120
110
100
90
50
48
46
44
42
80
40
38
36
34
70
60
50
40
30
20
10
0
32
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 16. Current Limit Propagation Delay vs.
Temperature
Figure 17. Maximum On−time vs. Temperature
1.60
1.58
1.56
1.54
1.52
1.50
1.48
220
210
200
190
180
170
160
150
140
130
120
1.46
1.44
1.42
1.40
1.38
110
100
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 18. VCS(stop) vs. Temperature
Figure 19. Leading Edge Blanking Duration for
CS(stop) vs. Temperature
V
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11
NCL30086BH
TYPICAL CHARACTERISTICS
600
580
560
540
520
500
480
460
440
100
90
80
70
60
50
40
30
20
420
400
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 20. ICS(short) vs. Temperature
Figure 21. VCS(low), VCS Rising vs.
Temperature
40
20
18
16
14
12
10
8
38
36
34
32
30
28
26
24
22
20
18
16
6
4
14
12
10
2
0
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 22. Sink Gate Drive Resistance vs.
Temperature
Figure 23. Source Gate Drive Resistance vs.
Temperature
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
5
0
5
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 24. Gate Drive Rise Time vs.
Temperature
Figure 25. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature
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12
NCL30086BH
TYPICAL CHARACTERISTICS
9.8
9.6
9.4
9.2
9.0
8.8
8.6
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
8.4
8.2
10.5
10.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 26. DRV Low Voltage vs. Temperature
Figure 27. DRV High Voltage vs. Temperature
150
140
130
120
110
100
90
80
75
70
65
60
55
50
45
40
80
70
60
50
35
30
40
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 28. Upper ZCD Threshold Voltage vs.
Temperature
Figure 29. Lower ZCD Threshold vs.
Temperature
50
45
40
35
30
25
20
15
10
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−50 −25
5
0
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 30. ZCD Hysteresis vs. Temperature
Figure 31. ZCD Blanking Delay vs.
Temperature
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13
NCL30086BH
TYPICAL CHARACTERISTICS
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
256
255
254
253
252
251
250
249
248
247
246
6.0
5.8
−50 −25
245
244
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 32. ZCD Time−out vs. Temperature
Figure 33. Reference Voltage vs. Temperature
110
100
90
60
58
56
54
52
50
48
80
70
60
50
40
46
30
44
42
20
10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 34. Current Sense Lower Threshold
(VCS Falling) vs. Temperature
Figure 35. Error Amplifier Trans−conductance
Gain vs. Temperature
22.0
21.5
21.0
44
43
42
41
40
39
38
20.5
20.0
19.5
19.0
18.5
18.0
37
36
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 36. Feedforward VVS to ICS(offset)
Conversion Ratio vs. Temperature
Figure 37. Line Feedforward Current on CS
Pin (@ VVS = 2 V) vs. Temperature
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14
NCL30086BH
TYPICAL CHARACTERISTICS
120
115
110
105
100
95
2.55
2.50
2.45
2.40
2.35
90
2.30
2.25
85
80
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 38. Ioffset(MAX) vs. Temperature
Figure 39. Threshold for High−line Range
Detection vs. Temperature
40
38
36
34
32
30
28
26
24
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
22
20
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 40. Threshold for Low−line Range
Detection vs. Temperature
Figure 41. Blanking Time for Low−line Range
Detection vs. Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
115
110
105
100
95
90
85
0.85
0.80
80
75
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 42. Threshold Voltage for Output Short
Circuit Detection vs. Temperature
Figure 43. Short Circuit Detection Timer vs.
Temperature
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15
NCL30086BH
TYPICAL CHARACTERISTICS
5.00
4.75
4.50
4.25
4.00
3.75
3.50
2.20
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
3.25
3.00
1.10
1.00
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 44. Auto−recovery Timer Duration vs.
Temperature
Figure 45. SD Pin Clamp Series Resistor vs.
Temperature
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
1.15
1.10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 46. SD Pin Clamp Voltage vs.
Temperature
Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature
38
36
34
32
30
28
26
91
90
89
88
87
86
85
84
83
82
81
24
22
80
79
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 48. TSD(delay) vs. Temperature
Figure 49. IOTP(REF) vs. Temperature
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16
NCL30086BH
TYPICAL CHARACTERISTICS
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
11.4
11.3
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
7.6
11.2
11.1
11.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 50. RTF(start) vs. Temperature
Figure 51. RTF(stop) vs. Temperature
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
7.8
7.7
7.6
5.5
5.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 52. ROTP(off) vs. Temperature
Figure 53. ROTP(on) vs. Temperature
55
54
53
52
51
50
49
48
47
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
46
45
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 54. Ratio VREF(50) over VREF vs.
Temperature
Figure 55. Brown−out ON Level vs.
Temperature
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17
NCL30086BH
TYPICAL CHARACTERISTICS
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
0.86
0.85
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 56. Brown−out OFF Level vs.
Temperature
Figure 57. Brown−out Blanking Time vs.
Temperature
500
450
400
350
300
250
200
150
100
50
0
−50 −25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
Figure 58. VS Pin Pulling−down Current vs.
Temperature
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18
NCL30086BH
Application Information
The NCL30086BH is a driver for power−factor corrected
and second temperature thresholds depend on the
NTC connected to the circuit SD pin. The SD pin
can also be used to shutdown the device by pulling
flyback and non−isolated buck−boost/ SEPIC converters. It
implements a current−mode, quasi−resonant architecture
including valley lockout and frequency fold−back
capabilities for maintaining high−efficiency performance
over a wide load range. A proprietary circuitry ensures both
accurate regulation of the output current (without the need
for a secondary−side feedback) and near−unity power factor
correction. The circuit contains a suite of powerful
protections to ensure a robust LED driver design without the
need of extra external components or overdesign
this pin below the V
min level. A Zener
OTP(off)
diode can also be used to pull−up the pin and stop
the controller for adjustable OVP protection. When
triggered, both protections lead the controller to stop
operating for the 4−s auto−recovery time.
♦ Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
V , the MOSFET is immediately turned off.
ILIM
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30086BH optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For a stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below 2%
are typically obtained.
♦ Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller for the 4−s
auto−recovery time if it exceeds 150% x VILIM for
4 consecutive cycles. This feature can protect the
converter if a winding is shorted or if the output
diode is shorted or simply if the transformer
saturates.
♦ Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation for the 4−s
auto−recovery time.
♦ Open LED protection: if the V pin voltage
CC
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
♦ Floating or Short Pin Detection: NCL30086BH
protections aid in pass safety tests. For instance, the
circuit stops operating when the CS pin is grounded
or open.
• Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
• Main protection features:
♦ Over Temperature Thermal Fold−back/
Shutdown/Over Voltage Protection: the
Power Factor and Constant Current Control
The NCL30086BH embeds an analog/digital block to
control the power factor and regulate the output current by
NCL30086BH features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. If the
monitoring the ZCD, V and CS pin voltages (signals ZCD,
S
V and V of Figure 59). This circuitry generates the
S
CS
temperature continues to rise after this point to a
second level, the controller stops operating. This
mode would only be expected to be reached under
normal conditions if there is a severe fault. The first
current setpoint (V
current sense signal (V ) to dictate the MOSFET turning
/4) and compares it to the
CONTROL
CS
off event when V exceeds V
/4.
CONTROL
CS
V
V
VS
ZCD STOP
REF
PWM Latch reset
V
Power Factor and
Constant−Current
Control
CS
COMP
DIM_disable
C1
Figure 59. Power Factor and Constant−Current Control
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19
NCL30086BH
Start−up Sequence
The V pin provides the sinusoidal reference necessary
S
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
for shaping the input current. The obtained current reference
is further modulated so that when averaged over a half−line
the time to charge the V capacitor, initiate startup and
period, it is equal to the output current reference (V
).
CC
REFX
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string. To
speed−up this phase, the following defines the start−up
sequence:
This averaging process is made by an internal Operational
Trans−conductance Amplifier (OTA) and the capacitor
connected to the COMP pin (C1 in Figure 59). Typical
COMP capacitance is 2.2 mF and should not be less than 1 mF
to ensure stability. The COMP ripple does not affect the
power factor performance as the circuit digitally eliminates
it when generating the current setpoint.
• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the V pin
S
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
If the V pin properly conveys the sinusoidal shape, power
S
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low, especially if the output voltage ripple is
small. In any case, the output current will be well regulated
following the equation below:
VREFX
2NPSRsense
(eq. 1)
Iout
+
Where:
• N is the secondary to primary transformer turns N
PS
PS
• If V drops below the V
threshold because the
CC
CC(off)
= N / N
S
P
circuit fails to start−up properly on the first attempt, a
new attempt takes place as soon as V is recharged to
• R
• V
V
is the current sense resistor (see Figure 1).
is the output current internal reference. V
(250 mV, typically) at full load.
sense
REFX
CC
=
V . The COMP voltage is not reset at that
CC(on)
REFX
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
REF
The output current reference (V
) is V
unless
REFX
REF
thermal fold−back is activated by the SD pin voltage being
reduced below 1 V typical (see “protections” section) or
• If the load is shorted, the circuit will operate in hiccup
mode with V oscillating between V
and
unless the DIM pin voltage is below V
dimming section).
(see analog
CC
CC(off)
DIM100
V
CC(on)
until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The AUX_SCP protection forces the 4−s
auto−recovery delay to reduce the operation duty−ratio.
Figure 60 illustrates a start−up sequence with the output
shorted to ground.
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
www.onsemi.com
20
NCL30086BH
VCC(on)
VCC
VCC(off)
‧‧‧
( )
‧‧‧
( )
time
time
AUX_SCPtrips
as t1 + t2 + t3 = tOVLD
t
(
^90 ms
)
DRV
OVLD
t1
t3
t1
t3
t2
t2
trecovery ^4 s
trecovery ^4 s
(
)
(
)
Figure 60. Start−up Sequence in a Load Short−circuit Situation
Zero Crossing Detection Block
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
situation, the NCL30086BH features a time−out circuit that
generates pulses if the voltage on ZCD pin stays below the
55−mV threshold for 6.5 ms nominal. The time−out also acts
as a substitute clock for the valley detection and simulates
a missing valley in case the free oscillations are too damped.
55−mV internal threshold (V
). At startup or in case
ZCD(TH)
of extremely damped free oscillations, the ZCD comparator
may not be able to detect the valleys. To avoid such a
www.onsemi.com
21
NCL30086BH
t
ZCD(blank1)
ZCD(blank2)
t
ZCD(blank)
FF_mode
t
ZCD
+
−
V
ZCD(TH)
Clock
Time−Out
+
−
+
−
V
ZCD(short)
S
Aux_SCP
Q
Q
90−ms Timer
R
4−s Auto−Recovery Timer
Figure 61. Zero Current Detection Block
www.onsemi.com
22
NCL30086BH
If the ZCD pin or the auxiliary winding happen to be
• After the appropriate number of “clock” pulses in
shorted, the time−out function would normally make the
controller keep switching and hence lead to improper LED
current value. The “AUX_SCP” protection prevents such a
stressful operation: a secondary timer starts counting that is
thermal foldback or dimming mode
For an optimal operation, the maximum ZCD level
should be maintained below 5 V to stay safely below the
built in clamping voltage of the pin.
only reset when the ZCD voltage exceeds the V
ZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no
ZCD voltage pulse having exceeded V for this time
Line Range Detection
As sketched in Figure 62, this circuit detects the low−line
ZCD(short)
period), the controller detects a fault and stops operation for
4 seconds.
The “clock” shown in Figure 61 is used by the “valley
selection frequency foldback” circuitry of the block diagram
(Figure 3), to generate the next DRV pulse (if no fault
prevents it):
range if the V pin remains below the V threshold (2.3 V
S
LL
typical) for more than the 25−ms blanking time. High−line
is detected as soon as the V pin voltage exceeds V (2.4 V
S
HL
typical). These levels roughly correspond to 184−V rms and
192−V rms line voltages if the external resistors divider
applied to the V pin is designed to provide a 1−V peak value
S
at 80 V rms.
• Immediately when the clock occurs in QR mode at low
line or valley 2 at high line (full load)
Figure 62. Line Range Detection
In the low−line range, conduction losses are generally
dominant. Adding a dead−time would further increase these
losses. Hence, only a short dead−time is necessary to reach
the MOSFET valley. In high−line conditions, switching
losses generally are the most critical. It is thus efficient to
skip one valley to lower the switching frequency. Hence,
under normal operation, the NCL30086BH optimizes the
efficiency over the line range by turning on the MOSFET at
the first valley in low−line conditions and at the second
valley in the high−line case. This is illustrated by Figure 63
that sketches the MOSFET Drain−Source voltage in both
cases. In the event that thermal foldback is activated,
additional valleys can be skipped as the power is reduced.
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line
(right)
Line Feedforward
To compensate for current regulation errors due to AC line
variation, the NCL30086BH includes a method to add line
feedforward adjustment. As illustrated by Figure 64, the
current. By adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset proportional
to the input voltage is added to the CS signal for the
MOSFET on−time.
input voltage is sensed by the V pin and converted into a
S
www.onsemi.com
23
NCL30086BH
Bulk rail
vDD
VS
CS
RCS
ICS(offset)
Rsense
Q_drv
Figure 64. Line Feed−Forward Schematic
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
PWM or Linear Dimming Detection
The DIM pin of the NCL30086BH is provided to
implement linear and/or PWM dimming of the LED current.
Where:
• N is the secondary to primary transformer turns
PS
Applying a voltage on the DIM pin voltage (V ) forces
DIM
NPS + NSńNP
the output current internal reference to operate in one of
three regions:
• R
• V
is the current sense resistor (see Figure 1).
sense
is the output current internal reference (250 mV
VREFX + 0
if VDIM v VDIM0
REF
typically)
(eq. 2)
VREFX + VREF
if VDIM w VDIM100
• I
is the full−load output current.
out,nom
The DRV output is disabled whenever the DIM pin
VDIM * VDIM0
VDIM100 * VDIM0
VREFX
+
VREF
otherwise
voltage is lower than V
is maximal when V
dimming, a PWM signal with a low−state value below
and the output current setpoint
DIM0
exceeds V
. Thus, for PWM
DIM
DIM100
V
DIM0
and V
respectively, are 0.7 V and 2.45 V
DIM100
typically.
V
DIM0
and a high−state value above V
should be
DIM100
The output current can then be controlled by the DIM pin
as follows:
applied.
In this case, the output current will be:
Iout + 0
if VDIM v VDIM0
(eq. 3)
Iout ^ Iout,nom @ d
(eq. 4)
VREF
2 NPSRsense
Iout + Iout,nom
+
if VDIM w VDIM100
Where d is the duty ratio of the DIM pin signal.
VDIM * VDIM0
VDIM100 * VDIM0
Iout
+
Iout,nom
otherwise
VDIM
VDIM100
VDIM0
time
Iout
Iout,nom
0 A
time
Figure 65. Pin DIM Chronograms
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24
NCL30086BH
Notes:
• The current does not immediately reach its new target
value when the PWM dimming signal state changes due
to system time constants like the time necessary to
charge or discharge the output capacitor to the required
level. The output current settling time can hence affect
the obtained output current, particularly if the PWM
signal frequency is high.
• If either the high−state (V
) or low−state level
DIM(high)
(V
) of the input or both are between V
and
DIM(low)
DIM0
V
DIM100
, the output current will be proportionally
reduced as both analog and PWM dimming are
simultaneous active, thus the output current will be:
VDIM(high) * VDIM0
VDIM100 * VDIM0
VDIM(low) * VDIM0
VDIM100 * VDIM0
Iout
^
ǒ
d )
(1 * d) Iout,nom if VDIM0 v VDIM(low) v VDIM(high) v VDIM100
Ǔ
VDIM(high) * VDIM0
VDIM100 * VDIM0
Iout
^
^
d @ Iout,nom
if VDIM0 v VDIM(high) v VDIM100 and VDIM(low) v VDIM0
VDIM(low) * VDIM0
Iout
ǒ
d )
(1 * d)
Ǔ
Iout,nom
if VDIM(high) w VDIM100 and VDIM0 v VDIM(low) v VDIM100
VDIM100 * VDIM0
Protections
• If thermal foldback is activated as well, the current
reduction is cumulative. For instance, if the DIM pin
voltage and the thermal foldback respectively, reduces
the output current setpoint by 50% and 20%
The circuit incorporates a full suite of protection features
listed below to make the LED driver very rugged.
Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage
remains below V
respectively, the output current will be 80%*50% that is
40% of its nominal level.
for 90 ms. In such a situation, the
ZCD(short)
The DIM pin is pulled up internally by a 10−mA current source.
Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture
there will be a component of line ripple (100 / 120 Hz) on the
output. If PWM dimming is used, it is recommended to
select the dimming frequency to be sufficiently high not to
generating beat frequencies that could create optical
artifacts.
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed.
Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
up in a very abrupt manner. The V
comparator (current
ILIM
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time, a current rise > 50%
>> As a general rule, the minimum PWM frequency
should be at least 2.5x the line ripple frequency and not
be set near multiples of the line frequency.
of the nominal maximum value set by V
is possible. As
ILIM
illustrated in Figure 66, an additional circuit monitors for
this current overshoot to detect a winding short circuit. The
leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
exceed (V
= 150% * V ), the controller enters the
ILIM
CS(stop)
auto−recovery mode (4−s operation interruption between
active bursts.)
www.onsemi.com
25
NCL30086BH
S
Q
Q
DRV
R
CS
LEB1
+
−
PWMreset
+
−
STOP
Ipkmax
UVLO
BONOK
V
ILIMIT
TSD
SD Pin OVP
(OVP2)
LEB2
+
−
WOD_SCP
4−pulse
counter
OTP
S
OFF
V
Q
Q
AUX_SCP
VCC(ovp)
CS(stop)
R
4−s auto−recovery timer
Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
VCC Over Voltage Protection
Programmable Over Voltage Protection (OVP2)
The circuit stops generating pulses if V
exceeds
In addition to the V OVP protection, it is possible to
CC
CC
V
and enters auto−recovery mode. This feature
connect a Zener diode between V
and the SD pin to
CC(OVP)
CC
protects the circuit in the event that the output LED string is
disconnected or an individual LED in the string happens to
fail open.
implement programmable V
Figure 67). The triggering level is (V +V
the 2.5−V internal threshold. If this protection trips, the circuit
enters the auto−recovery mode.
OVP monitoring (D of
CC
Z
) where V
is
Z
OVP
OVP
www.onsemi.com
26
NCL30086BH
Vdd
I
OTP(REF)
SD Pin OVP (OVP2) DETECTION
+
−
VCC
V
OVP
T
SD(delay)
D
Z
SD
S
Q
Q
OFF
OTP DETECTION
−
NTC
+
R
T
OTP(start)
V
/ V
OTP(on)
OTP(off)
4−s
auto−recovery
Timer
V
TF
Thermal
Foldback
Rclamp
Vclamp
Figure 67. Thermal Foldback and OVP/OTP Circuitry
www.onsemi.com
27
NCL30086BH
The SD pin is clamped to about 1.35 V (V
) through
clamp
a 1.6−kW resistor (R
). It is then necessary to inject about
clamp
VOVP * Vclamp
ǒ Ǔ
Rclamp
that is
2.50 * 1.35
ǒ
^ 700 mAǓ
1.6 k
typically, to trigger the OVP protection. This current helps
ensure an accurate detection by using the Zener diode far
from its knee region.
Programmable Over Temperature Foldback Protection
(OTP)
Connect an NTC between the SD pin and ground to detect
an over−temperature condition. In response to a high
Figure 68. Output Current Reduction versus SD
Pin Voltage
temperature (detected if V drops below V
), the
At startup, when V
reaches V , the OTP
CC(on)
SD
TF(start)
CC
circuit gradually reduces the LED current down to 50% (>
comparator is blanked for at least 180 ms which allows the
SD pin voltage to reach its nominal value if a filtering
capacitor is connected to the SD pin. This avoids flickering
of the LED light during turn on.
50% reduction in output power) of its initial value when V
SD
reaches V , in accordance with the characteristic of
TF(stop)
Figure 68 (Note 9).
At this point, if the temperature continues to rise and the
Brown−Out Protection
secondary OTP level is reached, (V drop below V ), the
SD
OTP
The NCL30086BH prevents operation when the line
voltage is too low for proper operation. As sketched in
circuit enters auto−recovery mode and cannot resume
operation until V exceeds V to provide some
temperature hysteresis (around 10°C typically). The OTP
thresholds nearly correspond to the following resistances of the
NTC:
SD
OTP(on)
Figure 69, the circuit detects a brown−out situation if the V
S
pin remains below the V
threshold (0.9 V typical) for
BO(off)
more than the 25−ms blanking time. In this case, the
controller stops operating. Operation resumes as soon as the
• Thermal foldback starts when R
(11.7 kW, typically)
≤ R
NTC
TF(start)
V pin voltage exceeds V
(1.0 V typical) and V is
S
BO(on)
CC
higher than V
. To ease recovery, the circuit overrides
CC(on)
• Thermal foldback stops when R
typically)
≤ R
(8.0 kW,
NTC
TF(stop)
the V normal sequence (no need for V cycling down
CC
CC
below V ). Instead, its consumption immediately
CC(off)
• OTP triggers when R
≤ R
(5.9 kW, typically)
(8.0 kW,
NTC
OTP(off)
reduces to I
so that V
rapidly charges up to
CC(start)
CC
• OTP is removed when R
≤ R
OTP(on)
V
CC(on)
and the circuit re−starts operation.
NTC
typically)
Figure 69. Brown−out Circuit
9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if PWM or
analog dimming is not engaged or a lower one based on the dimming value.
www.onsemi.com
28
NCL30086BH
Die Over Temperature (TSD)
Fault Management
The circuit stops operating if the junction temperature (T )
J
OFF Mode
exceeds 150°C typically. The controller remains off until T
J
The circuit turns off in the case of an incorrect feeding of the
circuit: “UVLO high”. The UVLO signal becomes high
when VCC drops below VCC(off) and remains high until
VCC exceeds VCC(on).
The circuit also turns off whenever a major faulty
condition prevents it from operating:
goes below nearly 100°C.
Pin Connection Faults
The circuit addresses most pin connection fault cases:
• CS Pin Short to Ground
The circuit senses the CS pin impedance every time it
starts−up and after DRV pulses terminated by the 36−ms
maximum on−time. If the measured impedance does
not exceed 120 W typically, the circuit stops operating.
In practice, it is recommended to place a minimum of
250 W in series between the CS pin and the current
sense resistor to take into account parasitics.
• Severe OTP (V level below VOTP(off)
)
SD
• V OVP
CC
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
In this mode, the DRV pulses generation is interrupted.
In the case of a latching−off fault, the circuit stops pulsing
• Fault of the GND Connection
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the V
CC
capacitor, flows out of the GND pin to return to the
negative terminal of the V capacitor. If the GND pin
CC
until the LED driver is unplugged and V drops below
CC
is not connected, the circuit ESD diodes offer another
return path. The accidental non−connection of the GND
pin is monitored by detecting that one of the ESD diode
is conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
V
. At that moment, the circuit resumes operation.
CC(reset)
In the auto−recovery case, the circuit cannot generate
DRV pulses for the auto−recovery 4−s delay. When this time
has elapsed, the circuit recovers operation as soon as the
V
CC
voltage has exceeded V
. All these protections are
CC(on)
auto−recovery.
More generally, incorrect pin connection situations
(open, grounded, shorted to adjacent pin) are covered by
ANDxxxx.
ORDERING INFORMATION
Device
Package Type
SOIC−8
Shipping
NCL30086BHDR2G
2500 / Tape & Reel
(Pb−Free/Halide Free)
www.onsemi.com
29
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ
ISSUE B
10
1
DATE 26 NOV 2013
SCALE 1:1
2X
NOTES:
0.10
C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
D
H
A
2X
0.10
C A-B
F
10
6
E
1
5. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
5
L2
A3
L
SEATING
PLANE
C
0.20
C
10X b
DETAIL A
B
2X 5 TIPS
M
MILLIMETERS
0.25
C A-B D
DIM MIN
MAX
1.75
0.25
0.25
0.51
5.00
4.00
TOP VIEW
A
A1
A3
b
D
E
1.25
0.10
0.17
0.31
4.80
3.80
10X
h
X 45
_
0.10
C
0.10
C
M
e
1.00 BSC
H
h
5.80
0.37 REF
6.20
A
L
L2
M
0.40
0
0.80
0.25 BSC
DETAIL A
e
SIDE VIEW
A1
SEATING
PLANE
C
8
_
_
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
10
1.00
PITCH
10X
0.58
XXXXX
ALYWX
G
1
XXXXX = Specific Device Code
6.50
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
1
10X
1.18
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52341E
SOIC−10 NB
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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