NCL30095ADR2G [ONSEMI]
LED 驱动器，AC-DC 功率因数校正升压开关稳压器，集成式 MOSFET，三端双向可控硅调光，温度折回;
| 型号： | NCL30095ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | LED 驱动器，AC-DC 功率因数校正升压开关稳压器，集成式 MOSFET，三端双向可控硅调光，温度折回 开关 驱动 功率因数校正 驱动器 稳压器 可控硅 |
| 文件： | 总23页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30095A
Power Factor Corrected
LED Boost Switching
Regulator
The NCL30095A high power factor boost PWM switching
regulator is designed to regulate the average current through a string of
LEDs. The circuit operates in Critical Conduction Mode (CrM) based
on a proven constant on−time control scheme to achieve near unity
power factor. In addition to regulating a constant current, the
switching regulator is optimized to support leading and trailing edge
phase dimming applications. When a dimmer is detected on the AC
input, an internal voltage reference of the current regulation loop
adjusts the current level based on the dimmer conduction angle so the
current through the LED string has a desired value based on a
programmed dimming curve. The shape of the dimming curve is
intended to emulate the response of an incandescent bulb while
achieving NEMA SSL6 and NEMA SSL7A recommendations.
An integrated HV MOSFET in a cascoded configuration supports
biasing the controller during operation and eliminates the need for an
auxiliary winding to provide bias power. A robust suite of protection
features is included to ensure proper handling of expected fault
conditions without the need for extra circuitry and a dedicated thermal
fold−back input proves gradually reduction of the current above a user
defined set−point.
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14
1
SOIC−14 NB (LESS PIN 4)
CASE 751DY
MARKING DIAGRAM
14
L30095AG
AWLYWW
1
L30095A = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
WL
Y
WW
G
General Features
• Near−Unity Power Factor
PIN CONNECTIONS
• Critical Conduction Mode (CrM)
• Constant On−time Control
1
14
Drain
Drain
Drain
Gate
Source
CS1
• Accurate Current Regulation (+/− 2% typical)
• Compatible with Leading and Trailing Edge Phase Controlled
Dimmers
GND
• Fast Startup Time (< 100 ms typical)
V
CC
COMP
ACC_TH
TF
• Integrated ZCD Detection
CS2
OVP
• User Programmable Thermal Current Fold−back
• Vcc Operation up to 18 V
7
8
(Top View)
Safety Features
• Output Overvoltage Protection
• Cycle−by−Cycle Current Limiting
• Vcc UVLO
ORDERING INFORMATION
†
Device
Package
Shipping
Typical Applications
• LED Bulbs
• LED Downlights
• LED Light Engines
• LED Modules
NCL30095ADR2G SOIC−14
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
September, 2017 − Rev. 1
NCL30095A/D
NCL30095A
V
in
Vout
L1
D1
R0L
AC_L
FZ
Cx
Rx
Rovp_top
D
C
in
Rcasc
L0L
Racc_top
1
2
3
14
13
12
11
10
9
DRAIN
DRAIN
DRAIN
GATE
SOURCE
CS1
Cout
R0N
AC_N
Racc_bot
D2
GND
VCC
CS2
Ccasc
5
6
7
L0N
Dz
casc
COMP
Ccomp
ACC_TH
TF
c
8
OVP
Ccc
RNTC
RTF
Figure 1. NCL30095A Application Schematic
Table 1. PIN FUNCTION DESCRIPTION
Pin No. Pin Name
Function
Pin Description
The Drain of the High Voltage NMOS.
Feedback loop compensation pin of the IC.
1, 2, 3
DRAIN
COMP
Drain of HV switch
Compensation
5
6
ACC_TH
Diming Detection Input
This pin receives a portion of the AC input voltage. It is compared to an inter-
nal reference voltage in order to determine the presence of a dimmer state
and the phase angle.
7
8
9
TF
Thermal Fold−back
Connecting an NTC to this pin allows linear reduction of the output current
above a user programmed temperature set−point.
OVP
CS2
Over−Voltage Protection Input
This pin receives a portion of the Boost output voltage V and serves to
OUT
trigger an OVP fault in the event the LED string is open.
nd
2
Current Sense Input
This pin monitors the LED load current across the R
resistor during the
sense2
off time. This pin is used to monitor the instantaneous load current for regula-
tion loop, and to determine when the Zero Current Detection (ZCD) point is
reached.
10
VCC
V
CC
Input
This positive supply pin accepts up to 18 Vdc. The supply for the device is
ensured by the external diode from the source pin.
11
12
GND
CS1
−
The switching regulator ground
st
1
Current Sense Input
This pin monitors the inductor current across the R
on−time. This pin monitors the maximum current cycle by cycle.
resistor during the
sense1
13
14
SOURCE
GATE
Source of HV Switch
Gate of HV Switch
The Source of the High Voltage NMOS. Connect the external diode between
the source and VCC pin to provide the IC supply.
The Gate of the High Voltage NMOS. External circuitry is used to bias this pin
to 20V.
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NCL30095A
Simplified Internal Block Schematic
GATE
Vdd
DRAIN
SOURCE
CS1
OVP_CMP
HV MOS
OVP
20 us
Filter
Vdd
LV MOS
DRV
OVP
VCC
CLK
UVP_CMP
Latch
Set
Q
UVPstop
IC stop
PWM
RST
ILIM_MIN
Reset
Qb
OCP_RST
UVLO_CMP
UVLO
IC stop
Latch
TSD
Ilimit_CMP
Vdd reg
TSD
ON_CMP
Vdd
VccON
WindShort
CS1fault
CS2fault
Ilimit_MIN_CMP
LEB 250ns
PowerOnReset_CMP
RESET
CSstop_CMP
Vdd
LEB 120ns
WindShort
4 events timer
DRV
DRVb
RST_CMP
PWM
COMP
EA_OTA
IC stop
Vref(tf ) = Ktf*Vref
Gm
ACC_TH
DIM_CMP
Multiplier
Vref
DIM
DIMb
CA input
Output
Vref processing
Vdd
Analog pass
DRVb
ZCD_CMP
CS2
DRVb
ZCD
Clock
generator
CLK
Vdd
DRV
Q
Set
60us watch-dog timer
Vtf(start)
1.0V
OA
DRVb
Q
TF
Qb Reset
GND
CS2open_CMP
Set
Reset
CS2fault
Figure 2. Simplified Internal Block Schematic
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NCL30095A
Table 2. MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
V
1, 2, 3 HV NMOS Drain to Source Voltage (V
)
DSS
+380
V
DRAIN(MAX)
Continuous Drain Current
R
steady state, T = 25°C (Note 1)
0.5
A
θ
J−C
C
Continuous Drain Current
Steady State, T = 100°C (Note 1)
R
0.25
A
A
θ
J−C
C
Peak Drain Current
−0.01 / 1.7
V
10
12
13
14
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum Current for VCC pin
– 0.3 to 18
30 (peak)
V
CC(MAX)
mA
V
Maximum Voltage
Continuous Current
– 0.3 to 5.5
−1.7/0.01
V
A
CS1(MAX)
V
HV NMOS Source Voltage
−20 to 18
−1.7/1.7
V
A
SOURCE(MAX)
Maximum current is equal to DRAIN pin
V
HV NMOS Gate Voltage
−20 to 18
V
GATE(MAX)
Maximum current to gate pin
1000 (peak)
mA
V
MAX
Maximum voltage on low power pins (except pins 1,2,3,10,12,13,14)
Maximum current to low power pins
– 0.3 to 9
10 (peak)
V
mA
P
D
Maximum Power Dissipation @ T = TBD°C
TBD
mW
C
R
Thermal Resistance SOIC−14
°C/W
θ
JA
Junction−to−Air, low conductivity PCB
Junction−to−Air, high conductivity PCB
108
70
T
Operating Junction Temperature
−40 to +125
°C
°C
°C
−
JMAX
T
Storage Temperature Range
−60 to +150
STRGMAX
T
LMAX
Lead Temperature (Soldering, 10s)
300
1
MSL
Moisture Sensitivity Level
ESD Capability, HBM model (All pins except GATE) (Note 2)
ESD Capability, HBM model (pin GATE) (Note 2)
ESD Capability, Machine Model (All pins except GATE) (Note 2)
ESD Capability, Machine Model (pin GATE) (Note 2)
ESD Capability, CDM model (Note 2)
3.5
200
250
100
1
kV
V
14
14
V
V
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Limited by the junction temperature.
2. This device contains ESD protection and exceeds the following tests:
Human Body Model per JEDEC Standard JESD22−A114E
Machine Model Method per JEDEC Standard JESD22−A115B
Charged Device Model per JEDEC Standard JESD22−C101E.
3. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA
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NCL30095A
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 13 V, unless otherwise noted)
J
J
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
SUPPLY
Turn−on Threshold Level
V
V
going up
V
V
11.0
8.2
2.8
4.0
12.0
8.8
−
13.0
9.4
−
V
V
V
V
CC
CC(on)
Minimum Operating Voltage, Turn−off Threshold
going down
CC
CC(off)
Hysteresis V
− V
V
CC(on)
CC(off)
CC(hyst)
CC(reset)
V
CC
decreasing level at which the internal logic
V
5.0
6.0
resets
Blanking Duration on V
Blanking Duration on V
t
−
−
−
10
10
10
−
−
ms
ms
mA
CC(off)
VCC(off)
t
CC(reset)
VCC(reset)
Internal Current Consumption of Device before
Start−up
V
= 10V
I
I
I
100
CC
CC1
CC2
CC3
Internal Current Consumption, when DRAIN Pin is
Switching
f
sw
= 65 kHz, V
= 0.5 V
= 2.5 V,
= 0 V
−
−
1.0
0.9
1.5
1.1
mA
mA
COMP
V
CS1
Internal Current Consumption, when DRAIN Pin is
Turned−on
V
COMP
= 2.5 V, V
CS1
OUTPUT OVERVOLTAGE PROTECTION
Over Voltage Protection Thresholds
V
V
going up
V
2.9
2.6
3.0
2.7
3.1
2.8
V
OVP
OVP(off)
V
OVP(on)
going down
OVP
Over Voltage Protection Hysteresis
Timer Duration for Over Voltage Detection
Internal OVP Pin Pull−up Current
Under Voltage Detect Threshold
Under Voltage Detect Propagation Delay
LED CURRENT REGULATION LOOP
Error Amplifier Trans−Conductance
Error Amplifier Current Capability
Error Amplifier Input Offset
V
−
300
33
−
mV
ms
nA
V
OVP(hyst)
t
23
50
0.4
23
43
OVP
OVP(bias)
I
250
0.5
33
450
0.6
43
V
UVP
UVP
t
ms
G
85
13
−20
4.2
−
100
25
−
115
−
mS
mA
mV
V
EA
I
EA
T = 25°C
j
V
20
−
EAIO
COMP(max)
Maximum Control Voltage
V
−
Minimum Control Voltage
V
−
0.7
−
V
COMP(min)
COMP Pin Discharge Resistance
R
−
200
W
COMP(dis)
CURRENT SENSE 1 − INDUCTOR OVERCURRENT LIMITATION
Maximum Internal Current Set−Point
V
> 4 V
V
0.95
−
1.00
50
1.05
90
V
COMP
ILIM
Propagation Delay from V
Off
Detection To Switch
V
CS1
> 1.2 V
t
ns
ilimit
delay
Minimum Internal Current Set−Point
(Dimming Is Detected)
V
< 0.7 V
V
300
−
350
50
400
90
mV
ns
COMP
ILIM_MIN
Propagation Delay from Reduced V
to DRV Off
Detection
V
CS1
> 1.2 V
t
ilimit
delay_DIM
Leading Edge Blanking Duration for V
t
220
320
420
ns
V
ILIM
LEB
Threshold for Winding Short Fault Protection
Activation
V
1.42
1.50
1.58
CS1(stop)
Leading Edge Blanking Duration for V
(Note 4)
t
90
−
120
1
150
−
ns
CS(Stop)
BCS
CURRENT SENSE 2 − ZERO CURRENT DETECTION AND LED REGULATION INPUT
Input Pull−Up Current
V
CS2
= 0.7 V
I
mA
CS2(bias)
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NCL30095A
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 13 V, unless otherwise noted)
J
J
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE 2 − ZERO CURRENT DETECTION AND LED REGULATION INPUT
Internal Reference for Nominal LED Current
Lower ZCD Threshold
V
233
15
250
50
267
80
mV
mV
mV
mV
ns
REF
V
ZCD(falling)
V
V
falling
rising
CS2
Upper ZCD Threshold
V
30
65
95
CS2
ZCD(rising)
ZCD Comparator Hysteresis
V
−
15
−
ZCD(hyst)
Propagation Delay from ZCD To Turn−On Internal
Switch
V
CS2
falling
t
400
500
600
DEM
Current Sense Threshold for CS2 Pin Open Pro-
tection
V
4.0
4.5
5.0
V
CS2(stop)
Blanking Duration for ZCD Detection
ZCD Timeout
t
200
20
300
32
400
45
ns
ZCD(blank)
t
ms
ZCD(timeout)
DIMMING DETECTION
Dimming Detection Comparator Thresholds
V
going up
V
0.400
0.300
0.450
0.350
0.500
0.400
V
ACCTH
ACCTH_H
V
going down
V
ACCTH_L
ACCTH
Dimming Detection Comparator Hysteresis
Dimming Detection Comparator Delay
ON−TIME GENERATOR
V
−
100
70
−
mV
ACCTH_Hyst
V
= V
+ 0.1 V
t
DIM_D
40
90
ms
ACCTH
ACCTH_H
Maximum On Time
V
= 4.2 V
= 2.5 V
= 0.7 V
t
15
8.0
−
18
9.5
0.6
22
11.0
1.2
ms
ms
ms
COMP
COMP
COMP
ONmax
On Time
V
V
t
ON
Minimum On Time
t
ONmin
Thermal Foldback
TF Pin Voltage at which Thermal Fold−Back Starts
V
V
0.94
0.45
1.00
0.5
1.06
0.55
V
V
TF(start)
(V
REF
is Decreased)
TF Pin Voltage at which Thermal Fold−Back Re-
duces V to 10% V
TF(10%)
REF
REF
Current Source for Direct NTC Connection
Blanking Duration for TF Detection after Start−Up
INTERNAL TEMPERATURE SHUTDOWN
Temperature Shutdown (Note 4)
V
V
= 0 V
I
80
85
90
mA
ms
TF
TF
= 0 V
t
250
300
350
TF
TF(blank)
T going up
J
T
TSD
135
−
150
30
165
−
°C
°C
Temperature Shutdown Hysteresis (Note 4)
INTERNAL CASCODED SWITCH
T going down
J
T
TSD(HYS)
On State Resistance of the Low Voltage NMOS
On State Resistance of the High Voltage NMOS
I
I
= 500 mA, Tj = 25°C
R
−
−
3.5
3.5
4.5
5.0
W
W
LDS
L,DS,on
R
H,DS,on
= 500 mA, V
= 15 V
HDS
GATE
V
= 0 V, Tj = 25°C
SOURCE
Maximum Drain to Source Voltage of the Low Volt-
age NMOS (Note 4)
V
30
−
−
V
V
L,DS,max
H,DS,max
Maximum Drain to Source Voltage of the High
Voltage NMOS
V
380
Maximum Off State Leakage Current
V
= 400 V
I
−
−
−
−
5.0
−
mA
ns
ns
DRAIN
DSS
Turn−On Time, 90 to 10 % of V
Turn−Off Time, 10 to 90 % of V
R
R
= 100 W, I = 500 mA
t
on
t
off
10
30
DRAIN
DRAIN
LOAD
LOAD
D
= 100 W, I = 500 mA
−
D
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Guaranteed by Design
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NCL30095A
TYPICAL CHARACTERISTICS
9.5
9.0
8.5
8.0
13
12.5
12
11.5
11
10.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Turn−On Threshold Level, VCC(on)
Figure 4. Minimum Operating Voltage, VCC(off)
5.5
15
13
11
9
5.0
4.5
4.0
7
5
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. VCC Decreasing Level at which the
Internal Logic Resets, VCC(reset)
Figure 6. Internal Current Consumption before
Start−Up, ICC1
1.3
1.1
0.9
0.7
0.5
1.3
1.1
0.9
0.7
0.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Internal Current Consumption when
DRV Pin is Switching, ICC2
Figure 8. Internal Current Consumption when
DRV Pin is Turned−On, ICC3
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NCL30095A
TYPICAL CHARACTERISTICS
4.0
3.5
3.0
2.5
2.0
4.0
3.5
3.0
2.5
2.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Overvoltage Protection Threshold
(VOVP going up), VOVP(off)
Figure 10. Overvoltage Protection Threshold
(VOVP going down), VOVP(on)
300
280
260
240
220
200
1.0
0.8
0.6
0.4
0.2
0.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Internal OVP Pin Pull−Up Current,
IOVP(bias)
Figure 12. Undervoltage Detect Threshold,
VUVP
1.2
1.1
1.0
0.9
0.8
400
380
360
340
320
300
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Maximum Internal Current
Set−Point, VILIM
Figure 14. Minimum Internal Current
Set−Point, VILIM_MIN
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NCL30095A
TYPICAL CHARACTERISTICS
1.60
1.55
1.50
1.45
1.40
260
255
250
245
240
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Threshold for Winding Short Fault
Protection Activation, VCS1(stop)
Figure 16. Internal Reference for Nominal LED
Current, VREF
50
48
46
44
42
40
65
63
61
59
57
55
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Lower ZCD Threshold, VZCD(falling)
Figure 18. Upper ZCD Threshold, VZCD(rising)
0.50
0.48
0.45
0.43
0.40
4.60
4.55
4.50
4.45
4.40
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Current Sense Threshold for CS2
Pin Open Protection, VCS2(stop)
Figure 20. Dimming Detection Comparator
Threshold, VACCTH Going Up, VACCTH_H
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NCL30095A
TYPICAL CHARACTERISTICS
0.40
0.38
0.35
0.33
0.30
1.2
1.1
1.0
0.9
0.8
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Dimming Detection Comparator
Threshold, VACCTH Going Down, VACCTH_L
Figure 22. TF Pin Voltage at Which Thermal
Fold−Back Starts, VTF(start)
90
88
86
84
0.7
0.6
0.5
0.4
0.3
82
80
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. TF Pin Voltage at Which Thermal
Fold−Back Reduces to 10%, VTF(10%)
Figure 24. Current Source for Direct NTC
Connection, ITF
10
10
8
6
4
2
0
8
6
4
2
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. On−State Resistance of the Driving
NMOS, RL,DS(on)
Figure 26. On−State Resistance of the Driving
NMOS, RH,DS(on)
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10
NCL30095A
TYPICAL CHARACTERISTICS
Figure 27. Typical On−Time Measured with 500
mA of Drain Current and Resistive Load
Figure 28. Typical Off−Time Measured with 500
mA of Drain Current and Resistive Load
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11
NCL30095A
APPLICATION IINFORMATION
Functional description
pin and capacitor C . Thanks to the cascoded DRAIN
VCC
NCL30095A uses a Constant On−time Boost architecture
in order to target a unity power factor, when no dimming is
detected. The cascoded drain architecture shown in Figure
29, where Q1 is the High Voltage Cascode NMOS, allows a
architecture, the startup time is very fast (typ < 100 ms).
Unlike a traditional asynchronous boost architecture, where
a power transistor is needed, the cascode architecture uses
two MOSFETs, a low voltage MOSFET Q2 , internal to the
IC Switching regulator, and a High−Voltage NMOS FET
Q1, which is housed in a SOIC−14 package.
simple implementation of a V supply by including a diode
CC
D , external to the switcher IC, between the SOURCE
VCC
Vin
Vout
D1
L1
Iind
ID1
ILED
DRAIN
Q1
Rcasc
GATE
Cout
ICOUT
Dzcasc
Ccasc
VCC
DVCC
SOURCE
CS2
Cvcc
DRV
IRsense2
Rsense2
Q2
CS1
IRsense1
Rsense1
Figure 29. Cascode Architecture
The NCL30095A operates in Critical Conduction Mode
processed then by a circuit block named “Vref processing”,
which provides analog signal Vref. The reference voltage
named Vref serves for the LED current regulation loop. The
LED current regulation loop is working for all conduction
angles, it is then possible by programming the Vref
processing circuit block to get the desired dimming curve as
depicted in Figure 31.
(CrM) under all working conditions, regulating the average
current flowing through the string of LEDs whether the
dimmer is present or not.
The ACC_TH pin senses a scaled down input voltage
(Vin) and by comparing it to an internal reference voltage
named V
it provides a digital signal DIM/DIMb that
ACC_TH
contains the amount of dimming information. DIM/DIMb is
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12
NCL30095A
CS2 open
Latch
(switch off)
V
CS1
>V
CS1(stop)
Thermal
foldback
V
CC
<V
CCreset
TSD+ UVP+OVP
V
TF
>V
V <V
TF TF(start)
TF(start)
V
<
(V >V
)*(V
>V
UVP
)*TSD
CC
CC
CCon
OVP
V
>V
CCreset
V >V
CC CCoff
CC
V
CCreset
Stop
Running
Const.ON
time
Power On
Reset
Read IPT
CTRL
Start
discharge
(V
>V
)*
)
(V
<V
)*
)
COMP
Cton
COMP
Cton
(V
CS1
<V
ILIM_MIN
(V
CS1
>V
ILIM_MIN
V
CC
<V
CCoff
Running
.
ConstPeak
current
Figure 30. Operating status diagram of the device
Critical conduction mode
signal (RST). This process represents the “constant t
on
By looking at Figure 29 it can be seen that the current
average LED regulation loop” which, when steady state is
reached, ensures that:
I
flowing through the external resistor R
,
Rsense1
sense1
connected between pin CS1 and GND, is the same as the
VREF
Rsense2
ILEDavg
+
(eq. 1)
inductor current I plus current spikes associated with the
ind
turning on or turning off of Q2 NMOS FET. The inductor
current information carried by the pin CS1 is used for the
There is one more condition to end the on−time cycle. The
power MOSFET is turned−off only under a condition that
the inductor peak current reaches a level set by the reference
. Minimum input current is
maintained by switching in Constant Peak Current mode.
When a dimmer is present this feature helps to avoid the
inductor peak current limitation. This voltage V
is used
CS1
to generate a reset signal (OCP_RST) resulting from having
reached the inductor maximum peak current controlled by
voltage named V
ILIM_MIN
V
ILIM
reference voltage. If the maximum peak inductor
current is not reached it is the second branch that takes care
of the reset signal (RST) indicating the end of the on−time.
The second branch monitors the off−time current
information at current sense input CS2. The second branch
is inhibited during the MOSFET on−time.
leakage current of the dimmer from charging the C
in
capacitor. At the same time this feature sets a minimum input
current to avoid the current loop cut off when the triac
dimming is applied
The reset signal (RST or OCP_RST) indicates an end of
the on−time and a start of the off−time. Once the off−time
has started, the CS2 pin senses the inductor off−time current
, which is compared to a reference voltage
in order to generate a zero−crossing signal (ZCD) that
in turn is processed by the clock generation block. The
generated clock pulse triggers a start of the new on−time
cycle.
As shown in Figure 2, the second branch voltage is an
image of the off−time inductor current. It is sent to the input
of an OTA and by comparing to a reference voltage (V
)
REF
across R
sense2
a control voltage is generated at the COMP pin. The COMP
pin voltage is proportional to the average LED current. It is
compared to a constant on−time ramp voltage generated by
V
ZCD
charging the capacitor C
by a constant current I
. The
TON
TON
output of the comparator generates constant on−time reset
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13
NCL30095A
LED Current Regulation and Dimming Curve
As long as the max peak current limitation is not exceeded
or a thermal foldback condition is present, the average LED
current regulation loop is controlled by the OTA via
equation 1 and Triac Dimming Curve of Figure 31.
100%
Incandescent
90%
NEMA 6 Max
NEMA 6 Min
80%
NEMA 7 Max Linear
NEMA 7 Min Linear
70%
NEMA 7 Max
NEMA 7 Min
60%
LED Current Match
Optimum Dimming
50%
Optimum Compatibility
40%
30%
20%
10%
0%
0
20
40
60
80
100
120
140
160
180
Dimmer Conduction Angle (deg)
Figure 31. Triac Dimming Curve Digitally Generated
For example if R
= 20 Ω and V
= 0.5 V this gives
processing
REF
optimum compatibility acceleration curve by default (see
Figure 31) with an option of the optimum diming
acceleration curve.
sense2
REF
I
= 25 mA. The circuit block named V
LED
which can be seen in Figure 2 will be programmed for the
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14
NCL30095A
Table 4. Coordinates of dimming curve programming points
Dimmer conduction angle (deg)
Optimum Dimming V
/V
Optimum Compatibility V
/V
REF REF,max
REF REF,max
18
35
0.0%
0.0%
2.0%
1.0%
36
1.0%
2.0%
40
2.0%
3.0%
45
3.0%
5.0%
54
5.0%
15.0%
35.0%
55.0%
75.5%
95.5%
100.0%
100.0%
100.0%
100.0%
100.0%
72
10.0%
90
28.0%
108
126
130
140
144
162
180
50.0%
75.0%
80.0%
95.0%
100.0%
100.0%
100.0%
Dimming presence sensing
The conduction angle of the dimmer is sensed through pin
ACC_TH. The rectified and dimmed V voltage (see Figure
To regulate an average LED current in a single stage
architecture the instantaneous LED current can have as
much as +/−50% ripple component (this ripple component
in
1) appears on pin ACC_TH divided by the resistor bridge
depends on the value of C capacitor and LED string
out
composed of R
equal to:
and R
. The ACC_TH voltage is
dynamic resistance). The OTA must work linearly while a
acc_top
acc_bot
voltage with ripple is applied. The transconductance (G )
m
value is set as low as 100 ms and the minimal output current
capability is at +/−25 mA to ensure the OTA linear operation,
without entering the saturation level
VACC_TH + Kacc @ Vin
(eq. 2)
(eq. 3)
With:
Racc_bot
Kacc
+
Racc_bot ) Racc_top
Kacc.Vin
VACC_TH
time
0
tCA
tCA,min
tCA,max
Figure 32. ACC_TH pin waveforms and max/min detectable dimmer conduction angles
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15
NCL30095A
Voltage sensed at the ACC_TH pin is compared to the
reference voltage (see Figure 32) in order to
between DRAIN and CS pins is kept open to avoid the
leakage current of the dimmer from charging the C
V
ACC_TH
in
generate a digital signal (DIM/DIMbar) (see Figure 2 and
Figure 33). The DIM/DIMbar signal is used as the input of
the block named “Vref processing block”. Every half period
of the mains voltage, the “Vref processing block” computes
and holds the dimmer duty cycle and sets the corresponding
capacitor (see Figure 1) and providing a low impedance path
for “SMART” dimmer operation.
CA is the Dimmer Conduction Angle expressed in
degrees and can be calculated based on the Dimmer
Conduction Time t (see Figure 33) and the AC mains
CA
V
REF
voltage.
frequency F
described in the following formula:
mains
Unless the minimum peak current at CS1 pin reaches the
CA + 360 @ tCA @ fmains
(eq. 4)
V
level the internal power MOSFET connected
ILIM_MIN
Kacc.Vin
VACC_TH
time
0
tCA
DIMbar
VDD
(CA_deg/180)*VDD
time
0
DIM
VDD
time
0
Figure 33. Dimming Waveforms
Detailed description of the VREF processing
2 @ Ton
2 @ T
CA +
(eq. 5)
The conduction angle is obtained by the digital division of
the sampled values of the conduction time and the period.
The conduction time is counted by the timer A over the both
periods of mains as the period of mains. This type of sensing
decreases the diming system sensitivity to the asymmetry of
the diming triac and reduces flickering. The conducting
angle is obtained as the ratio of Timer A (conduction time)
and Timer B (the mains period). Please refer to Figure 34 and
Figure 35.
The additional IIR filters and the conduction angle
lockout for 32 cycles of the rectified mains signal helps to
reduce flickering caused by the differing leading edges and
quantization error of the A/D conversion at TF pin and CA
measurement.
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16
NCL30095A
Figure 34. Detailed block schematic of the conduction angle measurement and the Vref processing
Kacc.V
in
VACCTH
time
0
Ton
Ton
2T
Timer A counts 2 conducting angles
DIMb
time
0
Timer A counts 2 conducting angles
DIM
time
0
DIM/2
Timer B counts 2 periods
time
0
Figure 35. Time diagram of the implemented conduction angle measurement
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17
NCL30095A
The minimum current set−point feature is implemented.
It starts play a role in case that the Vref is so small that the
current set−point observed at CS1 pin is below the
applied. This feature sets the minimum current to avoid the
current loop cut of when the triac dimming is applied. This
feature increases the compatibility with the most of the triac
dimmers.
V
level. Then the regulation loop requirement is
ILIM_MIN
ignored and higher level of current set−point V
is
ILIM_MIN
CS1 envelope
Minimum current set −point keeps the
loop current
VILIM_MIN
time
0
Figure 36. The minimum current set−point effect to keep the loop current
Operating modes and Protection modes
Table 5. Operating and protection modes
Event
Timer protection
Next device status
Release to normal operation mode
Overcurrent
N/A
Normal operation
N/A
V
ILIM
= 1.0 V
Reduced peak current
= 0.35 V
N/A
Normal operation
Latch
N/A
V
ILIM_MIN
Winding short
> V
4 consecutive pulses
10 ms timer
V
< V
CC CC(reset)
V
sense1
CS1(stop)
Low supply
< V
Device stops
V
> V
CC CC(on)
V
CC
CC(off)
Thermal foldback event
< V
Immediate reaction
20 ms timer
Reduced output current,
thermal fold−back
V
> V
OTP
TF(start)
V
OTP
TF(start)
Output overvoltage
> V
Device stops
Device stops
Device stops
V
OVP
< V
> V
OVP(on)
V
OVP
V
CC
OVP(off)
CC(on)
Overvoltage pin shorted to GND
< V
Immediate reaction
10 ms timer
V
< V
CC CC(reset)
V
OVP
UVP
Internal TSD
(V > V
CC
) & TSDb
CC(on)
CS2 ZCD timeout protection
ZCD is not detected. To avoid stopping the device under this
condition the ZCD timeout feature is added. If no ZCD event
is detected until the ZCD timer (tZCD(timeout)) elapses the
internal cascode switch is turned on anyway.
The second CS2 pin has an additional feature. In case of
very low average current is regulated the CS2 voltage can be
too low. The CS2 sensed voltage can be too low that the CS2
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18
NCL30095A
Vin
Vout
D1
L1
DRAIN
Q1
Rcasc
GATE
Cout
Dz
casc
Ccasc
ZCD timeout
DRV
CS2
32 ms timer
Q
S
R
VCC
DVCC
SOURCE
Cvcc
DRV
Q
S
R
Q2
VZCD
CS1
Figure 37. CS2 pin ZCD timeout protection – principal diagram
Protection against a winding short
Under some conditions, such as a winding short−circuit of
the boost inductor, the on−time duration is at a minimum
(based on the internal propagation delay of the detector and
LEB duration). In this event, the current sense voltage
increases above V , because the controller is blanked due
ILIM
to the LEB time and fast current slope. Dangerously high
current can occur in the system if nothing is done to stop the
controller. To avoid this, an additional fast comparator
senses when the current sense voltage on CS1 pin reaches
V
= 1.5 x V : if the fast comparator toggles 4
ILIM
CS1(stop)
times, the controller immediately enters a protection mode.
See the block diagram at Figure 2 for more details.
Overvoltage Protection
An overvoltage condition, for example if the LED string
is open, can be sensed on V voltage by the external resistor
out
divider comprised of R
Figure 38) which is connected to the OVP pin. If the voltage
of the OVP pin exceeds the V reference voltage, the
OVP fault state goes high and the switching regulator stops
switching. When the voltage at OVP pin drops below the
and R
resistors (see
ovp_top
ovp_bot
Figure 38. Overvoltage Protection Circuit
Thermal Fold−Back
The thermal fold−back circuit reduces the current
supplying to the LED string if the temperature monitored by
an external NTC resistor is too high.
The current is reduced down to 0% of its nominal value.
The thermal fold−back starting temperature depends on the
NTC resistor value selected by the power supply designer.
OVP(off)
V
the device starts switching again. In addition the
OVP(on)
OVP input also has under−voltage protection (UVP) to
ensure the resistor divider is properly connected. If the
voltage at OVP pin is below the V
stops.
threshold the device
UVP
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19
NCL30095A
The TF pin allows the direct connection of an NTC. When
the TF pin voltage V drops below V , the internal
of its required value then the switching regulator enters the
stop mode.
TF
TF(start)
reference for the constant current control V
is decreased
The thermal fold−back and OTP thresholds correspond
roughly to the following resistances:
REF
proportionally to V . When V reaches V
, V
is
TF
TF
TF(10%) REF
set to V
current. If V
regulator still reduces the V . If V
, corresponding to 10% of the required output
• Thermal fold−back starts when R
≤ 11.76 kW.
REF10
NTC
drops below V
the switching
TF
TF(10%)
• Thermal fold−back sets the 10% of VREF when R
NTC
drops below the 5%
REF
REF
≤ 5.88 kW.
Iout(nom)
10% Iout(nom)
0
VTF(10%)
VTF(start)
VTF
Figure 39. Output current reduction versus TF pin voltage
At startup, when V reaches V
, the TF pin sensing
LED light in case of over temperature or noise coupled to TF
pin. The maximum value of OTP pin capacitor is given by
the following formula (The standard start−up condition is
considered and the NTC current is neglected):
CC
CC(on)
is blanked for at least 300 ms in order to allow the TF pin
voltage to reach its nominal value if a filtering capacitor is
connected to the TF pin. This is to avoid flickering of the
t
TF(blank)min @ ITFmin
250 @ 10*6 @ 80 @ 10
CTFmax
+
+
*6 F + 19 nF
(eq. 6)
1.06
VTF(start)max
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20
NCL30095A
Figure 40. Thermal Fold−back circuitry
Figure 41. Typical thermal fold−back characteristic when the 330 kW NTC and 39 kW parallel resistor are
connected to TF pin
Temperature shutdown
instantaneously, and goes to the stop mode with low power
consumption. Specific blocks are still powered from the
The NCL30095A includes a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the switcher stops switching
V
CC
supply to keep the TSD information. When the
temperature falls below the low threshold, the device
restarts. See the status diagrams at the Figure 30.
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21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB LESS PIN 4
CASE 751DY
14
ISSUE O
1
DATE 28 OCT 2015
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
L
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C A
B
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
M
5.80
0.25
0.40
0
DETAIL A
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
14
13X
0.58
1.27
PITCH
XXXXXXXXXG
AWLYWW
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
6.50
WW
G
= Work Week
= Pb−Free Package
13X
1.18
1
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON06050G
SOIC−14 NB LESS PIN 4
PAGE 1 OF 1
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