NCL30105DR2G [ONSEMI]
灵活可调光的降压LED驱动器控制器;
| 型号： | NCL30105DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 灵活可调光的降压LED驱动器控制器 驱动 控制器 光电二极管 接口集成电路 驱动器 |
| 文件： | 总24页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30105
Constant Off Time PWM
Current-Mode Controller for
LED Applications
The NCL30105 is a peak current controlled fixed off time controller
designed for LED driver applications in which the LEDs are operated
in deep Continuous Conduction Mode (CCM) without requiring slope
compensation. Featuring an adjustable off time generator, the
controller can drive a MOSFET up to a 500 kHz switching frequency.
A dedicated dimming pin enables the use of a pulse−width
modulated logic signal to dim the LEDs directly. The soft−start pin
creates a startup sequence that slowly ramps up the peak current and
enables the adjustment of the peak current setpoint for analog
dimming control. The device features robust protection features to
detect switch overcurrent faults and to detect maximum on time
events.
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8
1
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
Features
L0105
ALYW
G
• Constant Off Time Current−Mode Control Operation
• Adjustable Off Time (0.5 ms to 10 ms)
• Internal Leading Edge Blanking
1
• Source 250 mA / Sink 500 mA Peak Drive Capability
L0105 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
3.2% Current Sense Accuracy at 25°C
• Internal Startup Delay
• 3.3 V Logic Level Dimming Input
• This is a Pb−Free Device
Safety Features
• Thermal Shutdown
• Maximum On Time Protection
• Overcurrent Protection
PIN CONNECTIONS
1
toff
NC
DIM
VCC
CS
SSTART
Typical Application
GND
DRV
• LED Backlight Drivers for LCD Panels
• LED Light Bars
• LED Street Lighting
• LED Bulbs
(Top View)
ORDERING INFORMATION
†
Device
NCL30105DR2G
Package
Shipping
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2012 − Rev. 2
NCL30105/D
NCL30105
Vin
LED
1
C
LED
LED
N
D
L
NCL30105
toff
NC
SSTART
GND
Soft−Start /
Ipeak Adjustment
DIM
VCC
CS
DIM
V
CC
C
SSTART
M
DRV
R
R
sense
CV
toff
CC
Figure 1. Typical Application Diagram
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NCL30105
Vcc
VCC
UVLO
ok = 1, else 0
NC
Von = V
CC(on)
CC(off)
ref
Voff = V
V
toff(open)
1 = reset
1 = reset
t
start(delay)
V
SSTART(open)
set current
high
I
SSTART
toff
SSTART
= rst
SET
toff
generator
Q
SET
V
DIM(open)
start
pulse
S
Q
R
DIM
DIM
Q
R
S
Q
Q
R
Q
/ I
ratio
GND
OVRI
−
−
OVRI
t
on
>
t
on(MAX)
V
ILIM
V
ILIM(fault)
down
N
fault
up
Vcc
count to N
fault
t
t
LEB
LEB(fault)
CS
DRV
Figure 2. Internal Circuit Architecture
Table 1. PIN FUNCTION DESCRIPTION
Pin
Number
Pin Name
Function
Pin Description
1
toff
Adjusts the Off Time
Duration
A resistor to ground sets the off time duration.
2
3
4
DIM
VCC
CS
Dimming Input
This pin is used for PWM dimming or to enable/disable the controller.
An external auxiliary voltage connected to this pin supplies the controller.
Supplies the Controller
Current Sense Input
This pin monitors the peak current. When the peak current reaches the
internal threshold, the DRV is turned off.
5
6
7
DRV
GND
Driver Output
The output of the driver is connected to an external MOSFET gate.
The controller ground.
−
SSTART
Soft−start / Peak Current
A capacitor connected to this pin sets the soft−start duration. The voltage
of this pin adjusts the peak current set point for analog dimming.
Adjustment
8
NC
Non−connected Pin
Non−connected pin
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NCL30105
Table 2. MAXIMUM RATINGS TABLE (Notes 1 – 4)
Rating
Symbol
Value
−0.3 to 5.5
10
Unit
V
toff Voltage
V
toff
toff
toff Current
I
mA
V
DIM Voltage
V
−0.3 to 7
10
DIM
DIM
DIM Current
I
mA
V
SSTART Voltage
SSTART Current
CS Voltage
V
−0.3 to 5.5
10
SSTART
SSTART
I
mA
V
V
CS
−0.3 to 7
10
CS Current
I
mA
V
CS
DRV Voltage
V
−0.3 to V
500
DRV
DRV(sink)
CC
DRV Sink Current
DRV Source Current
Supply Voltage
Supply Current
I
mA
mA
V
I
250
DRV(source)
V
CC
−0.3 to 22
20
I
mA
mW
CC
Power Dissipation (SO−8)
A
P
D
450
2
(T = 70°C, 2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)
Thermal Resistance Junction−to−Ambient (SO−8)
R
°C/W
q
JA
2
(2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)
178
168
127
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
Operating Junction Temperature Range
Storage Temperature Range
T
−40 to 150
−60 to 150
300
°C
°C
°C
J
T
STG
Lead Temperature (Soldering, 10 s)
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1 − 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1 − 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
Pins 1 − 8: Charged Device Model 2000 V per JEDEC Standard JESD22−C101C.
2. This device contains Latch−Up protection and exceeds 100 mA per JEDEC Standard JESD78.
2
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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NCL30105
Table 3. ELECTRICAL CHARACTERISTICS (R = 40.2 kW, V
= 3 V, C
= 100 nF, V = 0 V, C
= 1 nF, V = 12 V,
toff
DIM
SSTART
CS
DRV CC
unless otherwise specified (For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified))
J
J
Characteristic
STARTUP AND SUPPLY CIRCUITS
Startup Voltage Threshold
Minimum Operating Voltage
Supply Voltage Hysteresis
Current Consumption in Latch Mode
Startup Current Consumption
Device Disabled Current Consumption
Device Switching Current Consumption
GATE DRIVE
Test Conditions
Symbol
Min
Typ
Max
Unit
V
Increasing
Decreasing
V
V
9
8
1
−
−
−
−
10
8.8
11
10
V
V
CC
CC(on)
V
CC
CC(off)
V
CC(on)
− V
V
1.2
1.5
900
390
1.7
2.49
V
CC(off)
CC(HYS)
CC(latch)
I
510
250
0.71
1.84
mA
mA
mA
mA
V
< V
V
− 500 mV
I
I
I
CC
CC(on)
CC1
CC2
CC3
= 0 V
DIM
f
= 60 kHz
SW
Drive Sink Resistance
I
= 25 mA
= 25 mA
R
R
−
−
−
−
6.0
24
80
25
13.2
44
W
W
SNK
SNK
Drive Source Resistance
Rise Time
I
SRC
SRC
V
V
= 10% to 90%
= 90% to 10%
t
r
140
60
ns
ns
DRV
DRV
Fall Time
t
f
CURRENT SENSE
Current Sense Voltage Threshold
T =−40°C to 125°C
V
ILIM
0.95
0.977
1.01
1.01
1.05
1.042
V
J
T =25°C
J
Current Sense Propagation Delay
V
= 0 V to 1.2 V Step,
t
−
60
150
ns
CS
ILIM
dV/dt = 10 V/ms
V
CS
= V
to V
= 10%
ILIM
DRV
Leading Edge Blanking Duration
CONSTANT OFF TIME GENERATOR (Note 5)
Off Time (Note 6)
t
470
545
670
ns
LEB
R
= 5 kW
t
0.87
2.5
1.02
−
1.13
60
ms
kW
ms
toff
off1
Recommended Off Time Resistor Range
Minimum Off Time
R
t
toff(range)
R
= 0 W
t
0.3
0.37
11.77
1
0.5
14.5
1.05
−
toff
off(MIN)
Maximum Off Time
R
= open
10
ms
toff
off(MAX)
t
off
Pin Regulated Voltage
V
0.95
500
V
toff(REG)
Maximum Switching Frequency (Note 7)
SOFT−START
R
= 0 W
f
−
kHz
toff
(MAX)
Soft−Start Charge Current
V
= 3 V
I
17
20
3
23
mA
SSTART
SSTART
Soft−Start Voltage to Peak Current Set
Point Ratio
V
= V
* I
I
ratio
2.85
3.15
−
SSTART
ILIM
ratio
Soft−Start Pin Open Voltage
V
4.5
5
5.5
V
SSTART(open)
Soft−Start Internal Discharge Switch
Resistance
I
= 5 mA
R
200
350
500
W
SSTART
DS(on)SSTART
DIMMING INPUT
Dimming Enable Voltage Threshold
Dimming Disable Voltage Threshold
DIM Pin Open Voltage
V
Increasing
Decreasing
V
1.8
0.8
4
2
1
2.2
1.2
5.5
150
1
V
V
DIM
DIM(H)
V
DIM
V
DIM(L)
V
4.5
90
V
DIM(open)
DIM Pin Internal Pull−Up Resistor
Dimming Wake−Up Time
V
= 0 V
R
50
−
kW
ms
DIM
DIM
V
= 0 V to 3 V Step,
t
0.28
DIM
wake
dV/dt = 10 V/ms
to V = 90%
DRV
V
DIM
= V
DIM(H)
5. See Figure 17.
6. The tolerance of toff is guaranteed by design.
7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.
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NCL30105
Table 3. ELECTRICAL CHARACTERISTICS (R = 40.2 kW, V
= 3 V, C
= 100 nF, V = 0 V, C
= 1 nF, V = 12 V,
toff
DIM
SSTART
CS
DRV CC
unless otherwise specified (For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified))
J
J
Characteristic
PROTECTION
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum On Time
t
29.8
34
8
42.1
ms
on(MAX)
Number of Consecutive Maximum On
Time Events or Overcurrent Events
N
−
−
−
fault
Overcurrent Current Sense Voltage
Threshold
V
1.5
10
1.6
70
1.7
V
ILIM(fault)
ILIM(fault)
Overcurrent Propagation Delay
V
CS
= 0 V to 2 V Step,
t
150
ns
dV/dt = 10 V/ms
to V
DRV
V
CS
= V
= 10%
ILIM(fault)
Overcurrent Leading Edge Blanking Dur-
ation
t
170
220
280
ns
LEB(fault)
Leading Edge Blanking Duration Ratio
Startup Delay
t
/t
t
0.3
0.4
130
155
40
0.8
−
LEB(fault) LEB
LEB(ratio)
V
CC
= V
to V
= 90%
t
start(delay)
100
172
ms
°C
°C
ms
CC(on)
DRV
Thermal Shutdown
T = Increasing
J
T
SHDN
Thermal Shutdown Hysteresis
Thermal Shutdown Delay
5. See Figure 17.
6. The tolerance of toff is guaranteed by design.
7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.
T = Decreasing
J
T
SHDN(HYS)
SHDN(delay)
T
75
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NCL30105
TYPICAL CHARACTERISTICS
11.0
10.8
10.6
10.4
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
10.2
10.0
9.8
9.6
9.4
9.2
9.0
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Startup Voltage Threshold vs.
Junction Temperature
Figure 4. Minimum Operating Voltage vs.
Junction Temperature
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
330
310
290
270
250
230
210
190
170
150
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Supply Voltage Hysteresis vs.
Junction Temperature
Figure 6. Startup Current Consumption vs.
Junction Temperature
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.2
1.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Device Disabled Current
Consumption vs. Junction Temperature
Figure 8. Device Switching Current
Consumption vs. Junction Temperature
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NCL30105
TYPICAL CHARACTERISTICS
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
600
590
580
570
560
550
540
530
520
510
500
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Current Sense Voltage Threshold vs.
Junction Temperature
Figure 10. Leading Edge Blanking Duration vs.
Junction Temperature
100
90
80
70
60
50
24
23
22
21
20
19
18
40
30
20
17
16
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Current Sense Propagation Delay
vs. Junction Temperature
Figure 12. Soft−Start Charge Current vs.
Junction Temperature
3.15
3.10
3.05
3.00
1.15
1.10
1.05
1.00
0.95
Rtoff = 5 kW
2.95
2.90
2.85
0.90
0.85
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Soft−Start Voltage to Peak Current
Figure 14. Off Time vs. Junction Temperature
Set Point Ratio vs. Junction Temperature
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NCL30105
TYPICAL CHARACTERISTICS
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
9.5
9.0
−50 −25
−50 −25
0
25
50
75
100
125
150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Minimum Off Time vs. Junction
Temperature
Figure 16. Maximum Off Time vs. Junction
Temperature
13
12
11
10
9
8
7
6
5
50
45
40
35
30
4
3
25
20
2
1
0
2.5
12.5
22.5
32.5
42.5
52.5
62.5
−50 −25
0
25
50
75
100
125 150
R
, toff PIN RESISTOR (kW)
T , JUNCTION TEMPERATURE (°C)
J
toff
Figure 17. Off Time vs. toff Pin Resistor
Figure 18. Maximum On Time vs. Junction
Temperature
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
2.5
2.0
1.5
1.0
V
DIM(H)
V
DIM(L)
0.5
0.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Overcurrent Current Sense Voltage
Threshold vs. Junction Temperature
Figure 20. Dimming Thresholds vs. Junction
Temperature
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NCL30105
TYPICAL CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
R
, toff PIN RESISTOR (kW)
toff
Figure 21. Zoomed In Off Time vs. toff Pin
Resistor
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NCL30105
Application Information
Introduction
pin current source is enabled and the soft−start
NCL30105 implements a current−mode architecture
operated with a constant off time. The internal current set
point and the external sense resistor determine the on time
duration. The off time duration is adjusted with a resistor
connected from the toff pin to ground. The constant off time
operation enables deep continuous conduction mode
operation without requiring slope compensation. The DIM
pin enables the use of a PWM signal to modulate the
switching pattern and adjust the average luminosity. The
SSTART pin creates a soft−start that reduces the stress on the
power components during startup and enables the use of an
analog dimming signal to set the peak current by adjusting
the SSTART pin voltage.
• Constant Off Time Peak Current−Mode Operation:
The constant off time technique enables the controller
to operate a converter in deep continuous conduction
mode without requiring slope compensation. The
constant off time technique is inherently immune to
sub−harmonic oscillations.
sequence begins.
• Soft−Start Operation: A capacitor connected to the
SSTART pin is charged by an internal current source
after the t
timer period has elapsed. The
start(delay)
soft−start period is completed when the SSTART pin
voltage reaches V *I . The soft−start capacitor is
discharged during the t
ILIM ratio
to ensure the SSTART
start(delay)
pin voltage begins charging from zero.
• Peak Adjustment: Analog dimming is achieved by
forcing the SSTART pin below V
*I , which
ILIM ratio
lowers the peak current set point. Note: even if the
SSTART pin is forced to 0 V, there is still a minimum
on time every switching cycle. Under this condition, the
minimum on time is the current sense leading edge
blanking time plus the propagation delay to turn off the
MOSFET and the off time is determined by the toff
resistor value.
• Leading Edge Blanking: an internal circuit blinds the
current sense comparator for a few hundred
• Off Time Adjustment: A pull−down resistor
connected to the toff pin sets the off time duration.
• Maximum On Time Protection: an internal circuit
monitors the drive signal on time duration. If the drive
nanoseconds when the output drive goes high. The LEB
ensures that controller remains insensitive to the
turn−on voltage spikes observed on the CS pin due to
the free−wheel diode recovery time.
on time duration reaches t
, the fault up/down
on(MAX)
• Dimming Input: a dedicated pin is provided to PWM
counter is incremented by 1. If the drive on time
duration reaches t during the next clock cycle,
modulate the LED current to reduce the LED
on(MAX)
luminosity. The circuit is driven on and off via a 3.3−V
logic level signal. The DIM pin can also be used as an
enable/disable pin, since the switching is disabled when
there is a logic low signal applied to this pin.
the counter is incremented again. If the drive on time
duration does not reach t due to the current
on(MAX)
comparator being triggered during the next drive on
time, the counter is decremented by 1. This sequence
continues until the counter reaches 8. If the counter
reaches 8, the NCL30105 is immediately latched off.
• Thermal Shutdown: if the junction temperature of the
controller exceeds an internal threshold, the drive is
disabled. The drive remains disabled until the junction
temperature decreases below the internal hysteresis
threshold. The disabling of the drive protects the
controller from destruction due to overheating.
When V is forced below V
and then above
CC
CC(off)
V , the latch is reset.
CC(on)
• LED Short−Circuit Protection: If the CS pin voltage
increases above V , the overcurrent comparator
ILIM(fault)
is triggered, which turns off the drive and increments
the fault up/down counter by 1. If the overcurrent
comparator is triggered again during the next drive on
time, the counter is incremented again. If the
overcurrent comparator is not triggered due to the
current comparator being triggered during the next
drive on time, the counter is decremented by 1. This
sequence continues until the counter reaches 8. If the
counter reaches 8, the part is immediately latched off.
Startup Sequence
When V reaches V
, the NCL30105 maintains the
CC
CC(on)
drive low and the soft−start capacitor (C
to the SSTART pin) remains pulled to ground by the internal
pull−down switch until the startup delay (t
, connected
SSTART
)
start(delay)
elapses. Once the t
period has elapsed, the drive is
start(delay)
enabled and a soft−start sequence begins. The internal
current source begins charging C and the voltage on
the SSTART pin (V
SSTART
) begins increasing. The peak
divided by I . When
SSTART
current set point is equal to V
When V is forced below V
and then above
SSTART
ratio
CC
CC(off)
V
SSTART
reaches the voltage that sets the maximum peak
V , the latch is reset.
CC(on)
current (V
= V
*I ), the soft−start sequence is
SSTART
ILIM ratio
• Power On Delay: When V reaches V
, the
CC
CC(on)
complete and the peak current set point is equal to V
divided by I . Figure 22 describes a typical start−up
sequence.
SSTART
t
timer begins counting, during which the
start(delay)
ratio
drive is disabled. When t
elapses, the SSTART
start(delay)
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NCL30105
V
CC
V
V
CC(on)
CC(off)
t
Internal
timer
start(delay)
reset
reset
V
DRV
V
SSTART
V
SSTART(open)
V
= V
* I
SSTART
ILIM ratio
User changes
the setpoint
V
CS
Soft−Start
Sequence
V
ILIM
Soft−Start
Sequence
Constant Peak Variable Peak
Figure 22. A Typical Startup Sequence
Soft−Start Pin
source, the current into the SSTART pin must be limited to
ensure that the maximum current rating is not exceeded. It
The soft−start internal section is shown in Figure 23. The
soft−start sequence is implemented using a current source
that charges an external capacitor. The relationship between
the capacitor voltage and the peak current voltage set point
is recommended to set V
by connecting a diode as
SSTART
shown in Figure 23. Using this configuration, the SSTART
capacitor value to set a 15 ms soft−start duration (t
)
SSTART
is I . The maximum peak current set point is
is calculated using Equation 1:
ratio
V /I . For luminosity balancing purposes, it is
SSTART ratio
(eq. 1)
possible to force the voltage on the SSTART pin from an
external source. When forcing V with an external
I
SSTART @ tSSTART
20 m @ 15 m
CSSTART
+
+
+ 0.1 mF
3
Iratio
SSTART
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12
NCL30105
latch reset
V
SSTART(open)
Current
comparator
I
SSTART
−
D2
1N4148
peak current
SSTART
setpoint control
/
sensed
current
Iratio
C
SSTART
V
ILIM
t
UVLO reset
start(delay)
Timer reset
Figure 23. The Soft−start Block Configuration to Set the Peak Current Setpoint
Constant Off time Generator
peak current threshold, the inductor value, and the input
voltage. Unlike traditional peak current mode control, the
fixed off time technique is not susceptible to sub−harmonic
instability as shown in Figure 24:
The controller operates with a constant off time technique.
The off time technique is implemented by forcing a constant
off time with the on time being set by the combination of the
I (t)
L
constant
DI
L
constant
off
on
Figure 24. The Constant Off Time Technique is Immune to
Sub−Harmonic Instabilities without Ramp Compensation
In Figure 24, the perturbation is corrected in one switching
cycle, despite a duty ratio greater than 50%. This benefit
enables the designer to exclude slope compensation when
operating the inductor in a deep continuous conduction
mode.
The constant off time generator follows the principle
sketched in Figure 25 where an internal timer is started at the
end of each on time. Once the off time generator has elapsed,
it begins the next DRV pulse. The off time is programmed
by connecting a resistor from the toff pin to ground. The off
time range is from 0.5 ms to 10 ms.
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13
NCL30105
on
Drive
off
Internal
timer
adjustable
constant
Figure 25. A Timer is Started at the End of the On Time Duration
Protection
The NCL30105 includes several methods of protection.
One of the protection features is the maximum on time
limitation, which protects the system if the CS pin does not
receive a signal. The on time is internally limited to
t
. The maximum on time limitation may occur if the
on(MAX)
input voltage is too low or if the CS pin is shorted to ground.
After 8 consecutive maximum on times events, the
controller is latched as shown in Figure 26.
Fault
Controller is
latched after
the 8th event
occurs
Smaller pulse:
countdown
here
t
on(MAX)
Count 1
2
1
2
3
4
5
6
7
8
Figure 26. The Protection Feature Limits the Maximum On Time
and Disables the Controller During a Fault
In latched mode, the controller consumes a low current
and waits for a complete V cycle (V decreases to less
in the circuit. The LEB circuit “blanks” the noise to ensure
that the current and overcurrent comparators are not
inadvertently triggered. If the LEB circuit is omitted, the
noise causes the DRV to turn off before the required peak
current is reached as shown in Figure 28. This causes the
system to operate erratically. When the LEB circuit is
included, the noise is “blanked” by blinding the current
CC
CC
than V
and then increased to greater than V ) to
CC(on)
CC(off)
resume operation. The tracking of the fault events is
implemented with an up/down counter. The counter is
incremented by 1 when the t
duration ends the
on(MAX)
driving pulse. The counter is decremented by 1 when a
normal reset occurs via the current comparator. When the
counter reaches 0, it stores this value and waits for an up
pulse to change state.
The NCL30105 includes Leading Edge Blanking (LEB)
circuits to prevent inadvertent triggering of the current and
overcurrent comparators. When the DRV pin goes high,
noise is generated on the CS pin due to the parasitic elements
comparator for the LEB duration (t ) and the required
LEB
peak current is reached as shown in Figure 29. The inclusion
of the LEB circuits prevents the erratic operation of the
system.
Another protection feature is the overcurrent detection.
The overcurrent detection activates when a short−circuit
occurs in the inductor and LED string. To prevent false
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14
NCL30105
detection during surge tests, the controller uses the same
counter as the maximum on time limitation. Due to the two
< t . When the overcurrent comparator output goes high,
LEB
it resets the PWM latch and increments the counter. The
different LEB circuits (t
and t
) configuration, if
counter can no longer increment or decrement until the next
switching cycle. If during the time the overcurrent
LEB
LEB(fault)
there is a severe overload, the overcurrent comparator is
triggered first and the counter is incremented. If the
overcurrent comparator is not triggered during the next
clock cycle, the counter is decremented by the current
comparator. Figure 27 depicts the logical arrangement
inside the controller. In the presence of a fast rising signal,
comparator output is high, t
elapses and causes the
LEB
current comparator output to go high, the output of the
current comparator is ignored due to the AND gate
connection. Figure 30 illustrates the operation of the CS
logic during an overcurrent fault. Only one up count or one
down count is made per switching cycle.
the overcurrent comparator is triggered first since t
LEB(fault)
V
ILIM
Current
Comparator
−
latch
off
+
CS
t
LEB
Overcurrent
Comparator
t
LEB(fault)
+
down
up
Count to N
N
fault
−
fault
V
ILIM(fault)
t
>
on
Q
t
on(MAX)
PWM reset
Figure 27. CS Internal Logic
V
CS
(t)
V
CS
(t)
Required peak current
Noise “blanked”
t
ILIM
V
ILIM
V
ILIM
t
ILIM
t
t
V
down
Inadvertant trigger
ILIM
V
ILIM
down
Comparator
Output
Comparator
Output
t
t
LEB
LEB
t
t
DRV
t
t
DRV
DRV turned off
before required
peak current is
reached
Figure 29. Circuit with Leading Edge Blanking
Figure 28. Circuit without Leading Edge Blanking
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NCL30105
V
CS
(t)
V
V
ILIM(fault)
t
ILIM(fault)
ILIM
t
ILIM
t
t
V
ILIM(fault)
up
Comparator
t
LEB(fault)
V
ILIM
Ignored
Comparator
down
t
t
LEB
LEB
t
t
DRV
off
Figure 30. The Overcurrent Comparator Increments the Counter during a Fault
Minimum Dimming Duty Cycle
During each DIM cycle if the max on time limit is reached
a certain number of times, the current comparator must be
triggered the same number of times to reset the fault counter.
For each DIM cycle, if the maximum on time limit is reached
a greater number of times than the number of times the
current comparator is triggered, the fault counter is not reset
and is incremented each DIM cycle until the fault count is
reached (Nfault = 8). This results in a minimum dimming
duty cycle for a particular LED string voltage and inductor
combination. The minimum dimming duty cycle is
described in Figure 31 shown below. The first DRV pulse
during the dimming duty cycle reaches the maximum on
time, but the second DRV pulse does not and is turned off by
the current comparator. If the dimming on time (duty cycle)
is reduced, the second DRV pulse is turned off by the DIM
pin voltage, the current comparator is not triggered, and the
NCL30105 latches after 8 dimming cycles.
Figure 31. Minimum Dimming Duty Cycle
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16
NCL30105
Example Calculation
toff [ms] * 0.1214
Rtoff [kW] +
The design begins with the system requirements. The
following are the system requirements of an example
system:
0.1864
Where t is entered in ms and R is calculated in kW.
off
toff
2.5 * 0.1214
Rtoff
+
+ 12.76 kW
Input Voltage (Vin) = 80 V
Number of LEDs = 18
0.1864
R
toff
is selected as 12.7 kW.
The inductor value is calculated using the off time:
LED forward Voltage = 3.33 V
LED string Voltage (V
) = 60 V
LED
V
LED @ toff
dILED
(eq. 3)
L +
LED average current (I
) = 350 mA
LED
LED ripple current (DI
) = 150 mA ( 75 mA)
LED
60 @ 2.5 m
150m
L +
+ 1 mH
Operating frequency = 100 kHz
The switching period is calculated using the target
operating frequency:
The LED peak current (I
) is also the inductor
LED(peak)
peak current and is calculated using the average LED current
and the LED ripple current:
1
fSW
TSW
+
(eq. 1)
dILED
(eq. 4)
I
LED(peak) + ILED
)
2
1
100k
TSW
+
+ 10 ms
150m
2
I
LED(peak) + 350m )
+ 425 mA
The off time (t ) is calculated using the LED string
off
voltage, input voltage, and switching period:
It is critical that the inductor saturation current is greater
than the peak current. Sufficient margin is generally set to
20%. For 20% margin, the inductor should be selected to
have a saturation current greater than 510 mA. The sense
VLED
+ ǒ1 * Ǔ
toff
@ TSW
(eq. 2)
Vin
resistor (R
) value is calculated using the peak current:
sense
60
ǒ
80Ǔ@ 10 ms + 2.5 ms
t
off + 1 *
VILIM
Rsense
+
(eq. 5)
ILED(peak)
To set toff, the following calculation is used based on the
on the approximation of the linear region of the t vs. R
transfer function as shown in Figure 17:
off
toff
1
Rsense
+
+ 2.35 W
0.425
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17
NCL30105
Typical Application Schematic:
Figure 32. Typical Application Schematic
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18
NCL30105
Thermal Considerations:
Layout Tips:
The designer must ensure that the junction temperature of
the NCL30105 remains less than the value of the maximum
operating junction temperature in the Maximum Ratings
Table for the worst−case operating conditions. The
maximum junction temperature is calculated using the
estimated current consumption. The estimated current
consumption is calculated using the following assumptions:
1. The switching frequency is at the maximum of
Careful layout is critical for all switch−mode power
supply design. Successful layout includes special
consideration for noise sensitive pins of the controller IC.
For the NCL30105 the following pins should be carefully
routed:
1. Vcc: This pin requires a ceramic decoupling
capacitor (typically 100 nF) and a electrolytic
capacitor (typically 10 mF) to ensure that IC supply
is constant and decoupled from high frequency
noise generated by switching currents.
500 kHz (f
).
SW(MAX)
2. The Vcc is at the maximum of 22 V (V
)
CC(MAX)
3. The gate of the MOSFET is modeled using a 1 nF
2. toff: This pin requires a resistor connected to
ground to set the off time. It is not recommended
to leave this pin open or shorted to ground to set
the off time. The connection from the toff pin to
the resistor and from the resistor to ground must be
made as short as possible and connected directly to
the NCL30105 GND pin. High noise nodes and
traces must be routed as far away from this pin as
possible.
3. SSTART: A capacitor is connected to this pin to
set the Soft−Start time. The connection from the
SSTART pin to the capacitor and from the
capacitor to ground must be made as short as
possible.
capacitor (C )
g
4. The non−switching bias current is at the maximum
of 1.56 mA (I
)
CC2
Using these assumptions, the current consumption is
calculated:
ǒ
Ǔ
ICC(TJMAX) + Cg @ VCC @ fSW(MAX) ) ICC2
I
CC(TJMAX) + (1 n @ 22 @ 500 k) ) 1.56 m + 12.56 mA
The power dissipation of the NCL30105 is calculated:
P
(TJMAX) + ICC(TJMAX) @ VCC(MAX)
P
(TJMAX) + 12.56 m @ 22 + 276 mW
4. DIM: A decoupling capacitor may need to be
connected to this pin if it coupled to high noise
traces. The connection from the DIM pin to the
capacitor and from the capacitor to ground must be
made as short as possible. The addition of the
capacitor may affect the response of time of the
DIM signal to the DRV output.
The junction temperature is calculated using the
maximum thermal resistance (R
) with the
qJA(MAX)
minimum PCB copper area from the maximum ratings table:
T
J(rise) + P(TJMAX) @ RqJA(MAX)
T
J(rise) + 0.276 @ 178 + 40oC
5. CS: If LEB period is not long enough to ensure
predictable operation, a small RC filter may need
to be connected to this pin. The addition of the RC
filter affects the current set point accuracy.
6. DRV: The trace that connects the DRV pin to the
MOSFET must be made as short as possible to
reduce the parasitic inductance of the trace. The
DRV pin switches high currents and the parasitic
inductance can cause higher than expected
voltages to be applied to the gate of the MOSFET.
A small resistor is recommended to be connected
in series with the DRV pin to the gate. The resistor
reduces the effect of the parasitic inductance. The
addition of the resistor may affect the switching
losses of the MOSFET.
Assuming a maximum ambient temperature of 70°C
ambient
(T
), the maximum junction temperature is calculated:
T
J(MAX) + TJ(rise) ) Tambient
J(MAX) + 49 ) 70 + 119oC
T
Since this is less than the T
parameter with sufficient
SHDN
margin, the design is acceptable.
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19
NCL30105
Recommended Layout:
Figure 33. Top Layout
Figure 34. Bottom Layout
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20
NCL30105
The critical components for layout are the following:
1. R2 (R ): This resistor sets the off time. The
minimized. The recommended minimum value for
this capacitor is 100 nF.
toff
placement of this resistor is such that the distance
to the pin and IC ground is minimized. The
footprints R1 and R3 are optional to increase the
precision of the resistance value.
3. C8 (C ): This capacitor sets the soft−start
SSTART
time. The placement of this capacitor is such that
the distance to the pin and IC ground is
2. C5 (C
): This is the Vcc supply decoupling
minimized.
VCC
capacitor. The placement of this capacitor is such
that the distance to the pin and IC ground is
The layout includes options to use a surface mount
inductor (footprint L2) and MOSFET (footprint M2).
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21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
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