NB4L6254MNG [ONSEMI]
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer;
| 型号： | NB4L6254MNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer |
| 文件： | 总11页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4L6254
2.5V / 3.3V Differential
LVPECL 2x2 Clock Switch
and Low Skew Fanout
Buffer
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MARKING DIAGRAMS*
Description
The NB4L6254 is a differential 2x2 clock switch and drives
precisely aligned clock signals through its LVPECL fanout buffers. It
employs a fully differential architecture with bipolar technology,
offers superior digital signal characteristics, has very low clock output
skew and supports clock frequencies from DC up to 3.0 GHz.
The NB4L6254 is designed for the most demanding, skew critical
differential clock distribution systems. Typical applications for the
NB4L6254 are clock distribution, switching and data loopback
systems of high−performance computer, networking and
telecommunication systems, as well as on−board clocking of OC−3,
OC−12 and OC−48 communication systems. In addition, the
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL
fanout buffer.
NB4L
6254
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
1
NB4L6254
AWLYYWWG
G
32
1
QFN32
MN SUFFIX
CASE 488AM
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power
supply.
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
Features
= Work Week
G or G = Pb−Free Package
• Maximum Clock Input Frequency, 3 GHz
• Maximum Input Data Rate, 3 Gb/s
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
• Differential LVPECL Inputs and Outputs
• Low Output Skew: 50 ps Maximum Output−to−Output Skew
• Synchronous Output Enable Eliminating Output Runt Pulse
V
CC
Bank A
0
QA0
QA0
Generation and Metastability
CLK0
CLK0
• Operating Range: Single 3.3 V or 2.5 V Supply
QA1
QA1
QA2
QA2
V
CC
= 2.375 V to 3.465 V
1
• LVCMOS Compatible Control Inputs
• Packaged in LQFP−32
• Fully Differential Architecture
• −40°C to 85°C Ambient Operating Temperature
• These are Pb−Free Devices*
V
CC
Bank B
0
QB0
QB0
QB1
QB1
QB2
QB2
CLK1
CLK1
1
SEL0
SEL1
OEA
OEB
SYNC
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
March, 2009 − Rev. 3
NB4L6254/D
NB4L6254
QA0 QA0
V
QA1 QA1
V
QA2
QA2
CC
CC
32 31
30 29 28 27
26 25
V
24
23
V
CC
1
2
3
CC
GND
GND
OEA
SEL1
CLK1
22
21
20
CLK0
4
5
NB4L6254
CLK1
CLK0
SEL0
OEB
GND
6
7
19
18
17
GND
V
V
CC
CC
8
9
10
11 12
13 14 15 16
QB0 QB0
V
QB1 QB1
V
QB2
QB2
CC
CC
Figure 2. 32−Lead LQFP Pinout (Top View)
Exposed Pad
(EP)
QA0 QA0
V
QA1 QA1
V
QA2
QA2
CC
CC
32
31 30
29 28
27 26
25
V
CC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
V
CC
GND
GND
OEA
SEL1
CLK1
CLK0
NB4L6254
CLK1
CLK0
SEL0
OEB
GND
18
17
GND
V
CC
V
CC
9
10
11 12 13 14 15 16
QB0 QB0
V
QB1 QB1
V
QB2
QB2
CC
CC
Figure 3. 32−Lead QFN Pinout (Top View)
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2
NB4L6254
Table 1. PIN DESCRIPTION
Pin Name
CLK0, CLK0
CLK1, CLK1
OEAb, OEB
SEL0, SEL1
I/O
Description
LVPECL Input
LVPECL Input
LVCMOS Input
LVCMOS Input
LVPECL Output
Differential reference clock signal input 0.
Differential reference clock signal input 1.
Output Enable
Clock Switch Select
QA[0−2], QA[0−2]
QB[0−2], QB[0−2]
Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W
resistor to V – 2.0 V.
CC
GND
Power Supply
Power Supply
Negative Supply Voltage
V
CC
Positive supply voltage. All V pins must be connected to the positive power supply
for correct DC and AC operation.
CC
EP
The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of the package. THe exposed pad must be attached
to a heat−sinking conduit. The pad is electrically connected to GND.
Table 2. FUNCTION TABLE
Control
Default
0
1
OEA
0
QA[0−2], QA[0−2] are active. Deassertion of
OEA can be asynchronous to the reference
clock without generation of output runt pulses
QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
OEB
0
QB[0−2], QB[0−2] are active. Deassertion of
OEB can be asynchronous to the reference
clock without generation of output runt pulses
QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
SEL0,
SEL1
00
Refer to Table 3
Refer to Table 3
Table 3. CLOCK SELECT CONTROL
SEL0
SEL1
CLK0 Routed To
CLK1 Routed to
Application Mode
1:6 Fanout of CLK0
0
0
1
1
0
1
0
1
QA[0:2] and QB[0:2]
−
−
QA[0:2] and QB[0:2]
QB[0:2]
1:6 Fanout of CLK1
Dual 1:3 Buffer
QA[0:2]
QB[0:2]
QA[0:2]
Dual 1:3 Buffer (Crossed)
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3
NB4L6254
Table 4. ATTRIBUTES
Characteristics
Value
37.5 kW
75 kW
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Human Body Model
> 2000 V
> 200 V
Machine Model
Latchup Immunity
Cin, inputs
>200 mA
4.0 pF (TYP)
Moisture Sensitivity (Note 1)
LQFP−32
QFN32
Level 2
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
336
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Positive Power Supply
Condition
Condition
Rating
Unit
V
V
CC
−0.3 v V v 3.6
CC
V
IN
DC Input Voltage
−0.3 v V v V
V
IN
CC
+ 0.3
V
OUT
DC Output Voltage
−0.3 v V
v V
V
OUT
CC
+ 0.3
I
DC Input Current
$20
mA
IN
I
LVPECL DC Output Current
Continuous
Surge
$50
mA
mA
out
100
T
Operating Temperature Range
Storage Temperature Range
LQFP−32
−40 to +85
°C
°C
A
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient)
(Note 3)
0 lfpm
500 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
2S2P (Note 3)
LQFP−32
12 to 17
°C/W
JC
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
°C
JC
T
Wave Solder
Pb−Free
265
sol
V
TT
Output Termination Voltage
V
CC
– 2.0, TYP
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power); MIL−SPEC 883E Method 1012.1.
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NB4L6254
Table 6. DC CHARACTERISTICS V = 2.375 V to 3.465 V, GND = 0 V, T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
mA
mV
POWER SUPPLY CURRENT
I
Power Supply Current (Outputs Open)
60
85
GND
LVPECL CLOCK OUTPUTS
V
LVPECL Output HIGH Voltage (Notes 4, 5)
LVPECL Output LOW Voltage (Notes 4, 5)
V
− 1145
V
V
− 1020
V
– 895
OH
OL
CC
CC
CC
V
CC
V
CC
= 3.3 V
= 2.5 V
2155
1355
2280
1480
2405
1605
V
V
− 1945
− 1770
V − 1600
CC
mV
CC
CC
V
CC
V
CC
= 3.3 V
= 2.5 V
1355
555
1530
730
1700
900
CLOCK INPUTS
V
V
Dynamic Differential Input Voltage (Clock Inputs)
0.1
1.0
1.3
V
V
PP
Differential Cross−point Voltage (Clock Inputs)
V
− 0.3
CMR
CC
LVCMOS CONTROL INPUTS
V
IH
V
IL
Output HIGH Voltage (LVTTL/LVCMOS)
Output LOW Voltage (LVTTL/LVCMOS)
2.0
V
V
0.8
I
IH
Input Current V = V or V = GND
−100
+100
mA
IN
CC
IN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL Outputs loaded with 50 W termination resistors to V = V – 2.0 V for proper operation.
TT
CC
5. LVPECL Output parameters vary 1:1 with V
.
CC
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NB4L6254
Table 7. AC CHARACTERISTICS V = 2.375 V to 3.465 V, GND = 0 V, T = −40°C to +85°C (Note 6)
CC
A
Symbol
Characteristic
Min
0.3
1.2
0
Typ
Max
Unit
V
V
INPP
V
CMR
Differential Input Voltage (Peak−to−Peak)
Differential Input Cross−Point Voltage (Clock Inputs)
Clock Input Frequency
1.3
V
− 0.3
V
CC
f
IN
3.0
GHz
V
V
Differential Output Output Voltage Amplitude (Peak−to−Peak)
OUTPP
(Note 7)
f
O
f
O
f
O
< 1.1 GHz
< 2.5 GHz
< 3.0 GHz
0.45
0.35
0.2
0.70
0.55
0.35
f
t
t
Output Clock Frequency Range
0
3.0
GHz
ps
CLKOUT
Propagation Delay CLKx to Qx (Differential Configuration)
360
485
610
pd
Within Device Output−to−Output Skew (Differential Configuration)
Device−to−Device Skew
Output Pulse Skew (Duty Cycle Skew) (Note 8)
25
30
10
50
250
60
ps
skew
DCO
Output CLOCK Duty Cycle (DC Ref = 50%)
(Note 9)
t
t
<100 MHz
< 800 MHz
49.4
45.2
50.6
54.8
%
REF
REF
t
CLOCK Random Jitter (RMS) (SEL0 0 SEL1) (Note 10)
Output Rise/Fall Times (Note 11) CLKx / CLKx
Output Disable Time, T = CLK period
0.3
0.8
ps
ps
ns
ns
JIT
t , t
r
50
130
300
f
t
2.5 T + t
3.5 T + t
PD
PDL
PD
tPLD
Output Enable Time, T = CLK period
3 T + t
4 T + t
PD
PD
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. LVPECL Outputs loaded with 50 W to V − 2.0V.
CC
7. V
MIN = 0.1 V @ +85°C, f < 3.0 GHz.
OUTPP
O
8. Output Pulse Skew is the absolute difference of the propagation delay times: |t
− t
PHL
|
PLH
9. DCO
= 43.2%/59.2% @ +85°C.
MIN/MAX
= 1.6 ps @ 85°C, 3.0 V
10.t
JITMAX
11. Measured 20% to 80%
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6
NB4L6254
CLKX
CLKX
50%
OEX
t
(OEX to QXn)
PDL
t
(OEX to QXn)
PLD
QXn
QXn
Outputs Disabled
Figure 4. Output Disable / Enable Timing
800
700
600
500
400
300
200
100
0
0
1
2
3
f , CLOCK OUTPUT FREQUENCY (GHz)
OUT
Figure 5. Output Voltage Amplitude (VOUTPP) versus Clock Output Frequency at Ambient Temperature (Typical)
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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NB4L6254
Example Configurations
SEL0
SEL1
Switch Configuration
System Loopback
System A
System B
CLK0
3
3
0
0
1
1
0
1
0
1
CLK1
Line Loopback
Transmit/Receive Operation
System and Line Loopback
SEL0
SEL1
APPLICATIONS INFORMATION
Figure 7. 2 x 2 Clock Switch
Maintaining Lowest Device Skew
The NB4L6254 guarantees low output−output bank skew
at 50 ps and a part−to−part skew of 250 ps. To ensure low
skew clock signals in the application, both outputs of any
differential output pair need to be terminated identically,
even if only one output is used. When fewer than all nine
output pairs are used, identical termination of all output pairs
within the output bank is recommended. If an entire output
bank is not used, it is recommended to leave all of these
outputs open and unterminated. This will reduce the device
power consumption while maintaining minimum output
skew.
SEL0
SEL1
Switch Configuration
0
0
CLK0 Clocks System A and
System B
0
1
1
1
0
1
CLK1 Clocks System A and
System B
CLK0 Clocks System A and CLK1
Clocks System B
CLK1 Clocks System B and CLK1
Clocks System A
Power Supply Bypassing
The NB4L6254 is a mixed analog/digital product. The
differential architecture of the NB4L6254 supports low
noise signal operation at high frequencies. In order to
CLK0
CLK1
maintain its superior signal quality all V pins should be
CC
bypassed by high−frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally
generated switching noise on the supply pins cross the series
resonant port of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the noise bandwidth.
0
0
SEL0
SEL1
Figure 8. 1:6 Clock Fanout Buffer
Transmitter
QAn
System−Tx
System−Rx
CLK0
V
CC
V
CC
SEL0
SEL1
NB4L6254
33 − 100 nF
0.1 nF
QBn
CLK1
Receiver
Figure 10. VCC Power Supply Bypass
Figure 9. Loopback Device
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NB4L6254
ORDERING INFORMATION
Device
†
Package
Shipping
NB4L6254FAG
LQFP−32
(Pb−Free)
250 Units / Tray
2000 / Tape & Reel
74 Units / Rail
NB4L6254FAR2G
NB4L6254MNG
LQFP−32
(Pb−Free)
QFN32
(Pb−Free)
NB4L6254MNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB4L6254
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T-U
Z
32
25
1
AE
AE
−U−
−T−
P
B
V
B1
DETAIL Y
BASE
METAL
DETAIL Y
V1
17
8
N
9
4X
−Z−
0.20 (0.008) AC T-U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
A
A1
B
2. CONTROLLING DIMENSION:
MILLIMETER.
0.138 BSC
0.276 BSC
0.138 BSC
7.000 BSC
3.500 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
B1
C
1.400
1.600 0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.450 0.012
1.450 0.053
0.400 0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150 0.002
0.200 0.004
0.750 0.018
0.006
0.008
0.030
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160 0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
0.150
0.250 0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
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10
NB4L6254
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
L
EXPOSED PAD
32 X
K
16
9
32 X
17
SOLDERING FOOTPRINT*
8
5.30
E2
3.20
1
24
32 X
0.63
25
32
32 X
b
e
0.10
0.05
C
A
B
3.20 5.30
C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NB4L6254/D
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