NB4L7210MNTXG_技术文档

NB4L7210

2.5V/3.3V Differential 2x10

Crosspoint Clock Driver

with SDI Programmable

Output Selects

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The NB4L7210 is a Clock input crosspoint fanout distribution

device selecting between one of two input clocks on each of the 10

differential output pairs. A 10 Bit Serial Data Interface programs each

output MUX to asynchronously select either Input clock.

CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or

LVDS signal levels and incorporate an internal 50 ohms on die

termination resistors. SCLK, SDATA, and SLOAD input can accept

single ended LVPECL, CML, LVCMOS, LVTTL signals levels.

SCLK and SDATA inputs operate up to 20 MHz. SLOAD input

loads and latches the output select data. The SDATAOUT pin permits

cascading multiple devices. Outputs are optimized for minimal

output−to−outputskew and low jitter.

MARKING

DIAGRAM*

52

1

NB4L

7210

1

52

QFN52

MN SUFFIX

CASE 485M

AWLYYWWG

NB4L7210

= Device Code

= Assembly Site

= Wafer Lot

A

WL

YY

WW

G

Features

= Year

= Work Week

= Pb−Free Package

• Typical Input Clock Frequency > 2 GHz

• 200 ps Typical Rise and Fall Times

• 800 ps Typical Propagation Delay

• Output to Output Skew 150 ps

*For additional marking information, refer to

Application Note AND8002/D.

• Additive RMS Phase Jitter of 0.2 ps

• Operating Range: V = 2.375 V to 3.6 V with V = 0 V

CC

EE

Q0

• Differential LVPECL Output Level (Typ 700 mV Peak−to−Peak)

• Low Profile 8x8 mm, 52 QFN Package

• 10GE WAN: 155.52 MHz / 622.08 MHz

• 10GE LAN: 161.1328 MHz

Q0b

VTCLK0

CLK0

CLK0b

Q1

Q1b

VTCLK0b

• These are Pb−Free Devices*

Q8

VTCLK1

CLK1

CLK1b

Q8b

VTCLK1b

Q9

Q9b

VCC

VEE

SCLK

SDATA

SLOAD

SDATAOUT

Figure 1. Functional Block Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

1

Publication Order Number:

August, 2009 − Rev. 7

NB4L7210/D

NB4L7210

Exposed Pad (EP)

52 51 50 49 48 47 46 45 44 43 42 41 40

GND

SLOAD

VTCLK0

1

2

3

39 VCC3

38 Q3

37 Q3

CLK0

4

5

6

7

36 VCC4

35 Q4

VTCLK0

GND

34 Q4

NB4L7210

33 GND

VTCLK1

CLK1

8

9

32 Q5

31 Q5

CLK1 10

30 VCC5

29 Q6

VTCLK1 11

SDATA 12

GND 13

28 Q6

27 VCC6

14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 2. Pin Configuration (Top View)

Table 1. PIN DESCRIPTION

Name

I/O

Description

1, 7, 13, 25, 26, 33,

40, 41

GND

Supply

Negative Supply pins must be all externally connected to a power

supply to guarantee proper operation.

2

SLOAD

LVCMOS, LVTTL

Serial Load and Latch control input pin. Defaults LOW when float-

^{ing open}.

3, 6, 8, 11

VTCLK0, VTCLK0,

VTCLK1, VTCLK1

Termination−

Internal 50 Ohms Termination Resistor connection Pins. In the

differential configuration when the input termination pins are con-

nected to the common termination voltage.

4, 9

5, 10

12

CLK0, CLK1

SDATA

Differential LVPECL, CLOCK Input (TRUE). If no signal is applied then the device may

CML, or LVDS be susceptible to self oscillation.

Differential LVPECL, CLOCK Input (INVERT). If no signal is applied then the device

CML, or LVDS

may be susceptible to self oscillation.

LVCMOS, LVTTL

Serial Data input pin (for BITS 0:9, a “0” selects CLK1, “1” selects

CLK 0). Defaults LOW when floating open.

14

SCLK

LVCMOS, LVTTL

Supply

Serial Load Clock input pin. Defaults LOW when floating open.

15, 16, 19, 22, 27,

30, 36, 39, 44, 47,

50, 51

VCC, VCC9, VCC8,

VCC7, VCC6, VCC5,

VCC4, VCC3, VCC2,

VCC1, VCC0

Positive Supply pins must be all externally connected to a power

supply to guarantee proper operation.

17, 20, 23, 28, 31,

34, 37, 42, 45, 48

Q[9−0]

LVPECL

Output (INVERT)

18, 21, 24, 29, 32,

35, 38, 43, 46, 49

Q[9−0]

Output (TRUE)

52

SDATAOUT

EP

LVCMOS, LVTTL

GND

Serial Data output pin for cascade

Exposed Pad

Exposed Pad. The thermally exposed pad (EP) on package bot-

tom (see case drawing) must be attached to a sufficient heat−

sinking conduit for proper thermal operation and must be connec-

ted to GND.

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2

NB4L7210

10 MUXes

Output Qx

BIT

9

8

7

6

5

4

3

2

1

0

SLOAD

SDATA

SCLK

10 Bit LATCH

10 Bit SHIFT

SDATA REGISTER

DATA BIT VALUE

9

MSB

LSB

SDATAOUT

0

1

Selects CLK1 / CLK1

Selects CLK0 / CLK0

SDATA 10 BIT REGISTER

10 Bit SHIFT REGISTER

(A)

(B)

(C)

Figure 3. Serial Data Interface

Table 2. ATTRIBUTES

Characteristic

Value

Input Default State Resistors

ESD Protection

None

> 2 kV

Level 1

Human Body Model

Moisture Sensitivity Pb−Free Package (Note 1)

QFN−52

Flammability Rating

Transistor Count

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

2027

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

GND = 0 V

Condition 2

Rating

6.0

Unit

V

CC

V

I

Positive Power Supply

Positive Input

GND−0.3 ≤ V ≤ V

V

I

CC

I

IN

Input Current Through R (50 W Resistor)

Static

Surge

35

70

mA

T

V

Differential Input Voltage

Output Current (Q / Q)

2.5

V

INPP

I

Continuous

Surge

25

50

mA

OUT

T

Operating Temperature Range

QFN−52

−40 to +85

°C

A

T

stg

Storage Temperature Range

−65 to +150

Thermal Resistance (Junction−to−Ambient) (Note 2)

0 lfpm

500 lfpm

QFN−52

25

19.6

°C/W

q

JA

Thermal Resistance (Junction−to−Case)

2S2P (Note 2) QFN−52

21

°C/W

°C

q

JC

T

sol

Wave Solder

Pb−Free

265

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).

3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

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3

NB4L7210

Table 4. DC CHARACTERISTICS (V = 2.375 V to 3.6 V, V = 0 V, T = −40°C to +85°C (Note 4))

CC

EE

A

Symbol

Characteristic

Min

110

40

Typ

150

50

Max

200

60

Unit

mA

W

I

GND Supply Current (All Outputs Loaded)

Internal Input Termination Resistor

Output HIGH Voltage

EED

R

TIN

OH

OL

V

−1145

V

−1020

−1820

8

V −895

CC

mV

mA

CC

Output LOW Voltage

V

−1945

V

−1695

CC

I

IH

I

IL

Input HIGH Current (VTx/VTx open)

Input LOW Current (VTx/VTx open)

150

0.1

mA

DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 5, 6)

V

Input Threshold Reference Voltage Range (Note 5)

Single−Ended Input HIGH Voltage

Single−Ended Input LOW Voltage

GND +950

+ 150

V

− 150

mV

th

CC

V

th

V

CC

IH

GND

300

V − 150

th

IL

Single−Ended Input Amplitude

V

CC

INAMP

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8)

V

CMR

V

IHD

V

ILD

V

ID

Input Common Mode Range

Differential Input HIGH Voltage

Differential Input LOW Voltage

GND +950

+ 75

V

− 75

mV

CC

V

CC

CMR

GND

V

CMR

− 75 mV

Differential Input Voltage (V

− V

)

150

2400

mV

IHD

ILD

LVCMOS/LVTTL INPUTS (SCLK, SDATA, SLOAD)

V

IH

V

IL

Input HIGH Voltage

Input LOW Voltage

2.0

V

CC

GND

0.8

LVCMOS/LVTTL OUTPUTS (SDATAOUT)

V

OH

V

OL

Output HIGH Voltage @ I = −1.0 mA, R = 20 kW to GND

2.0

3.2

V

OH

L

Output LOW Voltage @ I = 1.0 mA, R = 20 kW to GND

0.25

0.5

OL

L

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. Input and Output parameters vary 1:1 with V . Outputs loaded with 50 W to V − 2.0 V (See Figure 16) except SDATAOUT.

CC

5. V is applied to the complementary input when operating in single−ended mode.

th

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4

NB4L7210

Table 5. AC CHARACTERISTICS (V = 2.375 V to 3.6 V, GND = 0 V, T = −40°C to +85°C (Note 6))

CC

A

Symbol

Characteristic

Min

Typ

Max

Unit

V

Output Voltage Amplitude @ V

(See Figure 9)

f = 100 MHz

in

650

530

800

790

875

960

mV

OUTPP

INPPmin

f

= 1 GHz

in

t

,

Propagation Delay to (See Figure 9)

PLH

PHL

CLK/CLK to Qx/Qx (Note 7)

610

6.5

725

20

875

30.8

ps

ns

SCLK to SDATAOUT Measured at 1.5 V

t

Duty Cycle Skew (Note 8)

Within −Device Skew

Device to Device Skew (Note 8)

−5

0

2

5

20

10

35

200

ps

SKEW

ts

Setup Time

ps

SDATA to SCLK Measured at 1.5 V

SCLK to SLOAD+ Measured at 1.5 V

−150

1000

−115

Th

Hold Time

SDATA to SCLK

SLOAD

325

2.0

345

365

ps

ns

fs

PWmin Minimum Pulse Width

t

(Ø)

RMS Phase Jitter, Integration Range 12 KHz to 20 MHz

JIT

@155.52 MHz

@ 622.08 MHz

See Fig 10

See Fig 11

t

TIE Rj (10,000 Cycles)

@155.52 MHz

@ 622.08 MHz

1.7

0.63

3.9

ps

JITTER

Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)

V

INPP

Input Voltage Swing/Sensitivity

(Differential Configuration, measured Single−ended on each input)

150

750

1200

mV

t , t

Output Risetime and Falltime

Qx/Qx (20% to 80%)

r

f

120

0.88

185

10

260

15

ps

ns

SDATAOUT (0.8 V − 2.0 V)

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

6. Measured by forcing V

(Typ 750 mV ) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50 W to V − 2.0 V (See Figure 16).

INPP

P

C

SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND.

7. Measured from the input pair crosspoint to each single output pair crosspoint.

8. Duty cycle skew is measured between differential outputs using the deviations of the sum of T − and T +.

pw

9. 155.52 MHz @ 750 mV input on measured output, 161.13 MHz @ 850 mV input on all other others.

PP

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5

NB4L7210

Programming Application Information for the SDI

As shown in Figure 4, the SLOAD pulse Low to HIGH

level transition transfers the data from the SHIFT register to

the LATCH register. The SLOAD Pulse HIGH to LOW level

transition will lock the new MUX select data values into the

LATCH register. An initial program load cycle is

recommended since the 10 bit register will power−up in a

random state.

SDATAOUT pin outputs the shift register LSB bit with

each SCLK rising edge for porting to the SCLK of the next

device in a cascade interconnect only. Cascade operation

will require a complete data register loading of all devices

to purge the shift registers of power up random state bits.

To use the serial port, the SCLK signal samples the

information on the SDATA line and indexes the data into a

10 bit shift register (See Figure 3). The register shifts once

per rising edge of the SCLK input. The serial input SDATA

bits must each meet setup and hold timing to their respective

SCLK rising edge as specified in the AC Characteristics

section of this document. (See Figure 4)

The SDATA Least Significant Bit (LSB), D0, is indexed

in first and the Most Least Significant Bit (LSB), D9, is

indexed in last. A Pulse on the SLOAD pin after the SHIFT

register is fully indexed (10 clocks) will load and lock the

MUX select data values into the Latch register (See Figure

4). For each MUX (Output Q[0:9], a “0” bit value selects

CLK1 and a “1” bit value selects CLK 0 (see Figure 3, “C”).

SDATA to SCLOCK

t

s

t

h

C0

SCLK

C1

D1

C2

D2

C3

D3

C4

D4

C5

C6

C9

C7

D7

C8

SDATA

D5

D9

D6

D8

D0

LSB

MSB

SLOAD

SDATA to SLOAD

t

s

PW

min

Figure 4. Serial Interface Timing Diagram

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6

NB4L7210

CLK

Qx

V

IH

V

IL

th

CLK

V

th

Figure 5. Differential Input Driven Single−Ended V_thSchema

V

CC

thmax

V

IHmax

V

ILmax

CLKx

V

th

V

IHmin

V

thmin

ILmin

CLKx

GND

Figure 6. Differential Input Driven Single−Ended V_thDiagram

CLK

Q

CLK

Q

Figure 7. Differential Inputs Driven Differentially

V

CC

V

IH(MAX)

IL

IH

V

CMR

V

INPP

= V − V

IHD ILD

V

IL

V

IH

IL(MIN)

GND

Figure 8. V_CMRDiagram

CLK

V

= V − V

IH IL

INPP

CLK

Q

= V (Q) − V (Q)

OUTPP

OH

OL

Q

t

PHL

t

PLH

Figure 9. AC Reference Measurement

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7

NB4L7210

Figure 10. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase

Noise with a 155.52 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 100 kHz

offset. From 100 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS.

Figure 11. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase

Noise with a 622.08 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 50 kHz

offset. From 50 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS.

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8

NB4L7210

V

CC

V

CC

CLK

Z = 50 W

50 W

LVTTL/

LVCMOS

Driver

V

TCLK

No Connect

NB4L7210

V

TCLK

Recommended V

Values

REF

V

REF

V

REF

CLK

60 pF

LVCMOS

V − V

CC EE

2

V

EE

V

CC

LVTTL 1.5 V

Figure 12. LVCMOS/LVTTL to NB4L7210 Receiver Interface

V

CC

V

CC

CLK

Z = 50 W

50 W

V

TCLK

LVPECL

Driver

NB4L7210

V

TCLK

Recommended R Values

T

V

CC

R

T

CLK

R

T

R

T

3.3 V 120 W

2.5 V 50 W

V

EE

V

EE

V

EE

Figure 13. LVPECL to NB4L7210 Receiver Interface

V

CC

V

CC

50 W 50 W

CML Driver

Q

CLK

Z = 50 W

50 W

V

TCLK

NB4L7210

V

CC

V

CC

TCLK

Z = 50 W

Q

CLK

V

EE

V

EE

Figure 14. CML to NB4L7210 Interface

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9

NB4L7210

V

CC

V

CC

CLK

Z = 50 W

50 W

V

TCLK

LVDS

Driver

NB4L7210

TCLK

Z = 50 W

CLK

V

EE

V

EE

Figure 15. LVDS to NB4L7210 Receiver Interface

Z = 50 W

o

Q

D

Receiver

NB4L7210

Z = 50 W

o

Q

D

50 W

V

TT

V

TT

= V − 2.0 V

CC

Figure 16. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

ORDERING INFORMATION

†

Device

Package

Shipping

NB4L7210MNG

QFN−52

(Pb−Free)

46 Units / Rail

NB4L7210MNTXG

QFN−52

(Pb−Free)

2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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10

NB4L7210

PACKAGE DIMENSIONS

52 PIN QFN 8x8

CASE 485M−01

ISSUE B

NOTES:

D

A

B

1. DIMENSIONING AND TOLERANCING

PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION:

MILLIMETERS

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED

BETWEEN 0.25 AND 0.30 MM FROM

TERMINAL.

PIN ONE

REFERENCE

4. COPLANARITY APPLIES TO THE

EXPOSED PAD AS WELL AS THE

TERMINALS.

E

MILLIMETERS

DIM MIN

MAX

1.00

0.05

0.80

2X

A

A1

A2

A3

b

0.80

0.00

0.60

0.15

C

0.20 REF

2X

0.18

0.30

6.80

D

8.00 BSC

0.15

C

D2

E

6.50

8.00 BSC

A2

E2

e

6.80

0.10

0.08

C

0.50 BSC

A

K

0.20

0.30

---

L

0.50

A3 REF

26

A1

SEATING PLANE

C

D2

14

27

13

L

52 X

E2

39

1

52

40

K

52 X

b

NOTE 3

52 X

e

0.10 C A

0.05

B

C

The products described herein (NB4L7210), may be covered by U.S. patents including 6,362,644. There may be other patents pending.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NB4L7210/D

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11


型号：	NB4L7210MNTXG
厂家：	ONSEMI
描述：	2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects 2.5V / 3.3V的差分2×10交叉点时钟驱动器与SDI可编程输出选择时钟驱动器
文件：	总11页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NB4L7210MNTXG [ONSEMI]

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