NB4L858MFAG [ONSEMI]
2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination; 2.5V / 3.3V ， 3 GHz的双差分时钟/数据2×2交叉点开关与CML输出和内部终端
| 型号： | NB4L858MFAG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination |
| 文件： | 总10页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4L858M
2.5V/3.3V, 3 GHz Dual
Differential Clock/Data 2x2
Crosspoint Switch with
CML Output and Internal
Termination
http://onsemi.com
MARKING
DIAGRAM*
Description
The NB4L858M is a high−bandwidth low voltage fully differential
dual 2 x 2 crosspoint switch with CML outputs that is suitable for
applications such as SDH/SONET DWDM and high speed switching
applications. Design technique minimizes jitter accumulation,
crosstalk, and signal skew which make this device ideal for
loop−through and protection channel switching application. Each
2 x 2 crosspoint switch can fan out and/or multiplex up to 3 Gb/s data
and 3 GHz clock signals.
NB4L
858M
AWLYYWW
LQFP−32
FA SUFFIX
CASE 873A
32
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Differential inputs incorporate a pair of internal 50 W termination
resistors in a center−tapped configuration (V
Pins) and can accept
TDx
LVPECL (Positive ECL) or CML input signal without any external
component. This feature provides transmission line termination
on−chip, at the receiver end, eliminating external components.
Differential 16 mA CML output provides matching internal 50 W
terminations, and 400 mV output swings when externally terminated,
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SELA0
50 W to V
.
CC
0
The SELECT inputs are single−ended and can be driven with either
LVCMOS or LVTTL input levels. The device is housed in a low
profile 7 x 7 mm 32−pin LQFP package.
DA0
50W
QA0
QA0
VTDA0
DA0
A0
50W
1
Features
SELA1
• Maximum Input Clock Frequency 3 GHz
• Maximum Input Data Frequency 3 Gb/s
• 350 ps Typical Propagation Delay
• 80 ps Typical Rise and Fall Times
• 12 ps Channel to Channel Skew
• 0.5 ps RMS Jitter
0
DA1
50W
50W
QA1
QA1
A1
VTDA1
DA1
1
0
SELB0
• 5 ps Deterministic Jitter @ 2.5 Gb/s
DB0
• Operating Range: V = 2.3V to 3.6 V with GND = 0 V
50W
50W
CC
QB0
QB0
VTDB0
B0
• CML Output Level (400 mV Peak−to−Peak Output), Differential
DB0
Output
1
0
• These are Pb−Free Devices
SELB1
DB1
QB1
QB1
50W
50W
B1
VTDB1
DB1
1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 9
NB4L858M/D
NB4L858M
GND
V
QA0 QA0
V
QA1 QA1
V
CC
CC
CC
24
23
22
21
20
19
18
17
DA0
VTDA0
DA0
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
CC
QB1
QB1
SELA1
V
CC
LQFP−32
DA1
QB0
QB0
VTDA1
DA1
V
CC
SELA0
GND
1
2
3
4
5
6
7
8
DB1 VTDB1 DB1 SELB0 DB0 VTDB0 DB0 SELB1
Figure 1. Pin Configuration (Top View)
Table 1. TRUTH TABLE
SELA0/SELB0
SELA1/SELB1
QA0/QB0
DA0/DB0
DA0/DB0
DA1/DB1
DA1/DB1
QA1/QB1
DA0/DB0
DA1/DB1
DA0/DB0
DA1/DB1
Function
L
L
L
H
L
1:2 Fanout or Redundant Distribution
Quad Repeater or Crosspoint Switch
Quad Repeater or Crosspoint Switch
1:2 Fanout or Redundant Distribution
H
H
H
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2
NB4L858M
Table 2. PIN DESCRIPTION
Pin
1
Name
DB1
I/O
LVPECL, CML Input Channel B1 positive signal input.
Internal 100 W center−tapped termination pin for channel B1.
LVPECL, CML Input Channel B1 negative signal input.
LVTTL / LVCMOS Channel B0 Output Select. See Table 1.
LVPECL, CML Input Channel B0 positive signal input.
Description
2
VTDB1
DB1
−
3
4
SELB0
DB0
5
6
VTDB0
DB0
−
Internal 100 W center−tapped termination pin for channel B0.
7
LVPECL, CML Input Channel B0 negative signal input.
8
SELB1
GND
LVTTL / LVCMOS
−
Channel B1 output select. See Table 1.
9,24
Supply ground. All GND pins must be externally connected to power supply to
guarantee proper operation.
10, 13, 16, 17, 20, 23
V
CC
−
Positive Supply. All V pins must be externally connected to power supply to
guarantee proper operation.
CC
11
12
14
15
18
19
21
22
QB0
QB0
QB1
QB1
QA1
QA1
QA0
QA0
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
Channel B0 negative signal output. Typically terminated with 50 W resistor to
V
CC.
Channel B0 positive signal output. Typically terminated with 50 W resistor to
V
CC
Channel B1 negative signal output. Typically terminated with 50 W resistor to
V
CC
.
Channel B1 positive signal output. Typically terminated with 50 W resistor to
V
CC
.
Channel A1 negative signal output. Typically terminated with 50 W resistor to
V
CC
.
Channel A1 positive signal output. Typically terminated with 50 W resistor to
V
CC
.
Channel A0 negative signal output. Typically terminated with 50 W resistor to
V
CC
.
Channel A0 positive signal output. Typically terminated with 50 W resistor to
V
CC
.
25
26
27
28
29
30
31
32
DA0
VTDA0
DA0
LVPECL, CML Input Channel A0 positive signal input.
−
Internal 100 W center−tapped termination pin for channel A0.
LVPECL, CML Input Channel A0 negative signal input.
SELA1
DA1
LVTTL
Channel A1 output select. See Table 1.
LVPECL, CML Input Channel A1 positive signal input.
VTDA1
DA1
−
Internal 100 W center−tapped termination pin for channel A1.
LVPECL, CML Input Channel A1 negative signal input.
SELA0
LVTTL
Channel A0 output select. See Table 1.
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NB4L858M
Table 3. Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2000 V
>110 V
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
32−LQFP
Level 2
UL 94 V−0 @ 0.125 in
380
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
Rating
3.8
Unit
V
V
V
V
CC
I
Positive Input
GND = 0 V
GND v V v V
3.8
V
I
CC
Differential Input Voltage
|D − D|
3.8
V
INPP
I
IN
Input Current Through Internal R (50 W
Resistor)
Static
Surge
45
80
mA
mA
T
I
Output Current
Continuous
Surge
25
80
mA
mA
OUT
T
Operating Temperature Range
Storage Temperature Range
LQFP−32
−40 to +85
°C
°C
A
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
2S2P (Note 2)
32 LQFP
12 to 17
265
°C/W
°C
JC
T
sol
Wave Solder
Pb−Free <3 sec @ 260°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
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NB4L858M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS V = 2.3 V to 3.6 V, GND = 0 V T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
Max
190
Unit
mA
mV
I
Power Supply Current
130
CC
V
outdiff
CML Differential Output Swing (Note 3) No Load
640
800
400
1000
Loaded 50 W to V
CC
V
V
Output HIGH Voltage (No Load)
Output LOW Voltage (No Load)
Output Source Resistance Qx or Qx
Input HIGH Voltage
V
−40
V
−10
V
mV
mV
W
OH
CC
CC
CC
V
CC
−1000
V
CC
−800
V
V
−650
OL
CC
R
40
1600
1500
100
40
50
60
TOUT
IH
V
V
V
V
CC
mV
mV
mV
W
Input LOW Voltage
−100
IL
CC
Differential Input Voltage (V
− V )
ILD
1600
60
ID
IHD
R
Input Termination Resistance D or D to V
TDx
50
TIN
x
x
LVTTL CONTROL INPUT PINS
V
V
Input HIGH Voltage (LVTTL Inputs)
Input LOW Voltage (LVTTL Inputs)
Input HIGH Current (LVTTL inputs)
Input LOW Current (LVTTL Inputs)
2000
mV
mV
mA
IH
IL
800
10
I
−10
−10
IH
IL
I
10
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. CML outputs require 50 W receiver termination resistors to V for proper operation.
CC
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NB4L858M
Table 6. AC CHARACTERISTICS V = 2.3 V to 3.6 V, GND = 0 V; (Note 4)
CC
−40°C
25°C
85°C
Min
Typ Max Min
Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
)
INPPmin
mV
OUTPP
f
in
f
in
f
in
≤ 2 GHz
≤ 3 GHz
≤ 3.5GHz
280
235
170
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
(See Figure 2)
f
Maximum Operating Data Rate
3
3
3
Gb/s
ps
DATA
t
t
,
Propagation Delay to Output Differential
D/D to Q/Q
PLH
PHL
220
350
0.5
450
1.0
220
350
0.5
450
1.0
220
350
0.5
450
1.0
t
t
SELyx to Valid Qyx Output (Note 9)
ns
ps
SWiITCH
SKEW
Within −Device Skew (Note 5)
Within −Device Skew (Note 6)
Device to Device Skew (Note 9)
12
25
100
12
25
100
12
25
100
t
RMS Random Clock Jitter (Note 8)
f
f
in
=2 GHz
=3 GHz
0.5
1.0
2.0
10
0.5
1.0
5.0
10
0.5
1.0
2.0
10
ps
JITTER
in
in
Peak−to−Peak Data Dependent Jitter f =2.5Gb/s
(Note 9)
f =3.2Gb/s
in
Crosstalk Induced RMS Jitter (Note 11)
0.5
0.5
0.5
V
Input Voltage Swing/Sensitivity
(Differential Configuration)
100
800
120
100
800
120
100
800
120
mV
ps
INPP
t
r
t
f
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q , Q
x x
80
80
80
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured by forcing V
(20% − 80%).
(MIN) from a 50% duty cycle clock source. All loading with an external R = 50 W to V . Input edge rates 40 ps
L CC
INPP
5. Worst−case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively),
when both outputs come from the same input.
6. Worst−case difference between QA and QB outputs, when DA or DB inputs are shorted.
7. Additive RMS jitter with 50% duty cycle input clock signal.
8. Additive peak−to−peak data dependent jitter with input NRZ data signal.
9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
10.LVTTL/LVCMOS input edge rate less than 1.5 ns
11. Data taken on the same device under identical condition.
400
−40°C
350
85°C
300
25°C
250
200
150
100
50
0
1
1.5
2
2.5
3
3.5
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature
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6
NB4L858M
Dx
V
V
= V (D ) − V (D )
IH X IL X
INPP
Dx
Qx
= V (Q ) − V (Q )
OUTPP
OH
X
OL
X
Qx
t
PHL
t
PLH
Figure 3. AC Reference Measurement
V
CC
50 W
50 W
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8057/D)
V
CC
V
CC
V
TDX
R
R
C
C
50 W
50 W
50 W
50 W
Q
Q
X
X
D
X
D
X
16 mA
GND
Output
GND
Input
Figure 5. CML Input and Output Structure
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NB4L858M
640 mV
MIN
Q
Q
X
X
320 mV
MIN
(Q − Q )
X
X
Q
Q
X
1000 mV
MAX
500 mV
MAX
X
(Q − Q )
X
X
Figure 6. CML Output Levels
ORDERING INFORMATION
Device
†
Package
Shipping
NB4L858MFAG
LQFP−32
(Pb−Free)
250 Units / Tray
NB4L858MFAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NB4L858M
PACKAGE DIMENSIONS
LQFP
FA SUFFIX
32−LEAD PLASTIC PACKAGE
CASE 873A−02
ISSUE B
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
−U−
V
−T−
AE
AE
P
B
B1
DETAIL Y
−Z−
V1
17
8
DETAIL Y
9
4X
NOTES:
0.20 (0.008) AC T−U
Z
9
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
S1
S
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETAIL AD
G
−AB−
−AC−
SEATING
PLANE
BASE
0.10 (0.004) AC
METAL
N
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
F
D
_
8X M
R
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
J
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
E
C
SECTION AE−AE
A
A1
B
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
3.500 BSC
7.000 BSC
3.500 BSC
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
W
_
Q
D
0.300
1.350
0.300
0.012
0.053
0.012
H
K
E
X
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
DETAIL AD
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5_
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
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NB4L858M
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your
local Sales Representative.
NB4L858M/D
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